CN109473394B - Wafer processing method - Google Patents

Wafer processing method Download PDF

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Publication number
CN109473394B
CN109473394B CN201811035752.6A CN201811035752A CN109473394B CN 109473394 B CN109473394 B CN 109473394B CN 201811035752 A CN201811035752 A CN 201811035752A CN 109473394 B CN109473394 B CN 109473394B
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wafer
cutting groove
front surface
sealing material
alignment
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CN109473394A (en
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铃木克彦
伴祐人
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Disco Corp
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Disco Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)

Abstract

A method for processing a wafer is provided. The method comprises the following steps: a 1 st cutting groove forming step of forming a 1 st cutting groove having a depth corresponding to the finished thickness of the device chip along the line to be divided from the front side of the wafer; a sealing step of sealing the front surface of the wafer with a sealing material; an alignment step of detecting an alignment mark by a visible light photographing member, and detecting a division scheduled line to be cut from the alignment mark; a 2 nd cutting groove forming step of forming a 2 nd cutting groove having a depth corresponding to the finished thickness in the sealing material in the 1 st cutting groove along the line to divide from the front side of the wafer; a protective member attaching step of attaching a protective member to the front surface of the wafer; and a dividing step of grinding the wafer from the back side of the wafer to a finished thickness to expose the 2 nd cutting groove, dividing the wafer into a front side and 4 device chips each having the side surrounded by the sealing material, and performing an alignment step while obliquely irradiating the region imaged by the visible light imaging means with light by the oblique light means.

Description

Wafer processing method
Technical Field
The present invention relates to a method of processing a wafer to form a 5S molded package.
Background
As a structure for realizing miniaturization and high-density mounting of various devices such as LSI and NAND-type flash memory, for example, a Chip Scale Package (CSP) in which a device chip is packaged in accordance with a chip size has been used in practical use, and is widely used in mobile phones, smart phones, and the like. In addition, in recent years, among the CSPs, a CSP in which not only the front surface of the chip but also the entire side surface is sealed with a sealing material, that is, a so-called 5S molded package has been developed and put into practical use.
The conventional 5S molded package is manufactured by the following steps.
(1) External connection terminals called devices (circuits) and bumps are formed on the front surface of a semiconductor wafer (hereinafter, sometimes referred to as a wafer in general).
(2) The wafer is cut along a line to be divided from the front side of the wafer to form a cut groove having a depth corresponding to the finished thickness of the device chip.
(3) The front side of the wafer was sealed with a sealing material containing carbon black.
(4) The backside of the wafer is ground to the finished thickness of the device chip to expose the sealing material in the kerf.
(5) Since the front surface of the wafer is sealed with a sealing material containing carbon black, the sealing material in the outer peripheral portion of the front surface of the wafer is removed to expose an alignment mark such as a target pattern, and alignment of the dividing lines to be cut is detected based on the alignment mark.
(6) According to the alignment, the wafer is cut along a dividing predetermined line from the front side of the wafer, thereby dividing into 5S molded packages whose front and entire sides are sealed with a sealing material.
As described above, since the front surface of the wafer is sealed with the sealing material containing carbon black, devices and the like formed on the front surface of the wafer are completely invisible to the naked eye. In order to solve this problem and to enable alignment, the applicant has developed the following technique as described in (5) above: an outer peripheral portion of the sealing material on the front surface of the wafer is removed to expose an alignment mark such as a target pattern, and a line to be cut is detected from the alignment mark to perform alignment (see japanese patent application laid-open nos. 2013-074021 and 2016-015438).
Patent document 1: japanese patent laid-open No. 2013-074021
Patent document 2: japanese patent laid-open publication 2016-015438
However, in the alignment method described in the above-mentioned publication, a step of removing the sealing material in the outer peripheral portion of the wafer by attaching a cutting tool having a wide width for edge trimming to the spindle instead of the cutting tool for cutting is required, and the replacement of the cutting tool and the removal of the sealing material in the outer peripheral portion by edge trimming take time and labor, which results in a problem of poor productivity.
Disclosure of Invention
The present invention has been made in view of the above-described points, and an object of the present invention is to provide a wafer processing method capable of performing an alignment process through a sealing material containing carbon black coated on a front surface of a wafer.
According to the present invention, there is provided a method for processing a wafer having devices each having a plurality of bumps formed in each region of a front surface divided by a plurality of dividing lines formed by intersecting, the method comprising: a 1 st cutting groove forming step of forming a 1 st cutting groove having a depth corresponding to a finished thickness of the device chip by a 1 st cutting tool having a 1 st thickness along the dividing line from the front surface side of the wafer; a sealing step of sealing the front surface of the wafer including the 1 st cutting groove with a sealing material after the 1 st cutting groove forming step is performed; an alignment step of detecting an alignment mark from the front surface side of the wafer through the sealing material by a visible light imaging means after the sealing step is performed, and detecting the dividing line to be cut from the alignment mark; a 2 nd cutting groove forming step of forming a 2 nd cutting groove having a depth corresponding to a finished thickness of a device chip in the sealing material in the 1 st cutting groove by a 2 nd cutting tool having a 2 nd thickness smaller than the 1 st thickness of the 1 st cutting tool along the dividing line from the front surface side of the wafer after the alignment step is performed; a protective member attaching step of attaching a protective member to the front surface of the wafer after the step of forming the 2 nd cutting groove; and a dividing step of grinding the wafer from the back side of the wafer to a finished thickness of the device chip to expose the 2 nd cutting groove, dividing the wafer into the device chips each having a front side and 4 sides surrounded by the sealing material, and performing the aligning step while obliquely irradiating the region photographed by the visible light photographing means with light by the oblique light means.
According to the wafer processing method of the present invention, the alignment mark formed on the wafer is detected by the visible light imaging means through the sealing material while the light is obliquely irradiated by the oblique light means, and the alignment can be performed based on the alignment mark, so that the alignment step can be easily performed without removing the sealing material at the outer peripheral portion of the front surface of the wafer as in the conventional technique.
Therefore, the 2 nd cutting groove can be formed from the front surface side of the wafer along the sealing material filled in the 1 st cutting groove formed to a depth corresponding to the finished thickness of the device chip, and thereafter the wafer is ground from the back surface side of the wafer to the finished thickness of the device chip to expose the 2 nd cutting groove, whereby the wafer can be divided into the device chips each having the front surface and the 4 sides sealed with the sealing material.
Drawings
Fig. 1 is a perspective view showing a semiconductor wafer.
Fig. 2 is a perspective view showing the 1 st cutting groove forming step.
Fig. 3 is a perspective view showing a sealing process.
Fig. 4 is a cross-sectional view showing an alignment process.
Fig. 5 (a) is a cross-sectional view showing the 2 nd cutting groove forming step, and fig. 5 (B) is an enlarged partial cross-sectional view of the wafer after the 2 nd cutting groove forming step is performed.
Fig. 6 (a) is a partial cross-sectional side view showing a dicing process, and fig. 6 (B) is an enlarged cross-sectional view of the device chip.
Description of the reference numerals
10: a cutting unit; 11: a semiconductor wafer; 13: dividing a predetermined line; 14. 14A: a cutting tool; 15: a device; 16: an alignment unit; 17: electrode bumps; 18: a photographing unit; 20: a sealing material; 23: a 1 st cutting groove; 25: a 2 nd cutting groove; 26: a grinding unit; 27: a device chip; 31: a tilting light member; 34: grinding the grinding wheel; 38: grinding tool.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Referring to fig. 1, there is shown a front side perspective view of a semiconductor wafer (hereinafter, sometimes simply referred to as a wafer) 11 suitable for processing by the processing method of the present invention.
A plurality of lines (streets) 13 for dividing are formed in a lattice shape on the front surface 11a of the semiconductor wafer 11. Devices 15 such as ICs and LSIs are formed in the respective regions partitioned by the vertical lines 13.
A plurality of electrode bumps (hereinafter, sometimes simply referred to as bumps) 17 are provided on the front surface of each device 15, and the wafer 11 has on the front surface thereof: a device region 19 formed with a plurality of devices 15 each having a plurality of bumps 17; and a peripheral remaining region 21 surrounding the device region 19.
In the wafer processing method according to the embodiment of the present invention, first, as step 1, step 1 is performed to form a 1 st cutting groove having a depth corresponding to the finished thickness of the device chip by a 1 st cutting tool having a 1 st thickness along the line 13 to be divided from the front side of the wafer 11. The 1 st cutting groove forming step will be described with reference to fig. 2.
The cutting unit 10 has: a cutting tool 14 detachably attached to the front end portion of the spindle 12; and an alignment unit 16 having a visible light photographing member (visible light photographing unit) 18. The visible light photographing unit 18 has a microscope and a camera that photograph with visible light.
Before the step of forming the 1 st cutting groove, first, the following alignment is performed: the visible light photographing unit 18 photographs the front surface of the wafer 11 with visible light, detects an alignment mark such as a target pattern formed on each device 15, and detects the dividing line 13 to be cut based on the alignment mark.
After alignment, a 1 st cutting groove forming step is performed, in which a cutting tool (1 st cutting tool) 14 rotating at a high speed in the direction of arrow R1 is cut from the front surface 11a side of the wafer 11 along a line to cut 13 at a depth corresponding to the finished thickness of the device chip, and a 1 st cutting groove 23 is formed along the line to cut 13 by performing machining feed in the direction of arrow X1 on a chuck table, not shown, which suctions and holds the wafer 11.
The 1 st cutting groove forming step is sequentially performed along the dividing line 13 extending in the 1 st direction while indexing the cutting unit 10 in a direction perpendicular to the machining feed direction X1 at intervals of the dividing line 13.
Next, after rotating the chuck table, not shown, by 90 °, the same 1 st cutting groove forming process is sequentially performed along the line 13 for dividing, which extends in the 2 nd direction perpendicular to the 1 st direction.
After the 1 st cutting groove forming step, a sealing step is performed, and as shown in fig. 3, a sealing material 20 is applied to the front surface 11a of the wafer 11, and the front surface 11a of the wafer 11 including the 1 st cutting groove 23 is sealed with the sealing material. Since the sealing material 20 has fluidity, the sealing material 20 is filled into the 1 st cutting groove 23 when the sealing process is performed.
The sealing material 20 comprises, by mass%, 10.3% of an epoxy resin or an epoxy resin+phenolic resin, 85.3% of a silica filler, 0.1 to 0.2% of carbon black, and 4.2 to 4.3% of other components. As the other component, for example, metal hydroxide, antimony trioxide, silica, and the like are included.
When the front surface 11a of the wafer 11 is covered with the sealing material 20 having such a composition to seal the front surface 11a of the wafer 11, the sealing material 20 is black due to the very small amount of carbon black contained in the sealing material 20, and thus it is generally difficult to see the front surface 11a of the wafer 11 through the sealing material 20.
Here, the carbon black is mixed into the sealing material 20 mainly for preventing electrostatic destruction of the device 15, and no sealing material containing no carbon black has been sold in the market.
The method of applying the sealing material 20 is not particularly limited, but it is preferable to apply the sealing material 20 up to the height of the bump 17, and then etch the sealing material 20 by etching to make the bump 17 come out.
After the sealing process, the following alignment process is performed: the front surface 11a of the wafer 11 is photographed by a visible light photographing means from the front surface 11a side of the wafer 11 so as to penetrate the sealing material 20, at least two alignment marks such as target patterns formed on the front surface of the wafer 11 are detected, and the dividing lines 13 to be cut are detected from these alignment marks.
This alignment process will be described in detail with reference to fig. 4. Before the alignment step is performed, the back surface 11b side of the wafer 11 is stuck to the dicing tape T whose outer peripheral portion is attached to the ring frame F.
In the alignment step, as shown in fig. 4, the wafer 11 is sucked and held by a chuck table 40 of a cutting device via a dicing tape T, and a sealing material 20 for sealing the front surface 11a of the wafer 11 is exposed upward. Then, the ring frame F is clamped and fixed by the clamp 42.
In the alignment step, the front surface 11a of the wafer 11 is photographed by a photographing element such as a CCD of the visible light photographing unit 18. However, since the sealing material 20 contains a silica filler, carbon black, or other component, and further the front surface of the sealing material 20 is uneven, even if the front surface 11a of the wafer 11 is photographed through the sealing material 20 by vertical irradiation by the visible light photographing unit 18, the photographed image becomes blurred, and it is difficult to detect the alignment mark such as the target pattern.
Therefore, in the alignment step of the present embodiment, in addition to the vertical irradiation of the visible light imaging unit 18, light can be obliquely irradiated from the oblique light member 31 to the imaging region, so that blurring of the captured image can be alleviated, and the alignment mark can be detected.
The light emitted from the inclined light member 31 is preferably white light, and the incident angle with respect to the front surface 11a of the wafer 11 is preferably in the range of 30 ° to 60 °. The visible light photographing unit 18 preferably has an exposure device (exposure) capable of adjusting exposure time or the like.
Next, the chuck table 40 is rotated θ so that a straight line connecting the alignment marks is parallel to the machining feed direction, and then the cutting unit 10 shown in fig. 2 is moved in a direction perpendicular to the machining feed direction X1 by a distance between the alignment mark and the center of the line to be cut 13, thereby detecting the line to be cut 13.
After the alignment step, a 2 nd cutting groove forming step is performed, and as shown in fig. 5 (a), a 2 nd cutting groove 25 having a depth corresponding to the finished thickness of the device chip is formed in the wafer 11 having the front surface 11a sealed with the sealing material 20 by the 2 nd cutting tool 14A having a smaller width than the width of the 1 st cutting tool 14 along the line to divide 13 from the front surface 11a side of the wafer 11.
After the 2 nd cutting groove forming step is sequentially performed along the line to divide 13 extending in the 1 st direction, the chuck table 40 is rotated by 90 °, and the 2 nd cutting groove forming step is sequentially performed along the line to divide 13 extending in the 2 nd direction perpendicular to the 1 st direction.
After the 2 nd cutting groove forming step, a protective member attaching step is performed to attach a protective member 22 such as a protective tape to the front surface 11a of the wafer 11. After the protective member attaching step, a dividing step is performed to grind the wafer 11 from the back surface 11b side of the wafer 11 to the finished thickness of the device chips, thereby exposing the 2 nd cutting grooves 25, and dividing the wafer 11 into the device chips 27 each having the front surface and 4 sides sealed with the sealing material 20.
This dividing process will be described with reference to fig. 6. The wafer 11 is sucked and held by a chuck table 24 of the grinding apparatus through a protective member 22 such as a front protective tape attached to the front surface 11a of the wafer 11.
The grinding unit 26 includes: a spindle 30 rotatably accommodated in the spindle housing 28 and rotationally driven by a motor not shown; a grinding wheel mount 32 fixed to the front end of the spindle 30; and a grinding wheel 34 detachably attached to the wheel mount 32. The grinding wheel 34 is composed of an annular wheel base 36 and a plurality of grinding tools 38 bonded to the outer periphery of the lower end of the wheel base 36.
In the dividing step, the chuck table 24 is rotated, for example, at 300rpm in the direction indicated by the arrow a, the grinding wheel 34 is rotated, for example, at 6000rpm in the direction indicated by the arrow b, and a grinding tool 38 of the grinding wheel 34 is brought into contact with the back surface 11b of the wafer 11 by driving a grinding unit feeding mechanism, not shown.
Then, the rear surface 11b of the wafer 11 is ground while the grinding wheel 34 is ground and fed downward by a predetermined amount at a predetermined grinding feed rate. While the thickness of the wafer 11 is measured by a contact or non-contact thickness gauge, the wafer 11 is ground to a predetermined thickness, for example, 100 μm, to expose the 2 nd cutting groove 25, and as shown in fig. 6 (B), the wafer 11 is divided into device chips 27 each having a front surface and 4 side surfaces surrounded by the sealing material 20.
The device chip 27 thus manufactured can be mounted on a motherboard by flip-chip bonding which inverts the front surface and the back surface of the device chip 27 to connect the bumps 17 with conductive pads of the motherboard.

Claims (1)

1. A method for processing a wafer having a plurality of bumps formed in each region of a front surface divided by a plurality of dividing lines formed by crossing each other,
the wafer processing method is characterized by comprising the following steps:
a 1 st cutting groove forming step of forming a 1 st cutting groove having a depth corresponding to a finished thickness of the device chip by a 1 st cutting tool having a 1 st thickness along the dividing line from the front surface side of the wafer;
a sealing step of sealing the front surface of the wafer including the 1 st cutting groove with a sealing material after the 1 st cutting groove forming step is performed;
an alignment step of detecting an alignment mark from the front surface side of the wafer through the sealing material by a visible light imaging means after the sealing step is performed, and detecting the dividing line to be cut from the alignment mark;
a 2 nd cutting groove forming step of forming a 2 nd cutting groove having a depth corresponding to a finished thickness of the device chip in the sealing material in the 1 st cutting groove by a 2 nd cutting tool having a 2 nd thickness smaller than the 1 st thickness of the 1 st cutting tool along the dividing line from the front surface side of the wafer after the alignment step is performed;
a protective member attaching step of attaching a protective member to the front surface of the wafer after the step of forming the 2 nd cutting groove; and
a dividing step of grinding the wafer from the back side of the wafer to a finished thickness of the device chips to expose the 2 nd cutting grooves, dividing the wafer into the device chips each having a front side and 4 sides surrounded by the sealing material after the protective member attaching step is performed,
the alignment step is performed while the visible light photographing means is vertically irradiated and the inclined light means is obliquely irradiated to the region photographed by the visible light photographing means.
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