KR20190032189A - Wafer processing method - Google Patents

Wafer processing method Download PDF

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KR20190032189A
KR20190032189A KR1020180104747A KR20180104747A KR20190032189A KR 20190032189 A KR20190032189 A KR 20190032189A KR 1020180104747 A KR1020180104747 A KR 1020180104747A KR 20180104747 A KR20180104747 A KR 20180104747A KR 20190032189 A KR20190032189 A KR 20190032189A
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wafer
encapsulant
divided
alignment
line
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KR1020180104747A
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KR102569620B1 (en
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가츠히코 스즈키
유리 반
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가부시기가이샤 디스코
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    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
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Abstract

The present invention provides a method of processing a wafer capable of performing an alignment process through an encapsulant containing carbon black coated on a wafer surface. A surface of a device wafer, on which devices are formed in a chip region partitioned by a plurality of division lines formed crosswise on the surface, is sealed with an encapsulant, and a plurality of bumps are formed in the chip region of the encapsulant. The wafer processing method includes: an alignment step of detecting an alignment mark by photographing a surface side of a device wafer through an encapsulant from the surface side of the wafer by an infrared photographing unit and detecting a line to be divided which is to be laser-processed based on the alignment mark; and, a dividing step of irradiating a laser beam having absorption property with respect to the encapsulant and a device wafer from the surface side of the wafer along the line to be divided and dividing the wafer into individual device chips having surfaces sealed with the encapsulant by performing the ablation process after the alignment step. The encapsulant has permeability for allowing infrared rays received by the infrared photographing unit to be transmitted.

Description

웨이퍼의 가공 방법{WAFER PROCESSING METHOD}[0001] WAFER PROCESSING METHOD [0002]

본 발명은 WL-CSP 웨이퍼의 가공 방법에 관한 것이다.The present invention relates to a method of processing a WL-CSP wafer.

WL-CSP (Wafer-level Chip Size Package) 웨이퍼란, 웨이퍼의 상태로 재배선층이나 전극 (금속 포스트) 을 형성 후, 표면측을 수지 봉지 (封止) 하고, 절삭 블레이드 등으로 각 패키지로 분할하는 기술로, 웨이퍼를 개편화한 패키지의 크기가 반도체 디바이스 칩의 크기가 되기 때문에, 소형화 및 경량화의 관점에서도 널리 채용되고 있다.Wafer-level Chip Size Package (WL-CSP) wafer is a wafer in which a rewiring layer or an electrode (metal post) is formed in the state of a wafer, the surface side is resin sealed and divided into individual packages by a cutting blade or the like Technology has been widely adopted from the viewpoints of downsizing and weight saving because the size of the package obtained by dividing the wafer becomes the size of the semiconductor device chip.

WL-CSP 웨이퍼의 제조 프로세스에서는, 복수의 디바이스가 형성된 디바이스 웨이퍼의 디바이스면측에 재배선층을 형성하고, 또한 재배선층을 통하여 디바이스 중의 전극에 접속하는 금속 포스트를 형성한 후, 금속 포스트 및 디바이스를 수지로 봉지한다.In a manufacturing process of a WL-CSP wafer, a re-wiring layer is formed on the device surface side of a device wafer on which a plurality of devices are formed, and a metal post to be connected to an electrode in the device is formed through a re- Lt; / RTI >

이어서, 봉지재를 박화 (薄化) 함과 함께 금속 포스트를 봉지재 표면에 노출시킨 후, 금속 포스트의 단면에 전극 범프라고 불리는 외부 단자를 형성한다. 그 후, 절삭 장치 등으로 WL-CSP 웨이퍼를 절삭하여 개개의 CSP 로 분할한다.Subsequently, the sealing material is thinned and the metal post is exposed on the surface of the sealing material, and then an external terminal called an electrode bump is formed in the end face of the metal post. Thereafter, the WL-CSP wafer is cut by a cutting device or the like to be divided into individual CSPs.

반도체 디바이스를 충격이나 습기 등으로부터 보호하기 위해, 봉지재로 봉지하는 것이 중요하다. 통상, 봉지재로서, 에폭시 수지 중에 SiC 로 이루어지는 필러를 혼입한 봉지재를 사용함으로써, 봉지재의 열팽창률을 반도체 디바이스 칩의 열팽창률에 가깝게 하여, 열팽창률의 차에 의해 생기는 가열시의 패키지의 파손을 방지하고 있다.In order to protect the semiconductor device from shock, moisture, etc., it is important to seal the semiconductor device with an encapsulating material. Normally, as a sealing material, an encapsulation material in which a filler made of SiC is mixed in an epoxy resin is used, so that the coefficient of thermal expansion of the encapsulation material is made close to the coefficient of thermal expansion of the semiconductor device chip, .

WL-CSP 웨이퍼는, 일반적으로 절삭 장치를 사용하여 개개의 CSP 로 분할된다. 이 경우, WL-CSP 웨이퍼는, 분할 예정 라인을 검출하기 위해서 이용하는 디바이스가 수지로 덮여 있기 때문에, 표면측으로부터 디바이스의 타깃 패턴을 검출할 수 없다.WL-CSP wafers are generally divided into individual CSPs using a cutting device. In this case, in the WL-CSP wafer, since the device used for detecting the line to be divided is covered with resin, the target pattern of the device can not be detected from the surface side.

그 때문에, WL-CSP 웨이퍼의 수지 상에 형성된 전극 범프를 타깃으로 하여 분할 예정 라인을 산출하거나, 수지의 상면에 얼라인먼트용의 타깃을 인쇄하는 등을 하여 분할 예정 라인과 절삭 블레이드의 얼라인먼트를 실시하고 있었다.For this purpose, the line to be divided is calculated using the electrode bumps formed on the resin of the WL-CSP wafer as a target, or the target for alignment is printed on the upper surface of the resin to align the line to be divided and the cutting blade there was.

그러나, 전극 범프나 수지 상에 인쇄된 타깃은 디바이스와 같이 고정밀도로는 형성되어 있지 않기 때문에, 얼라인먼트용의 타깃으로는 정밀도가 낮다는 문제가 있다. 따라서, 전극 범프나 인쇄된 타깃에 기초하여 분할 예정 라인을 산출했을 경우, 분할 예정 라인으로부터 벗어나 디바이스 부분을 절삭해 버릴 우려가 있었다.However, since the target printed on the electrode bump or the resin is not formed with high precision as in the device, there is a problem that precision is low as a target for alignment. Therefore, when the line to be divided is calculated based on the electrode bump or the printed target, the device portion may be cut off from the line to be divided.

그래서, 예를 들어 일본 공개특허공보 2013-74021호에서는, 웨이퍼의 외주에서 노출되는 디바이스 웨이퍼의 패턴을 기초로 얼라인먼트하는 방법이 제안되어 있다.Thus, for example, in Japanese Laid-Open Patent Publication No. 2013-74021, a method of aligning based on a pattern of a device wafer exposed on the periphery of a wafer has been proposed.

일본 공개특허공보 2013-074021호Japanese Laid-Open Patent Publication No. 2013-074021 일본 공개특허공보 2016-015438호Japanese Laid-Open Patent Publication No. 2016-015438

그러나, 일반적으로 웨이퍼의 외주에서는 디바이스 정밀도가 나빠, 웨이퍼의 외주에서 노출되는 패턴을 기초로 얼라인먼트를 실시하면, 분할 예정 라인과는 벗어난 위치에서 웨이퍼를 분할해 버릴 우려가 있는 데다가, 웨이퍼에 따라서는 디바이스 웨이퍼의 패턴이 외주에서 노출되어 있지 않은 것도 있다.However, in general, when alignment is performed on the basis of a pattern exposed on the outer periphery of the wafer because the accuracy of the device is poor on the outer periphery of the wafer, there is a possibility that the wafer is divided at a position deviated from the line to be divided, The pattern of the device wafer may not be exposed from the outer periphery.

본 발명은 이와 같은 점을 감안하여 이루어진 것으로, 그 목적으로 하는 점은, 웨이퍼 표면에 피복된 카본 블랙을 함유하는 봉지재를 통하여 얼라인먼트 공정을 실시 가능한 웨이퍼의 가공 방법을 제공하는 것이다.The object of the present invention is to provide a method of processing a wafer capable of performing an alignment process through an encapsulant containing carbon black coated on the wafer surface.

본 발명에 의하면, 표면에 교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 칩 영역에 각각 디바이스가 형성된 디바이스 웨이퍼의 표면이 봉지재로 봉지되고, 그 봉지재의 그 칩 영역에 각각 복수의 범프가 형성된 웨이퍼의 가공 방법으로서, 그 웨이퍼의 표면측으로부터 적외선 촬상 수단에 의해 그 봉지재를 투과하여 그 디바이스 웨이퍼의 표면측을 촬상하여 얼라인먼트 마크를 검출하고, 그 얼라인먼트 마크에 기초하여 레이저 가공해야 할 그 분할 예정 라인을 검출하는 얼라인먼트 공정과, 그 얼라인먼트 공정을 실시한 후, 그 웨이퍼의 표면측으로부터 그 분할 예정 라인을 따라 그 봉지재 및 그 디바이스 웨이퍼에 대해 흡수성을 갖는 파장의 레이저 빔을 조사하고, 어블레이션 가공에 의해 표면이 그 봉지재에 의해 봉지된 개개의 디바이스 칩으로 분할하는 분할 공정을 구비하고, 그 봉지재는, 그 적외선 촬상 수단이 수광하는 적외선이 투과하는 투과성을 갖는 것을 특징으로 하는 웨이퍼의 가공 방법이 제공된다.According to the present invention, the surface of a device wafer, on which a device is formed in a chip area divided by a plurality of lines to be divided formed on the surface, is sealed with an encapsulating material, and a plurality of bumps are formed in the chip area of the encapsulating material A method of processing a wafer, comprising the steps of: detecting the alignment mark by imaging the surface side of the device wafer by transmitting the sealing material through the infrared imaging unit from the front side of the wafer; An alignment step of detecting a predetermined line and an alignment step of irradiating the encapsulant and the device wafer with a laser beam having a water absorbing property along the line to be divided from the surface side of the wafer, Each device whose surface is sealed by the sealing material by machining And a sealing step of dividing the sealing material into chips. The sealing material has a permeability through which infrared rays received by the infrared imaging means are transmitted.

바람직하게는, 얼라인먼트 공정에서 사용하는 적외선 촬상 수단은 InGaAs 촬상 소자를 포함한다.Preferably, the infrared imaging means used in the alignment step includes an InGaAs imaging element.

본 발명의 웨이퍼의 가공 방법에 의하면, 적외선 촬상 수단이 수광하는 적외선이 투과하는 봉지재로 디바이스 웨이퍼의 표면을 봉지하고, 적외선 촬상 수단에 의해 봉지재를 투과하여 디바이스 웨이퍼에 형성된 얼라인먼트 마크를 검출하고, 얼라인먼트 마크에 기초하여 얼라인먼트를 실시할 수 있도록 했으므로, 종래와 같이 웨이퍼의 표면의 외주 부분의 봉지재를 제거하는 일 없이, 간단하게 얼라인먼트 공정을 실시할 수 있다.According to the method of processing a wafer of the present invention, the surface of a device wafer is sealed with an encapsulating material that infrared rays received by the infrared imaging unit transmits, and an encapsulating material is transmitted by the infrared imaging unit to detect an alignment mark formed on the device wafer , The alignment can be performed based on the alignment mark. Therefore, the alignment process can be simply performed without removing the sealing material on the outer peripheral portion of the wafer surface as in the conventional case.

따라서, 웨이퍼의 표면측으로부터 봉지재 및 디바이스 웨이퍼에 대해 흡수성을 갖는 파장의 레이저 빔을 분할 예정 라인을 따라 조사하고, 어블레이션 가공에 의해 웨이퍼를 개개의 디바이스 칩으로 분할할 수 있다.Therefore, it is possible to irradiate the encapsulant and the device wafer from the surface side of the wafer with a laser beam of a wavelength having an absorbing property along the line to be divided, and divide the wafer into individual device chips by ablation processing.

도 1(A) 는 WL-CSP 웨이퍼의 분해 사시도, 도 1(B) 는 WL-CSP 웨이퍼의 사시도이다.
도 2 는, WL-CSP 웨이퍼의 확대 단면도이다.
도 3 은, WL-CSP 웨이퍼를 외주부가 환상 (環狀) 프레임에 장착된 다이싱 테이프에 첩착 (貼着) 하는 모습을 나타내는 사시도이다.
도 4 는, 얼라인먼트 공정을 나타내는 단면도이다.
도 5(A) 는 분할 공정을 나타내는 단면도, 도 5(B) 는 분할 공정을 나타내는 확대 단면도이다.1 (A) is an exploded perspective view of a WL-CSP wafer, and FIG. 1 (B) is a perspective view of a WL-CSP wafer.
2 is an enlarged cross-sectional view of a WL-CSP wafer.
3 is a perspective view showing a state in which the outer peripheral portion of the WL-CSP wafer is attached (adhered) to a dicing tape mounted on an annular frame.
4 is a cross-sectional view showing an alignment process.
Fig. 5 (A) is a cross-sectional view showing a dividing step, and Fig. 5 (B) is an enlarged sectional view showing a dividing step.

이하, 본 발명의 실시형태를 도면을 참조하여 상세하게 설명한다. 도 1(A) 를 참조하면, WL-CSP 웨이퍼 (27) 의 분해 사시도가 나타나 있다. 도 1(B) 는 WL-CSP 웨이퍼 (27) 의 사시도이다.BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to Fig. 1 (A), an exploded perspective view of the WL-CSP wafer 27 is shown. 1 (B) is a perspective view of the WL-CSP wafer 27. FIG.

도 1(A) 에 나타낸 바와 같이, 디바이스 웨이퍼 (11) 의 표면 (11a) 에는 격자상으로 형성된 복수의 분할 예정 라인 (스트리트) (13) 에 의해 구획된 각 영역에 LSI 등의 디바이스 (15) 가 형성되어 있다.A device 15 such as an LSI or the like is formed on each surface of the surface 11a of the device wafer 11 by dividing the surface of the device wafer 11 by a plurality of lines 13 to be divided, Respectively.

디바이스 웨이퍼 (이하, 간단히 웨이퍼라고 약칭하는 경우가 있다) (11) 는 미리 이면 (11b) 이 연삭되어 소정의 두께 (100 ∼ 200 ㎛ 정도) 로 박화된 후, 도 2 에 나타내는 바와 같이, 디바이스 (15) 중의 전극 (17) 에 전기적으로 접속된 복수의 금속 포스트 (21) 를 형성한 후, 웨이퍼 (11) 의 표면 (11a) 측을 금속 포스트 (21) 가 매설하도록 봉지재 (23) 로 봉지한다.A device wafer 11 (hereinafter, simply referred to as a wafer) may be formed by grinding the back surface 11b in advance and thinning it to a predetermined thickness (about 100 to 200 占 퐉) A plurality of metal posts 21 electrically connected to the electrodes 17 of the wafers 11 are formed on the surface 11a of the wafer 11 so that the metal posts 21 are embedded with the sealing material 23 do.

봉지재 (23) 로는, 질량％ 로 에폭시 수지 또는 에폭시 수지 + 페놀 수지 10.3 ％, 실리카 필러 8.53 ％, 카본 블랙 0.1 ∼ 0.2 ％, 그 밖의 성분 4.2 ∼ 4.3 ％ 를 함유하는 조성으로 하였다. 그 밖의 성분으로는, 예를 들어, 금속 수산화물, 삼산화안티몬, 이산화규소 등을 함유한다.As the sealing material 23, a composition containing 10.3% by weight of epoxy resin or epoxy resin + phenol resin, 8.53% of silica filler, 0.1-0.2% of carbon black and 4.2-4.3% of other components was used as the mass%. Other components include, for example, metal hydroxides, antimony trioxide, silicon dioxide and the like.

이와 같은 조성의 봉지재 (23) 로 웨이퍼 (11) 의 표면 (11a) 을 피복하여 웨이퍼 (11) 의 표면 (11a) 을 봉지하면, 봉지재 (23) 중에 매우 소량 함유되어 있는 카본 블랙에 의해 봉지재 (23) 가 흑색이 되기 때문에, 봉지재 (23) 를 통하여 웨이퍼 (11) 의 표면 (11a) 을 보는 것은 통상 곤란하다.When the surface 11a of the wafer 11 is covered with the sealing material 23 having such a composition and the front surface 11a of the wafer 11 is sealed with the carbon black contained in a very small amount in the sealing material 23 It is usually difficult to see the surface 11a of the wafer 11 through the sealing material 23 because the sealing material 23 becomes black.

여기서 봉지재 (23) 중에 카본 블랙을 혼입시키는 것은, 주로 디바이스 (15) 의 정전 파괴를 방지하기 위해서이고, 현재로는 카본 블랙을 함유하지 않는 봉지재는 시판되어 있지 않다.The incorporation of carbon black into the encapsulant 23 is mainly intended to prevent the electrostatic breakdown of the device 15, and currently no encapsulant containing no carbon black is commercially available.

다른 실시형태로서, 디바이스 웨이퍼 (11) 의 표면 (11a) 상에 재배선층을 형성한 후, 재배선층 상에 디바이스 (15) 중의 전극 (17) 에 전기적으로 접속된 금속 포스트 (21) 를 형성하도록 해도 된다.A metal post 21 electrically connected to the electrode 17 of the device 15 may be formed on the rewiring layer after the rewiring layer is formed on the surface 11a of the device wafer 11 You can.

이어서, 단결정 다이아몬드로 이루어지는 바이트 절삭 공구를 갖는 평면 절삭 장치 (서피스 플레이너) 나 그라인더라고 불리는 연삭 장치를 사용하여 봉지재 (23) 를 박화한다. 봉지재 (23) 를 박화한 후, 예를 들어 플라즈마 에칭에 의해 금속 포스트 (21) 의 단면을 노출시킨다.Subsequently, the sealing material 23 is thinned by using a planar cutting apparatus (surface plateener) having a cutting tool made of single crystal diamond or a grinder called a grinder. After the encapsulation material 23 is thinned, the end face of the metal post 21 is exposed by, for example, plasma etching.

이어서, 노출된 금속 포스트 (21) 의 단면에 잘 알려진 방법에 의해 솔더 등의 금속 범프 (25) 를 형성하여, WL-CSP 웨이퍼 (27) 가 완성된다. 본 실시형태의 WL-CSP 웨이퍼 (27) 에서는, 봉지재 (23) 의 두께는 100 ㎛ 정도이다.Then, a metal bump 25 such as solder is formed on the end surface of the exposed metal post 21 by a well-known method to complete the WL-CSP wafer 27. In the WL-CSP wafer 27 of the present embodiment, the thickness of the sealing material 23 is about 100 占 퐉.

WL-CSP 웨이퍼 (27) 를 레이저 가공 장치로 가공함에 있어서, 도 3 에 나타내는 바와 같이, 바람직하게는, WL-CSP 웨이퍼 (27) 를 외주부가 환상 프레임 (F) 에 첩착된 점착 테이프로서의 다이싱 테이프 (T) 에 첩착한다. 이로써, WL-CSP 웨이퍼 (27) 는 다이싱 테이프 (T) 를 개재하여 환상 프레임 (F) 에 지지된 상태가 된다.3, the outer peripheral portion of the WL-CSP wafer 27 is preferably diced as an adhesive tape adhered to the annular frame (F) by processing the WL-CSP wafer 27 with a laser processing apparatus, And attached to the tape (T). As a result, the WL-CSP wafer 27 is supported by the annular frame F via the dicing tape T.

그러나, WL-CSP 웨이퍼 (27) 를 레이저 가공 장치로 가공함에 있어서, 환상 프레임 (F) 을 사용하지 않고, WL-CSP 웨이퍼 (27) 의 이면에 점착 테이프를 첩착하는 형태이어도 된다.However, in the case of processing the WL-CSP wafer 27 by a laser processing apparatus, an adhesive tape may be attached to the back surface of the WL-CSP wafer 27 without using the annular frame F. [

본 발명의 웨이퍼의 가공 방법에서는, 먼저, WL-CSP 웨이퍼 (27) 의 표면측으로부터 적외선 촬상 수단에 의해 봉지재 (23) 를 통하여 디바이스 웨이퍼 (11) 의 표면 (11a) 을 촬상하여, 디바이스 웨이퍼 (11) 의 표면에 형성되어 있는 적어도 2 개의 타깃 패턴 등의 얼라인먼트 마크를 검출하고, 이들 얼라인먼트 마크에 기초하여 레이저 가공해야 할 분할 예정 라인 (13) 을 검출하는 얼라인먼트 공정을 실시한다.In the method of processing a wafer of the present invention, first, the surface 11a of the device wafer 11 is imaged through the sealing material 23 by the infrared imaging unit from the front side of the WL-CSP wafer 27, Alignment marks such as at least two target patterns formed on the surface of the substrate 11 are detected and based on these alignment marks an alignment step of detecting a line to be divided 13 to be laser-processed is performed.

이 얼라인먼트 공정에 대해, 도 4 를 참조하여 상세하게 설명한다. 얼라인먼트 공정에서는, 도 4 에 나타내는 바와 같이, 다이싱 테이프 (T) 를 개재하여 레이저 가공 장치의 척 테이블 (10) 로 WL-CSP 웨이퍼 (27) 를 흡인 유지하고, 디바이스 웨이퍼 (11) 의 표면 (11a) 을 봉지하고 있는 봉지재 (23) 를 상방으로 노출시킨다. 그리고, 클램프 (12) 로 환상 프레임 (F) 을 클램프하여 고정시킨다.This alignment process will be described in detail with reference to FIG. 4, the WL-CSP wafer 27 is sucked and held by the chuck table 10 of the laser processing apparatus via the dicing tape T and the surface of the device wafer 11 11a of the sealing member 23 is exposed upward. Then, the annular frame (F) is clamped and fixed by the clamp (12).

이어서, 도시되지 않은 레이저 가공 장치의 촬상 유닛 (14) 의 적외선 촬상 소자로 WL-CSP 웨이퍼 (27) 의 봉지재 (23) 를 통하여 디바이스 웨이퍼 (11) 의 표면 (11a) 을 촬상한다. 봉지재 (23) 는, 촬상 유닛 (14) 의 적외선 촬상 소자가 수광하는 적외선이 투과하는 봉지재로 구성되어 있기 때문에, 적외선 촬상 소자에 의해 디바이스 웨이퍼 (11) 의 표면 (11a) 에 형성된 적어도 2 개의 타깃 패턴 등의 얼라인먼트 마크를 검출할 수 있다.Subsequently, the surface 11a of the device wafer 11 is imaged through the sealing material 23 of the WL-CSP wafer 27 with the infrared imaging device of the imaging unit 14 of the laser processing device (not shown). The sealing material 23 is formed of at least two pieces of the sealing material 23 formed on the front surface 11a of the device wafer 11 by the infrared ray imaging device because the sealing material 23 is composed of the sealing material through which the infrared rays received by the infrared ray imaging device of the image- It is possible to detect an alignment mark such as a target pattern.

바람직하게는, 적외선 촬상 소자로는 감도가 높은 InGaAs 촬상 소자를 채용한다. 바람직하게는, 촬상 유닛 (14) 은, 노광 시간 등을 조정할 수 있는 익스포저를 구비하고 있다.Preferably, an InGaAs imaging element having high sensitivity is employed as the infrared imaging element. Preferably, the image pickup unit 14 is provided with an exposer capable of adjusting the exposure time and the like.

이어서, 이들 얼라인먼트 마크를 연결한 직선이 가공 이송 방향과 평행이 되도록 척 테이블 (10) 을 θ 회전하고, 또한 얼라인먼트 마크와 분할 예정 라인 (13) 의 중심의 거리만큼 척 테이블 (10) 을 가공 이송 방향과 직교하는 방향으로 이동함으로써, 레이저 가공해야 할 분할 예정 라인 (13) 을 검출한다.Subsequently, the chuck table 10 is rotated by theta so that the straight line connecting these alignment marks is parallel to the processing transfer direction, and the chuck table 10 is processed and transported by the distance of the center of the alignment mark and the line to be divided 13 Direction, thereby detecting the line to be divided 13 to be laser-machined.

얼라인먼트 공정을 실시한 후, 도 5(A) 에 나타내는 바와 같이, WL-CSP 웨이퍼 (27) 의 표면측으로부터 분할 예정 라인 (13) 을 따라 레이저 가공 장치의 레이저 헤드 (집광기) (16) 로부터 봉지재 (23) 및 디바이스 웨이퍼 (11) 에 대해 흡수성을 갖는 파장 (예를 들어, 355 ㎚) 의 레이저 빔 (LB) 을 조사하고, 어블레이션 가공에 의해, 도 5(B) 에 나타내는 바와 같은 레이저 가공 홈 (29) 을 형성하고, WL-CSP 웨이퍼 (27) 를 표면이 봉지재 (23) 로 봉지된 개개의 디바이스 칩 (CSP) (31) 으로 분할한다.After the alignment process, as shown in Fig. 5 (A), from the surface side of the WL-CSP wafer 27 along the line to be divided 13, from the laser head (light condenser) 16 of the laser processing apparatus, A laser beam LB having a wavelength (for example, 355 nm) having an absorbing property is irradiated to the laser beam 23 and the device wafer 11, and the laser beam LB as shown in Fig. 5 (B) The groove 29 is formed and the WL-CSP wafer 27 is divided into individual device chips (CSP) 31 whose surfaces are sealed with the sealing material 23.

이 분할 공정을, 제 1 방향으로 신장하는 분할 예정 라인 (13) 을 따라 차례차례로 실시한 후, 척 테이블 (10) 을 90°회전하고, 제 1 방향에 직교하는 제 2 방향으로 신장하는 분할 예정 라인 (13) 을 따라 차례차례로 실시함으로써, 도 5(B) 에 나타낸 바와 같이, WL-CSP 웨이퍼 (27) 를 표면이 봉지재 (23) 에 의해 봉지된 개개의 CSP (31) 로 분할할 수 있다.This dividing step is sequentially performed along the dividing line 13 extending in the first direction and then the chuck table 10 is rotated by 90 degrees and the dividing line to be divided, which extends in the second direction perpendicular to the first direction, The WL-CSP wafer 27 can be divided into individual CSPs 31 whose surfaces are sealed by the sealing material 23, as shown in Fig. 5 (B) .

이와 같이 하여 제조한 디바이스 칩 (CSP) (31) 은, CSP (31) 의 표리를 반전하여 범프 (25) 를 마더보드의 도전 패드에 접속하는 플립 칩 본딩에 의해, 마더보드에 실장할 수 있다.The device chip (CSP) 31 thus manufactured can be mounted on the mother board by flip chip bonding in which the front and back of the CSP 31 are inverted to connect the bumps 25 to the conductive pads of the mother board .

11 디바이스 웨이퍼
13 분할 예정 라인
14 촬상 유닛
15 디바이스
16 레이저 헤드 (집광기)
21 금속 포스트
23 봉지재
25 범프
27 WL-CSP 웨이퍼
31 디바이스 칩 (CSP)11 device wafer
Line to be divided into 13 lines
14 image pickup unit
15 devices
16 laser head (concentrator)
21 Metal posts
23 bags
25 bump
27 WL-CSP wafer
31 Device chip (CSP)

Claims (2)

표면에 교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 칩 영역에 각각 디바이스가 형성된 디바이스 웨이퍼의 표면이 봉지재로 봉지되고, 상기 봉지재의 상기 칩 영역에 각각 복수의 범프가 형성된 웨이퍼의 가공 방법으로서,
상기 웨이퍼의 표면측으로부터 적외선 촬상 수단에 의해 상기 봉지재를 투과하여 상기 디바이스 웨이퍼의 표면측을 촬상하여 얼라인먼트 마크를 검출하고, 상기 얼라인먼트 마크에 기초하여 레이저 가공해야 할 상기 분할 예정 라인을 검출하는 얼라인먼트 공정과,
상기 얼라인먼트 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 상기 봉지재 및 상기 디바이스 웨이퍼에 대해 흡수성을 갖는 파장의 레이저 빔을 조사하고, 어블레이션 가공에 의해 표면이 상기 봉지재에 의해 봉지된 개개의 디바이스 칩으로 분할하는 분할 공정을 구비하고,
상기 봉지재는, 상기 적외선 촬상 수단이 수광하는 적외선이 투과하는 투과성을 갖는 것을 특징으로 하는 웨이퍼의 가공 방법.There is provided a method of processing a wafer in which a surface of a device wafer on which a device is formed in a chip area divided by a plurality of lines to be divided formed on the surface is sealed with an encapsulating material and a plurality of bumps are formed in each of the chip areas of the encapsulating material ,
An alignment mark is detected by imaging the surface side of the device wafer through the sealing material from the front surface side of the wafer by the infrared imaging means and an alignment for detecting the line to be divided to be subjected to laser processing based on the alignment mark, The process,
After the alignment step is performed, a laser beam of a wavelength having an absorbing property is applied to the encapsulant and the device wafer from the surface side of the wafer along the line to be divided along the dividing line, and the surface is abraded by the abrasive material And dividing the semiconductor chip into individual device chips sealed by the semiconductor chip,
Wherein the sealing material has permeability through which infrared rays received by the infrared imaging unit are transmitted. 제 1 항에 있어서,
상기 얼라인먼트 공정에서 사용하는 상기 적외선 촬상 수단은 InGaAs 촬상 소자를 포함하는 웨이퍼의 가공 방법.The method according to claim 1,
Wherein the infrared imaging means used in the alignment step includes an InGaAs imaging element.
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