TWI789422B - Wafer processing method - Google Patents

Wafer processing method Download PDF

Info

Publication number
TWI789422B
TWI789422B TW107131468A TW107131468A TWI789422B TW I789422 B TWI789422 B TW I789422B TW 107131468 A TW107131468 A TW 107131468A TW 107131468 A TW107131468 A TW 107131468A TW I789422 B TWI789422 B TW I789422B
Authority
TW
Taiwan
Prior art keywords
wafer
sealing material
cutting groove
sealing
modified layer
Prior art date
Application number
TW107131468A
Other languages
Chinese (zh)
Other versions
TW201913783A (en
Inventor
鈴木克彦
伴祐人
Original Assignee
日商迪思科股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商迪思科股份有限公司 filed Critical 日商迪思科股份有限公司
Publication of TW201913783A publication Critical patent/TW201913783A/en
Application granted granted Critical
Publication of TWI789422B publication Critical patent/TWI789422B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/38—Removing material by boring or cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
    • B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
    • B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/02—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by rotary tools, e.g. drills
    • B28D5/022—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by rotary tools, e.g. drills by cutting with discs or wheels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Dicing (AREA)
  • Laser Beam Processing (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

本發明係一種晶圓之加工方法，其課題為提供：通過含有被覆於晶圓表面之碳黑的封閉材而可實施校準工程之晶圓之加工方法者。 　　解決手段為於經由交叉所形成之複數的分割預定線所區劃之表面的各範圍，形成具有各複數的突起電極之裝置的晶圓之加工方法，其中，具備：自該晶圓的表面側，沿著該分割預定線，經由切削刀片而形成相當於裝置晶片之完成厚度之深度的切削溝的切削溝形成工程，和實施該切削溝形成工程之後，以封閉材而封閉包含該切削溝之該晶圓的表面之封閉工程，和實施該封閉工程之後，自該晶圓的背面側，至該裝置晶片之完成厚度為止，研削該晶圓而使該切削溝中之該封閉材露出之研削工程，和實施該研削工程之後，自該晶圓的表面側，經由可視光攝影手段而透過該封閉材，查出對準標記，依據該對準標記而查出欲雷射加工之該分割預定線的校準工程，和實施該校準工程之後，對於該封閉材而言，將具有透過性之波長的雷射束的集光點，定位於該切削溝中之該封閉材之內部，自該晶圓的表面側，沿著該分割預定線而照射雷射束，形成改質層於該封閉材之內部的改質層形成工程，和實施該改質層形成工程之後，於該切削溝中該封閉材，賦予外力而將該改質層作為分割起點，經由該封閉材而分割成圍繞有表面及4側面之各個的裝置晶片之分割工程；在該校準工程係於經由該可視光攝影手段而攝影之範圍，經由斜光手段而自傾斜照射光之同時而實施者。The present invention is a method of processing a wafer, and its object is to provide a method of processing a wafer which can perform alignment work by using a sealing material containing carbon black coated on the surface of the wafer. The solution is a wafer processing method for forming a device having a plurality of protruding electrodes in each range of the surface demarcated by a plurality of dividing lines formed by intersecting, wherein, from the surface side of the wafer, A cutting groove forming process of forming a cutting groove having a depth corresponding to the finished thickness of the device wafer through a cutting blade along the planned division line, and sealing the cutting groove including the cutting groove with a sealing material after performing the cutting groove forming process The sealing process of the surface of the wafer, and the grinding process of exposing the sealing material in the cutting groove by grinding the wafer from the back side of the wafer to the finished thickness of the device wafer after the sealing process is performed , and after implementing the grinding process, from the surface side of the wafer, the alignment mark is detected through the sealing material by means of visible light photography, and the planned division line to be laser processed is detected according to the alignment mark The calibration project, and after the calibration project is implemented, for the sealing material, the light-collecting point of the laser beam with a transparent wavelength is positioned inside the sealing material in the cutting groove, from the wafer The surface side of the modified layer is irradiated with a laser beam along the planned dividing line to form a modified layer forming process inside the sealing material, and after performing the modified layer forming process, the sealing material is formed in the cutting groove. material, giving external force to the modified layer as the starting point for division, and dividing the sealing material into device wafers surrounding the surface and 4 sides; The range is implemented by obliquely irradiating light by means of oblique light.

Description

晶圓之加工方法Wafer processing method

本發明係有關加工晶圓而形成5S模製封裝的晶圓之加工方法。The present invention relates to a processing method for processing wafers to form 5S molded and packaged wafers.

作為實現LSI或NAND型快閃記憶體等之各種裝置的小型化及高密度安裝化之構造，例如將以晶片尺寸而封裝化裝置晶片之晶片尺寸封裝(CSP)提供於實用，廣泛使用於行動電話或智慧型手機等。更且，近年係在此CSP之中，開發有不僅晶片的表面而將全側面，以封閉材進行封閉之CSP，所謂5S模製封裝而加以實用化。As a structure to realize the miniaturization and high-density mounting of various devices such as LSI and NAND flash memory, for example, the chip size package (CSP) that packages the device chip at the chip size is provided for practical use, and is widely used in mobile applications. phone or smartphone etc. Furthermore, in recent years, among these CSPs, a CSP in which not only the surface of the chip but also the entire side is sealed with a sealing material, a so-called 5S molded package, has been developed and put into practical use.

以往的5S模製封裝係經由以下的工程而加以製作。 　　(1) 於半導體晶圓(以下，有略稱為晶圓之情況)之表面，形成稱為裝置(電路)及突起電極之外部連接端子。 　　(2) 自晶圓的表面側，沿著分割預定線而切削晶圓，形成相當於裝置晶片的完成厚度之深度的切削溝。 　　(3) 以摻入碳黑之封閉材而封閉晶圓的表面。 　　(4) 將晶圓的背面側，研削至裝置晶片的完成厚度而使切削溝中之封閉材露出。 　　(5) 晶圓表面係因以摻入碳黑之封閉材而加以封閉之故，除去晶圓表面的外周部分之封閉材而使標靶圖案等之對準標記露出，依據此對準標記而實施查出欲切削之分割預定線的校準。 　　(6) 依據校準，自晶圓的表面側，沿著分割預定線而切削晶圓，分割成以封閉材而封閉表面及全側面之5S模製封裝。Conventional 5S molded packages are produced through the following processes. (1) External connection terminals called devices (circuits) and protruding electrodes are formed on the surface of semiconductor wafers (hereinafter, referred to as wafers for short). (2) From the surface side of the wafer, the wafer is cut along the planned dividing line to form cutting grooves with a depth equivalent to the finished thickness of the device wafer. (3) Seal the surface of the wafer with a sealing material doped with carbon black. (4) Grind the back side of the wafer to the finished thickness of the device wafer to expose the sealing material in the cutting groove. (5) The surface of the wafer is sealed with a sealing material doped with carbon black. The sealing material on the outer peripheral part of the wafer surface is removed to expose the alignment mark of the target pattern, etc., according to the alignment mark. Carry out the calibration to detect the planned dividing line to be cut. (6) According to the calibration, cut the wafer from the surface side of the wafer along the predetermined dividing line, and divide it into a 5S molded package with the sealing material sealing the surface and the whole side.

如上述，晶圓的表面係以包含碳黑之封閉材而加以封閉之故，形成於晶圓表面的裝置等係完全無法以肉眼看見。為了解決此問題而可進行校準，而如在上述(5)所記載地，本申請人係開發除去晶圓表面的封閉材之外周部分而使標靶圖案等之對準標記露出，依據此對準標記而查出欲切削之分割預定線，執行校準的技術(參照日本特開2013-074021號公報及日本特開2016-015438號公報)。 [先前技術文獻] [專利文獻]As mentioned above, since the surface of the wafer is sealed with a sealing material containing carbon black, devices and the like formed on the surface of the wafer cannot be seen with naked eyes at all. In order to solve this problem, alignment can be performed, and as described in (5) above, the present applicant has developed to remove the outer peripheral portion of the sealing material on the wafer surface to expose the alignment marks such as the target pattern, and based on this The technique of detecting the planned dividing line to be cut by using the quasi-mark and performing calibration (refer to Japanese Patent Laid-Open No. 2013-074021 and Japanese Patent Laid-Open No. 2016-015438). [Prior Art Document] [Patent Document]

[專利文獻1]日本特開2013-074021號公報 　　[專利文獻2]日本特開2016-015438號公報[Patent Document 1] Japanese Patent Laid-Open No. 2013-074021 [Patent Document 2] Japanese Patent Laid-Open No. 2016-015438

[發明欲解決之課題][Problem to be solved by the invention]

但在記載於上述公開公報之校準方法中，取代於切割用之切削刀片，而將磨邊修整用之寬度廣的切削刀片安裝於心軸，除去晶圓的外周部分之封閉材之工程則必要，而經由切削刀片的交換及磨邊修整，除去外周部分之封閉材的工時則耗費，有著生產性差的問題。However, in the calibration method described in the above publication, instead of the cutting blade for dicing, a wide cutting blade for edging and trimming is attached to the mandrel, and the process of removing the sealing material at the outer peripheral portion of the wafer is necessary. , and through the exchange of cutting blades and edge grinding, it takes a lot of man-hours to remove the sealing material at the outer peripheral part, and there is a problem of poor productivity.

本發明係有鑑於如此的點所作為的構成，而其目的係提供：通過包含被覆於晶圓表面的碳黑之封閉材而可實施校準工程之晶圓的加工方法者。 [為了解決課題之手段]The present invention is constituted in view of such points, and an object of the present invention is to provide a method for processing a wafer that can perform an alignment process by using a sealing material including carbon black coated on the surface of the wafer. [Means to solve the problem]

根據本發明時，提供：於經由交叉所形成之複數的分割預定線所區劃之表面的各範圍，形成具有各複數的突起電極之裝置的晶圓之加工方法，其特徵為具備：自該晶圓的表面側，沿著該分割預定線，經由切削刀片而形成相當於裝置晶片之完成厚度之深度的切削溝的切削溝形成工程，和實施該切削溝形成工程之後，以封閉材而封閉包含該切削溝之該晶圓的表面之封閉工程，和實施該封閉工程之後，自該晶圓的背面側，至該裝置晶片之完成厚度為止，研削該晶圓而使而使該切削溝中之該封閉材露出之研削工程，和實施該研削工程之後，自該晶圓的表面側，經由可視光攝影手段而透過該封閉材，查出對準標記，依據該對準標記而查出欲雷射加工之該分割預定線的校準工程，和實施該校準工程之後，對於該封閉材而言，將具有透過性之波長的雷射束的集光點，定位於該切削溝中之該封閉材之內部，自該晶圓的表面側，沿著該分割預定線而照射雷射束，形成改質層於該封閉材之內部的改質層形成工程，和實施該改質層形成工程之後，於該切削溝中該封閉材，賦予外力而將該改質層作為分割起點，經由該封閉材而分割成圍繞有表面及4側面之各個的裝置晶片之分割工程；該校準工程係於經由該可視光攝影手段而攝影之範圍，經由斜光手段而自傾斜照射光之同時而實施之晶圓的加工方法。 [發明效果]According to the present invention, there is provided: a wafer processing method for forming a device having a plurality of protruding electrodes in each range of the surface demarcated by a plurality of planned dividing lines formed by crossing, which is characterized by: On the surface side of the circle, a cutting groove forming process of forming a cutting groove having a depth equivalent to the complete thickness of the device wafer through a cutting blade along the planned division line, and after performing the cutting groove forming process, sealing the containing material with a sealing material The sealing process of the cutting groove on the surface of the wafer, and after performing the sealing process, grinding the wafer from the back side of the wafer to the finished thickness of the device wafer so that the cutting groove The grinding process where the sealing material is exposed, and after the grinding process is performed, the alignment marks are detected through the sealing material from the surface side of the wafer through visible light photography, and the desired lightning is detected based on the alignment marks. The calibration process of the predetermined division line of laser processing, and after the calibration process is carried out, for the sealing material, the light-collecting point of the laser beam with a transparent wavelength is positioned on the sealing material in the cutting groove Inside, from the surface side of the wafer, a laser beam is irradiated along the planned division line to form a modified layer forming process in the inside of the sealing member, and after performing the modified layer forming process, In the cutting groove, the sealing material is applied with an external force, and the modified layer is used as the starting point of division, and the sealing material is divided into the division process of each device chip surrounding the surface and 4 sides; the alignment process is performed through the sealing material. The scope of photographing by means of visible light photography is a wafer processing method that is carried out while irradiating light from oblique light by means of oblique light. [Invention effect]

當根據本發明之晶圓的加工方法時，因作為呈以斜光手段而自傾斜照射光之同時，經由可視光攝影手段而透過封閉材，查出形成於晶圓之對準標記，再依據對準標記而可實施校準之故，無須如以往，除去晶圓表面之外周部分的封閉材之情況，而可簡單地實施校準工程。When according to the processing method of the wafer of the present invention, since the light is irradiated obliquely by means of oblique light, the alignment mark formed on the wafer is detected through the sealing material through the means of visible light photography, and then according to the alignment mark Since the alignment can be performed by using the alignment mark, it is not necessary to remove the sealing material on the outer peripheral portion of the wafer surface as in the past, and the alignment process can be easily implemented.

因而，將對於封閉材而言具有透過性之波長的雷射束，定位於切削溝中之封閉材的內部，自晶圓的表面側，照射雷射束，形成改質層於切削溝中之封閉材的內部，可將該改質層作為分割起點，將晶圓，經由該封閉材而分割為圍繞表面及4側面之各個之裝置晶片者。Therefore, the laser beam having a wavelength that is transparent to the sealing material is positioned inside the sealing material in the cutting groove, and the laser beam is irradiated from the surface side of the wafer to form a modified layer in the cutting groove. Inside the sealing material, the modified layer can be used as a starting point for division, and the wafer can be divided into device chips surrounding the surface and four side surfaces through the sealing material.

以下，參照圖面而加以詳細說明本發明之實施形態。當參照圖1時，顯示適合於以本發明之加工方法而加工之半導體晶圓(以下，有單略稱為晶圓之情況)11之表面側斜視圖。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. When referring to FIG. 1 , it shows a front oblique view of a semiconductor wafer (hereinafter, simply referred to as a wafer) 11 suitable for processing by the processing method of the present invention.

在半導體晶圓11之表面11a中，將複數之分割預定線(切割道)13形成為格子狀，而對於經由正交之分割預定線13所區劃之各範圍，係形成有IC、LSI等之裝置15。On the surface 11a of the semiconductor wafer 11, a plurality of planned dividing lines (dicing lines) 13 are formed in a grid pattern, and for each area partitioned by the orthogonal planned dividing lines 13, IC, LSI, etc. are formed device 15.

對於各裝置15之表面係具有複數的電極凸塊(以下，有單略稱為突起電極之情況)17，而晶圓11係於其表面具備形成有備有各複數之突起電極17之複數的裝置15之裝置範圍19，和圍繞裝置範圍19之外周剩餘範圍21。The surface of each device 15 has a plurality of electrode bumps (hereinafter referred to simply as protruding electrodes) 17, and the wafer 11 has a plurality of protruding electrodes 17 formed on its surface. The device range 19 of the device 15 and the remaining range 21 around the device range 19 .

在本發明實施形態之晶圓的加工方法中，首先，作為第1工程，實施自晶圓11之表面側，沿著分割預定線13，經由切削刀片而形成相當於裝置晶片之完成厚度之深度的切削溝之切削溝形成工程。參照圖2而說明此切削溝形成工程。In the wafer processing method of the embodiment of the present invention, first, as the first process, from the surface side of the wafer 11, along the planned dividing line 13, through the cutting blade, the depth corresponding to the completed thickness of the device wafer is formed. The cutting groove formation project of the cutting groove. This cutting groove forming process will be described with reference to FIG. 2 .

切削單元10係具備：可拆裝於心軸12之前端部地加以安裝之切削刀片14，和具有可視光攝影手段(可視光攝影單元)18之校準單元16。可視光攝影單元18係具有以可視光攝影之顯微鏡及攝影機。The cutting unit 10 includes: a cutting blade 14 detachably attached to the front end of the spindle 12 ; and an alignment unit 16 having a visible light photography means (visible light photography unit) 18 . The visible light photography unit 18 is provided with a microscope and a camera for taking visible light photography.

在實施切削溝形成工程之前，首先由攝影單元18，以可視光而攝影晶圓11之表面，查出形成於各裝置15之標靶圖案等之對準標記，實施依據此對準標記而查出欲切削之分割預定線13的校準。Before implementing the cutting groove formation process, firstly, the imaging unit 18 photographs the surface of the wafer 11 with visible light, detects the alignment marks formed on the target patterns of each device 15, and performs inspection based on the alignment marks. Calibration of the planned dividing line 13 to be cut.

校準實施後，使高速旋轉於箭頭R1方向之切削刀片14，自晶圓11的表面11a側，沿著分割預定線13而切入至相當於裝置晶片之完成厚度之深度，經由將吸引保持晶圓11之未圖示之夾盤加工傳送至箭頭X1方向之時，實施沿著分割預定線13而形成切削溝23之切削溝形成工程。After the calibration is implemented, the cutting blade 14 rotating at high speed in the direction of the arrow R1 is cut from the surface 11a side of the wafer 11 along the planned dividing line 13 to a depth equivalent to the completed thickness of the device wafer, and the wafer is held by suction. 11. When the not-shown chuck processing is transferred to the arrow X1 direction, the cutting groove forming process of forming the cutting groove 23 along the planned dividing line 13 is carried out.

將此切削溝形成工程，各分割預定線13之間距算出傳送切削單元10於與加工傳送方向X1正交之方向的同時，沿著伸長於第1方向之分割預定線13而依序實施。The cutting groove forming process is carried out sequentially along the planned dividing lines 13 extending in the first direction while the distance between the planned dividing lines 13 is calculated and the cutting unit 10 is carried out in a direction perpendicular to the processing conveying direction X1.

接著，90°旋轉未圖示之夾盤之後，沿著伸長於正交於第1方向之第2方向的分割預定線13，依序實施同樣之切削溝形成工程。Next, after the chuck (not shown) is rotated by 90°, the same cutting groove forming process is sequentially carried out along the planned dividing line 13 extending in the second direction perpendicular to the first direction.

實施切削溝形成工程之後，如圖3所示，塗佈封閉材20於晶圓11之表面11a，實施以封閉材而封閉包含切削溝23之晶圓11的表面11a之封閉工程。封閉材20係有流動性之故，當實施封閉工程時，於切削溝23中，填充有封閉材20。After the groove formation process is performed, as shown in FIG. 3 , the sealing material 20 is coated on the surface 11 a of the wafer 11 , and the sealing process of sealing the surface 11 a of the wafer 11 including the groove 23 with the sealing material is performed. Because the sealing material 20 has fluidity, the cutting groove 23 is filled with the sealing material 20 when the sealing work is carried out.

作為封閉材20係作成以質量%，包含環氧樹脂或環氧樹脂+苯酚樹脂10.3%、二氧化矽填充料85.3%、碳黑0.1~0.2%、其他成分4.2~4.3%之組成。作為其他的成分係例如，包含金屬氫氧化物，三氧化二銻，二氧化矽等。The sealing material 20 is made by mass %, including 10.3% of epoxy resin or epoxy resin + phenol resin, 85.3% of silica filler, 0.1-0.2% of carbon black, and 4.2-4.3% of other components. Other components include, for example, metal hydroxides, antimony trioxide, silicon dioxide, and the like.

由如此組成之封閉材20而被覆晶圓11的表面11a，封閉晶圓11的表面11a時，經由極少量含於封閉材20中之碳黑而封閉材20成為黑色之故，通過封閉材20而看到晶圓11的表面11a之情況係通常為困難。The surface 11a of the wafer 11 is covered by the sealing material 20 composed in this way, and when the surface 11a of the wafer 11 is sealed, the sealing material 20 becomes black due to a very small amount of carbon black contained in the sealing material 20, and the sealing material 20 It is generally difficult to see the surface 11 a of the wafer 11 .

在此，使碳黑混入於封閉材20中之情況係主要為了防止裝置15之靜電破壞，而目前未有市售未含有碳黑之封閉材。Here, mixing carbon black into the sealing material 20 is mainly to prevent electrostatic breakdown of the device 15, and currently there is no sealing material that does not contain carbon black on the market.

封閉材20之塗佈方法係未特別加以限定，但塗佈封閉材20至突起電極17之高度為止者為佳，接著，經由蝕刻而蝕刻封閉材20，進行突起電極17之露出。The method of coating the sealing material 20 is not particularly limited, but it is preferable to coat the sealing material 20 up to the height of the protruding electrodes 17, and then etch the sealing material 20 by etching to expose the protruding electrodes 17.

實施封閉工程之後，自晶圓11的背面11b側至裝置晶片之完成厚度為止，研削晶圓11，實施使第1切削溝23中之封閉材20露出的研削工程。After the sealing process is performed, the wafer 11 is ground from the back surface 11b side of the wafer 11 to the finished thickness of the device wafer, and the grinding process is performed to expose the sealing material 20 in the first cutting groove 23 .

參照圖4而說明此研削工程。貼著表面保護膠帶22於晶圓11的表面11a，由研削裝置之夾盤24，藉由表面保護膠帶22而吸引保持晶圓11。This grinding process will be described with reference to FIG. 4 . The surface protection tape 22 is attached to the surface 11 a of the wafer 11 , and the wafer 11 is sucked and held by the chuck 24 of the grinding device through the surface protection tape 22 .

研削單元26係包含：經由可旋轉於主軸套28中地加以收容而未圖示之馬達，進行旋轉驅動之心軸30，和固定於心軸30之前端的盤座32，和可拆裝於盤座32地加以裝設之研削砂輪34。研削砂輪34係由環狀之轉輪基台36，和固定安裝於轉輪基台36之下端外周之複數的研磨石38而加以構成。The grinding unit 26 includes: a motor that is rotatably accommodated in the main shaft sleeve 28 and is not shown in the figure, a spindle 30 that is driven to rotate, and a disk seat 32 that is fixed on the front end of the spindle 30, and a disk base that can be disassembled on the disk. The grinding wheel 34 installed on the seat 32. Grinding grinding wheel 34 is made up of ring-shaped running wheel base 36 and a plurality of grinding stones 38 fixedly installed on the outer periphery of the lower end of running wheel base 36 .

在研削工程中，將夾盤24，於以箭頭a所示之方向，例如以300rpm進行旋轉同時，使研削砂輪34，於以箭頭b所示之方向，例如以6000rpm進行旋轉同時，驅動未圖示之研削單元傳送機構，使研削砂輪34之研磨石38接觸於晶圓11之背面11b。In the grinding process, the chuck 24 is rotated at, for example, 300 rpm in the direction shown by the arrow a, while the grinding wheel 34 is rotated at, for example, 6000 rpm in the direction shown by the arrow b, and is driven (not shown) The conveying mechanism of the grinding unit shown makes the grinding stone 38 of the grinding wheel 34 contact the back surface 11 b of the wafer 11 .

並且，將研削砂輪34，以特定的研削傳送速度，於下方進行特定量研削傳送之同時，研削晶圓11之背面11b。以接觸式或非接觸式之厚度測定計而測定晶圓11的厚度同時，將晶圓11研削為特定的厚度，例如100μm，使埋設於切削溝23中的封閉材20露出。In addition, the grinding wheel 34 grinds the back surface 11b of the wafer 11 while carrying out a specific amount of grinding transfer downward at a specific grinding transfer speed. While measuring the thickness of the wafer 11 with a contact or non-contact thickness gauge, the wafer 11 is ground to a specific thickness, eg, 100 μm, to expose the sealing material 20 buried in the cutting groove 23 .

實施研削工程之後，自晶圓11的表面11a側，經由可視光攝影手段而通過封閉材20，攝影晶圓11的表面11a，查出形成於晶圓11之表面11a的至少2個之標靶圖案等之對準標記，實施依據此等之對準標記而查出欲雷射加工之分割預定線13之校準工程。After the grinding process is carried out, the surface 11a of the wafer 11 is photographed from the surface 11a side of the wafer 11 through the sealing material 20 by means of visible light photography, and at least two targets formed on the surface 11a of the wafer 11 are detected. For alignment marks such as patterns, a calibration process is performed to detect the planned division line 13 to be laser-processed based on these alignment marks.

對於此校準工程，參照圖5而詳細說明。在實施校準工程之前，在晶圓11的背面11b側，貼著於裝設外周部於環狀框體F之切割膠帶T。This calibration process will be described in detail with reference to FIG. 5 . Before the alignment process is performed, the dicing tape T attached to the ring frame F on the outer periphery of the wafer 11 is attached to the rear surface 11b side of the wafer 11 .

在校準工程中，如圖5所示，藉由切割膠帶T，以雷射加工裝置之夾盤40而吸引保持晶圓11，使封閉晶圓11的表面11a之封閉材20露出於上方。並且，以夾鉗42而夾鉗固定環狀框體F。In the alignment process, as shown in FIG. 5 , the wafer 11 is sucked and held by the chuck 40 of the laser processing device by dicing the tape T, so that the sealing material 20 sealing the surface 11a of the wafer 11 is exposed above. And, the ring-shaped frame body F is clamped and fixed by clamps 42 .

在校準工程中，以與切削裝置之可視光攝影單元18同樣之雷射加工裝置的可視光攝影單元18A之CCD等之攝影元件，而攝影晶圓11之表面11a。但，對於封閉材20中係含有二氧化矽填充料，碳黑等之成分，而更且對於封閉材20之表面係有凹凸之故，在可視光攝影單元18A之垂直照明中，即使透過封閉材20而攝影晶圓11的表面11a，攝影畫像亦成為散焦，而查出標靶圖案等之對準標記之情況則為困難。In the calibration process, the surface 11a of the wafer 11 is photographed with an imaging element such as a CCD of the visible light imaging unit 18A of the laser processing device similar to the visible light imaging unit 18 of the cutting device. However, since the sealing material 20 contains silicon dioxide filler, carbon black, etc., and the surface of the sealing material 20 has unevenness, in the vertical illumination of the visible light photography unit 18A, even through the sealing The material 20 and the surface 11a of the wafer 11 are photographed, and the photographed image also becomes defocused, and it is difficult to detect alignment marks such as target patterns.

因此，在本實施形態之校準工程中，加上於可視光攝影單元18A之垂直照明而自斜光手段31，從傾斜照射光於攝影範圍，改善攝影畫像之散焦，作為可查出對準標記。Therefore, in the calibration project of this embodiment, the oblique light means 31 is added to the vertical illumination of the visible light photography unit 18A, and the light is irradiated to the photographing range from an oblique angle, so as to improve the defocus of the photographed image and serve as a detectable alignment mark. .

自斜光手段31照射的光係白色光為佳，而對於晶圓11的表面11a之入射角係30°~60°之範圍內為佳。理想係可視光攝影單元18A係具備可調整曝光時間等之曝光部。The light irradiated from the oblique light means 31 is preferably white light, and the incident angle to the surface 11 a of the wafer 11 is preferably in the range of 30° to 60°. Ideally, the visible light imaging unit 18A is equipped with an exposure unit capable of adjusting exposure time and the like.

接著，連結此等之對準標記的直線則呈與加工傳送方向平行地，θ旋轉夾盤40，更且經由僅對準標記與分割預定線13之中心的距離，將圖2所示之切削單元10移動於與加工傳送方向X1正交之方向之時，查出欲切削之分割預定線13。Then, the straight line connecting these alignment marks is parallel to the processing transmission direction, θ rotates the chuck 40, and only the distance between the alignment marks and the center of the dividing line 13 is used to cut the cutting surface shown in FIG. When the unit 10 moves in the direction perpendicular to the processing conveying direction X1, the planned dividing line 13 to be cut is detected.

實施校準工程之後，如圖6(A)所示，自晶圓11的表面11a側，沿著分割預定線13，自雷射加工裝置之雷射頭(集光器)46，將對於封閉材20而言具有透過性之波長(例如，1064nm)的雷射束LB，定位其集光點於切削溝23中的封閉材20之內部而進行照射，經由將夾盤40加工傳送於箭頭X1方向之時，實施形成如圖6(B)所示之改質層25於切削溝23中之封閉材20的內部之改質層形成工程。After implementing the calibration project, as shown in FIG. 6(A), from the surface 11a side of the wafer 11, along the planned dividing line 13, from the laser head (collector) 46 of the laser processing device, the sealing material For 20, the laser beam LB with a transparent wavelength (for example, 1064nm) is positioned at the inside of the sealing material 20 in the cutting groove 23 for irradiation, and the chuck 40 is processed and transmitted in the direction of the arrow X1 At this time, the modified layer forming process of forming the modified layer 25 inside the sealing material 20 in the cutting groove 23 as shown in FIG. 6(B) is carried out.

將此改質層形成工程，沿著伸長於第1方向之分割預定線13而依序實施之後，90°旋轉夾盤40，沿著伸長於正交於第1方向之第2方向的分割預定線13而依序實施。After the modified layer forming process is carried out sequentially along the planned dividing line 13 extending in the first direction, the chuck 40 is rotated at 90° along the planned dividing line 13 extending in the second direction perpendicular to the first direction. Line 13 is implemented sequentially.

改質層形成工程實施後，使用圖7所示之分割裝置50而賦予外力至晶圓11，實施將晶圓11分割為各個裝置晶片27之分割步驟。圖7所示之分割裝置50係具備：保持環狀框體F之框體保持手段52，和擴張裝設於由框體保持手段52所保持之環狀框體F的切割膠帶T之膠帶擴張手段54。After the modified layer formation process is performed, an external force is applied to the wafer 11 using the dividing device 50 shown in FIG. 7 , and a dividing step of dividing the wafer 11 into individual device chips 27 is performed. The dividing device 50 shown in FIG. 7 is equipped with: a frame body holding means 52 for holding the annular frame body F, and a tape expansion device for expanding the dicing tape T of the annular frame body F held by the frame body holding means 52. means54.

框體保持手段52係由環狀之框體保持構件56，和作為配設於框體保持構件56之外周的固定手段之複數的夾鉗58加以構成。框體保持構件56之上面係形成載置環狀框體F之載置面56a，而於此載置面56a上，載置有環狀框體F。The frame holding means 52 is composed of an annular frame holding member 56 and a plurality of clamps 58 as fixing means arranged on the outer periphery of the frame holding member 56 . On the upper surface of the frame holding member 56, a mounting surface 56a on which the annular frame F is mounted is formed, and the annular frame F is mounted on the mounting surface 56a.

並且，載置於載置面56a上之環狀框體F係經由夾鉗58而固定於框體保持手段52。如此所構成之框體保持手段52係經由膠帶擴張手段54而可移動於上下方向地加以支持。And the ring-shaped frame body F mounted on the mounting surface 56a is fixed to the frame body holding means 52 via the clamp 58. As shown in FIG. The frame holding means 52 constituted in this way is supported vertically through the tape expanding means 54 so as to be movable.

膠帶擴張手段54係具備：配設於環狀之框體保持構件56的內側之擴張筒體60。擴張筒體50之上端係由蓋52而加以閉鎖。此擴張筒體60係具有較環狀框體F之內徑為小，而較貼著於裝設於環狀框體F之切割膠帶T的晶圓11之外徑為大的內徑。The adhesive tape expansion means 54 is equipped with the expansion cylinder 60 arrange|positioned inside the ring-shaped frame body holding member 56. As shown in FIG. The upper end of the expansion cylinder 50 is locked by a cover 52 . The expansion cylinder 60 has a smaller inner diameter than the inner diameter of the annular frame F, and a larger inner diameter than the outer diameter of the wafer 11 attached to the dicing tape T mounted on the annular frame F.

擴張筒體60係具有一體性地形成於其下端之支持突緣64。膠帶擴張手段54係更且具備移動環狀之框體保持構件56於上下方向之驅動手段66。此驅動手段66係由配設於支持突緣64上之複數的空氣壓缸68所構成，而此活塞負荷部70係連結於框體保持構件56之下面。The expansion barrel 60 has a support flange 64 integrally formed at its lower end. The tape expanding means 54 is further equipped with a drive means 66 for moving the ring-shaped frame holding member 56 in the up and down direction. The driving means 66 is composed of a plurality of air cylinders 68 arranged on the supporting flange 64 , and the piston load part 70 is connected to the lower surface of the frame holding member 56 .

由複數的空氣壓缸68所構成之驅動手段66係將環狀的框體保持構件56，在成為與其載置面56a則為擴張筒體60之上端的蓋62之表面略同一高度之基準位置，和較擴張筒體60之上端為特定量下方的擴張位置之間，移動於上下方向。The driving means 66 constituted by a plurality of air cylinders 68 sets the ring-shaped frame body holding member 56 at a reference position that is substantially at the same height as the surface of the cover 62 at the upper end of the expansion cylinder 60 with its mounting surface 56a. , and between the expansion position which is lower than the upper end of the expansion cylinder 60 by a certain amount, and moves in the up and down direction.

對於使用如以上所構成之分割裝置50而實施之晶圓11的分割工程，參照圖8而加以說明。如圖8(A)所示，將藉由切割膠帶T而支持晶圓11之環狀框體F，載置於框體保持構件56之載置面56a上，再經由夾鉗58而固定於框體保持構件56。此時，框體保持構件56係定位於其載置面56a則成為與擴張筒體60之上端略同一高度的基準位置。The process of dividing wafer 11 performed using dividing apparatus 50 configured as above will be described with reference to FIG. 8 . As shown in FIG. 8(A), the ring-shaped frame F supporting the wafer 11 by the dicing tape T is placed on the mounting surface 56a of the frame holding member 56, and then fixed on the frame through the clamp 58. The frame holding member 56 . At this time, the frame holding member 56 is positioned at a reference position at which the mounting surface 56 a is substantially at the same height as the upper end of the expansion cylinder 60 .

接著，驅動空氣壓缸68而將框體保持構件56，下降於圖8(B)所示之擴張位置。經由此，下降固定於框體保持構件56之載置面56a上之環狀框體F之故，而裝設於環狀框體F之切割膠帶T係抵接於擴張筒體60之上端緣而主要擴張於半徑方向。Next, the air cylinder 68 is driven to lower the frame holding member 56 to the expanded position shown in FIG. 8(B). Through this, the annular frame F fixed on the mounting surface 56a of the frame holding member 56 is lowered, and the dicing tape T installed on the annular frame F abuts against the upper edge of the expansion cylinder 60 And mainly expand in the radial direction.

其結果，對於貼著於切割膠帶T之晶圓11係放射狀地產生拉伸力作用。如此，對於晶圓11，放射狀地產生拉伸力作用時，沿著分割預定線13而形成於封閉材20中之改質層25則成為分割起點，而晶圓11則沿著改質層25，如圖9之擴大圖所示地加以割斷，再經由封閉材20而分割為圍繞表面及4側面之各個的裝置晶片27。As a result, a tensile force acts radially on the wafer 11 attached to the dicing tape T. As shown in FIG. In this way, when a tensile force acts radially on the wafer 11, the modified layer 25 formed in the sealing member 20 along the planned dividing line 13 becomes the starting point for dividing, and the wafer 11 is formed along the modified layer. 25, as shown in the enlarged view of FIG.

10‧‧‧切削單元11‧‧‧半導體晶圓13‧‧‧分割預定線14‧‧‧切削刀片15‧‧‧裝置16‧‧‧校準單元17‧‧‧電極凸塊18、18A‧‧‧攝影單元20‧‧‧封閉材23‧‧‧切削溝25‧‧‧改質層26‧‧‧研削單元27‧‧‧裝置晶片31‧‧‧斜光手段34‧‧‧研削砂輪38‧‧‧研磨石46‧‧‧雷射頭(集光器)50‧‧‧分割裝置10‧‧‧cutting unit 11‧‧‧semiconductor wafer 13‧‧‧separation line 14‧‧‧cutting blade 15‧‧‧device 16‧‧‧calibration unit 17‧‧‧electrode bump 18, 18A‧‧‧ Camera unit 20‧‧‧sealing material 23‧‧‧cutting groove 25‧‧‧modified layer 26‧‧‧grinding unit 27‧‧‧device wafer 31‧‧‧oblique light means 34‧‧‧grinding grinding wheel 38‧‧‧grinding Stone 46‧‧‧laser head (light collector) 50‧‧‧separation device

圖1係半導體晶圓之斜視圖。 　　圖2係顯示切削溝形成工程之斜視圖。 　　圖3係顯示封閉工程之斜視圖。 　　圖4係顯示研削工程之一部分剖面側面圖。 　　圖5係顯示校準工程之剖面圖。 　　圖6(A)係顯示改質層形成工程的剖面圖，圖6(B)係顯示改質層形成工程之擴大剖面圖。 　　圖7係分割裝置之斜視圖。 　　圖8係顯示分割步驟之剖面圖。 　　圖9係分割步驟實施後之晶圓的一部分擴大剖面圖。Fig. 1 is a perspective view of a semiconductor wafer. Figure 2 is an oblique view showing the cutting groove formation process. Figure 3 is an oblique view showing the closed works. Figure 4 is a side view showing a partial section of the grinding process. Figure 5 is a sectional view showing the calibration works. Fig. 6(A) is a sectional view showing the process of forming the modified layer, and Fig. 6(B) is an enlarged sectional view showing the process of forming the modified layer. Figure 7 is a perspective view of the splitting device. Figure 8 is a cross-sectional view showing the segmentation step. Figure 9 is an enlarged cross-sectional view of a part of the wafer after the dividing step is performed.

11‧‧‧半導體晶圓 11‧‧‧semiconductor wafer

11a‧‧‧表面 11a‧‧‧surface

18‧‧‧攝影單元 18‧‧‧Photography unit

20‧‧‧封閉材 20‧‧‧sealing material

31‧‧‧斜光手段 31‧‧‧oblique light means

40‧‧‧夾盤 40‧‧‧Chuck

42‧‧‧夾鉗 42‧‧‧Clamp

F‧‧‧環狀框體 F‧‧‧ring frame

T‧‧‧切割膠帶 T‧‧‧Cutting Tape

Claims (1)

一種晶圓之加工方法，係於經由交叉所形成之複數的分割預定線所區劃之表面的各範圍，形成具有各複數的突起電極之裝置的晶圓之加工方法，其特徵為具備： 　　自該晶圓的表面側，沿著該分割預定線，經由切削刀片而形成相當於裝置晶片之完成厚度之深度的切削溝的切削溝形成工程， 　　和實施該切削溝形成工程之後，以封閉材而封閉包含該切削溝之該晶圓的表面之封閉工程， 　　和實施該封閉工程之後，自該晶圓的背面側至該裝置晶片之完成厚度為止研削該晶圓而使該切削溝中之該封閉材露出之研削工程， 　　和實施該研削工程之後，自該晶圓的表面側，經由可視光攝影手段而透過該封閉材，查出對準標記，依據該對準標記而查出欲雷射加工之該分割預定線的校準工程， 　　和實施該校準工程之後，對於該封閉材而言，將具有透過性之波長的雷射束的集光點，定位於該切削溝中之該封閉材之內部，自該晶圓的表面側，沿著該分割預定線而照射雷射束，形成改質層於該封閉材之內部的改質層形成工程， 　　和實施該改質層形成工程之後，於該切削溝中之該封閉材，賦予外力而將該改質層作為分割起點，經由該封閉材而分割成圍繞有表面及4側面之各個的裝置晶片之分割工程； 　　該校準工程係於經由該可視光攝影手段而攝影之範圍，經由斜光手段而自傾斜照射光之同時而實施者。A wafer processing method, which is a wafer processing method for forming a device with a plurality of protruding electrodes in each range of the surface demarcated by a plurality of predetermined division lines formed by crossing, which is characterized by: On the surface side of the wafer, a cutting groove forming process of forming a cutting groove having a depth equivalent to the complete thickness of the device wafer through a cutting blade along the planned division line, and sealing with a sealing material after performing the cutting groove forming process sealing process of the surface of the wafer including the cutting trench, and after performing the sealing process, grinding the wafer from the back side of the wafer to the finished thickness of the device wafer so that the sealing material in the cutting trench The exposed grinding process, and after the grinding process is carried out, from the surface side of the wafer, the alignment mark is detected through the sealing material by means of visible light photography, and the position to be processed by laser is detected according to the alignment mark. The calibration process of the predetermined dividing line, and after the calibration process is carried out, for the sealing material, the light-collecting point of the laser beam having a transparent wavelength is positioned inside the sealing material in the cutting groove, A modified layer forming process of irradiating a laser beam along the planned dividing line from the surface side of the wafer to form a modified layer inside the sealing member, and after performing the modified layer forming process, in the cutting The sealing material in the groove is given an external force and the modified layer is used as the starting point of division, and the sealing material is divided into the division process of each device chip surrounding the surface and 4 sides; the alignment process is based on the visible light Photography means and the scope of photography is implemented by oblique light means and simultaneously irradiating light from obliquely.
TW107131468A 2017-09-08 2018-09-07 Wafer processing method TWI789422B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-172839 2017-09-08
JP2017172839A JP6918418B2 (en) 2017-09-08 2017-09-08 Wafer processing method

Publications (2)

Publication Number Publication Date
TW201913783A TW201913783A (en) 2019-04-01
TWI789422B true TWI789422B (en) 2023-01-11

Family

ID=65441994

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107131468A TWI789422B (en) 2017-09-08 2018-09-07 Wafer processing method

Country Status (6)

Country Link
JP (1) JP6918418B2 (en)
KR (1) KR102581138B1 (en)
CN (1) CN109473351A (en)
DE (1) DE102018215247A1 (en)
SG (1) SG10201807747VA (en)
TW (1) TWI789422B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7368098B2 (en) * 2019-04-17 2023-10-24 株式会社ディスコ Wafer processing method
CN110744731B (en) * 2019-10-30 2021-07-27 许昌学院 Wafer slicing equipment based on photoelectric control
US11908831B2 (en) 2020-10-21 2024-02-20 Stmicroelectronics Pte Ltd Method for manufacturing a wafer level chip scale package (WLCSP)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017041472A (en) * 2015-08-17 2017-02-23 株式会社ディスコ Processing method for stuck substrate
JP2017117990A (en) * 2015-12-25 2017-06-29 株式会社ディスコ Processing method of wafer

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0756877B2 (en) * 1990-01-24 1995-06-14 三菱電機株式会社 Lead flatness measuring device for semiconductor device
US6649445B1 (en) * 2002-09-11 2003-11-18 Motorola, Inc. Wafer coating and singulation method
JP2004200258A (en) 2002-12-17 2004-07-15 Shinko Electric Ind Co Ltd Device and method for inspecting bump
JP2007190596A (en) * 2006-01-20 2007-08-02 Seiko Epson Corp Method for manufacturing base body, flexible circuit substrate, electrooptical device and electronic equipment
JP2009158763A (en) * 2007-12-27 2009-07-16 Disco Abrasive Syst Ltd Protective film coating apparatus
JP2010024064A (en) * 2008-07-15 2010-02-04 Seiko Epson Corp Method for manufacturing structure and droplet ejection head
JP5474630B2 (en) * 2010-03-30 2014-04-16 トッパン・フォームズ株式会社 Electronic component and manufacturing method thereof, component mounting board
JP5895332B2 (en) 2010-04-01 2016-03-30 株式会社ニコン Position detection apparatus, overlay apparatus, position detection method, and device manufacturing method
JP5948034B2 (en) 2011-09-27 2016-07-06 株式会社ディスコ Alignment method
KR20130059291A (en) * 2011-11-28 2013-06-05 닛토덴코 가부시키가이샤 Underfill material and method for manufacturing semiconductor device
JP2014003274A (en) * 2012-05-25 2014-01-09 Nitto Denko Corp Method for manufacturing semiconductor device and underfill material
JP6157890B2 (en) * 2013-03-26 2017-07-05 日東電工株式会社 Underfill material, sealing sheet, and method for manufacturing semiconductor device
DE112014001676B4 (en) * 2013-03-27 2024-06-06 Hamamatsu Photonics K.K. Laser processing device and laser processing method
JP2016015438A (en) 2014-07-03 2016-01-28 株式会社ディスコ Alignment method
JP2016166120A (en) * 2015-03-06 2016-09-15 三星ダイヤモンド工業株式会社 Processing method of laminated substrate, and processing device of laminated substrate by laser beam
JP2017022162A (en) * 2015-07-07 2017-01-26 株式会社ディスコ Wafer processing method
JP6557081B2 (en) * 2015-07-13 2019-08-07 株式会社ディスコ Wafer processing method
JP2017028160A (en) * 2015-07-24 2017-02-02 株式会社ディスコ Machining method for wafer
CN107924877B (en) * 2015-08-11 2020-08-28 株式会社村田制作所 High-frequency module and method for manufacturing same
JP2017054888A (en) * 2015-09-08 2017-03-16 株式会社ディスコ Processing method for wafer
JP2017107984A (en) * 2015-12-09 2017-06-15 株式会社ディスコ Wafer processing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017041472A (en) * 2015-08-17 2017-02-23 株式会社ディスコ Processing method for stuck substrate
JP2017117990A (en) * 2015-12-25 2017-06-29 株式会社ディスコ Processing method of wafer

Also Published As

Publication number Publication date
SG10201807747VA (en) 2019-04-29
DE102018215247A1 (en) 2019-03-14
KR102581138B1 (en) 2023-09-20
KR20190028317A (en) 2019-03-18
JP6918418B2 (en) 2021-08-11
CN109473351A (en) 2019-03-15
TW201913783A (en) 2019-04-01
JP2019050252A (en) 2019-03-28

Similar Documents

Publication Publication Date Title
TWI715663B (en) Wafer processing method
TWI789422B (en) Wafer processing method
TW201913784A (en) Wafer processing method
TWI797156B (en) Wafer processing method
TWI766094B (en) Wafer processing method
TWI766091B (en) Wafer processing method
TWI788410B (en) Wafer processing method
TWI766092B (en) Wafer processing method
TWI766090B (en) Wafer processing method
TWI773822B (en) Wafer processing method
TWI769311B (en) Wafer Processing Method
TWI761588B (en) Wafer processing method
TWI786176B (en) Wafer processing method