JP2019033178A - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
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- JP2019033178A JP2019033178A JP2017153327A JP2017153327A JP2019033178A JP 2019033178 A JP2019033178 A JP 2019033178A JP 2017153327 A JP2017153327 A JP 2017153327A JP 2017153327 A JP2017153327 A JP 2017153327A JP 2019033178 A JP2019033178 A JP 2019033178A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 113
- 239000002184 metal Substances 0.000 claims abstract description 289
- 229910052751 metal Inorganic materials 0.000 claims abstract description 289
- 239000010410 layer Substances 0.000 claims abstract description 284
- 239000012792 core layer Substances 0.000 claims abstract description 49
- 229920005989 resin Polymers 0.000 claims abstract description 20
- 239000011347 resin Substances 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 12
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000007769 metal material Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 description 15
- 238000005530 etching Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 13
- 238000012545 processing Methods 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 238000007788 roughening Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 239000003365 glass fiber Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011247 coating layer Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
Description
図1、図2、図3、図4A〜図4Kおよび図6を参照しつつ、第1実施形態における半導体モジュール100について説明する。図1は、第1実施形態に係る半導体モジュール100の一例を概略的に示す断面図である。図2は、第1実施形態に係る半導体モジュール100における島状の導電パターン140の一例を概略的に示す平面図である。図3は、第1実施形態に係る半導体モジュール100の他の形態の一例を概略的に示す断面図である。図4A〜図4Kは、第1実施形態に係る半導体モジュール100の製造工程を示す断面図である。図6は、一般的な半導体モジュール1000の一例を概略的に示す断面図である。
このような半導体モジュール100は、図1に示すように、少なくとも、金属コア層110と、内部電子部品120と、絶縁層130と、導電パターン140と、ソルダーレジスト層150と、を含んで構成されている。なお、ここでいう導電パターン140とは、電極、電極と一体でなる配線、viaとコンタクトした電極、外部電極などである。
言い換えると、第1金属層111は、第2金属層112および第3金属層113と比較して硬い金属材料で形成されている。より具体的には、第1金属層111は合金圧延銅で形成され、第2金属層112および第3金属層113は圧延銅または電界銅で形成されることが好ましい。
図4A〜図4Kを参照しつつ、半導体モジュール100の製作工程を以下のとおり説明する。なお、以下説明においては、第1実施形態に係る半導体モジュール100の製造を想定することとし、重複する説明および図中の符号については適宜省略する。
図5を参照しつつ、第2実施形態に係る半導体モジュール200について以下のとおり説明する。図5は、第2実施形態に係る半導体モジュール200を概略的に示す断面図である。なお、以下において説明すること以外については、既に説明した実施形態と同じこととし、その説明および図面の符号を省略する。
以上説明したように、半導体モジュール100は、第1表面と、第1表面と反対側の第1裏面と、を有する第1金属層111と、第2表面と、第2表面と反対側の第2裏面と、を有し、第1表面が第2裏面側を向くように第1金属層111に積層される第2金属層112と、を備える金属コア層110と、第2金属層112が取り除かれて、第1金属層111が露出して形成される底面と、第2金属層112に底面と連続して形成される側面と、の少なくとも一方が、第1表面よりも滑らかになるように形成されるキャビティ114と、樹脂成分を含む固着材を介してキャビティ114の底面に設けられる半導体素子120と、第2表面および半導体素子120を覆う絶縁層130に設けられ、半導体素子120と電気的に接続される第1導電パターン140と、第1裏面を被覆する絶縁層130に設けられ、半導体素子120と電気的に接続される第2導電パターン140と、を備える。かかる実施形態によれば、半導体モジュール100における絶縁樹脂の所謂ブリードアウト現象を防止することができる。
110,210 金属コア層
111,211 第1金属層
112,212 第2金属層
114 キャビティ
120 内部電子部品
130 絶縁層
140 導電パターン
141A 第3導電パターン
Claims (15)
- 第1表面と、前記第1表面と反対側の第1裏面と、を有する第1金属層と、第2表面と、前記第2表面と反対側の第2裏面と、を有し、前記第1表面が前記第2裏面側を向くように前記第1金属層に積層される第2金属層と、を備える金属コア層と、
前記第2金属層が取り除かれて、前記第1金属層が露出して形成される底面と、前記第2金属層に前記底面と連続して形成される側面と、の少なくとも一方が、前記第1表面よりも滑らかになるように形成されるキャビティと、
樹脂成分を含む固着材を介して前記キャビティの底面に設けられる半導体素子と、
前記第2表面および前記半導体素子を覆う絶縁層に設けられ、前記半導体素子と電気的に接続される第1導電パターンと、
前記第1裏面を被覆する絶縁層に設けられ、前記半導体素子と電気的に接続される第2導電パターンと、
を備えることを特徴とする半導体モジュール。 - 前記金属コア層は、前記第1金属層よりも前記第2金属層の方が薄く形成される
ことを特徴とする請求項1に記載の半導体モジュール。 - 前記第1金属層は、前記第2金属層よりも硬い金属材料から成る
ことを特徴とする請求項1又は請求項2に記載の半導体モジュール。 - 前記第2金属層は、前記半導体素子または前記第1導電パターンの少なくともいずれか一方と電気的に接続されるような第3導電パターンを有する
ことを特徴とする請求項1乃至請求項3の何れか一項に記載の半導体モジュール。 - 前記第2金属層は、第1金属部と、前記第1金属部と分離された第2金属部と、を含んで形成され、
前記第3導電パターンは、前記第1金属部または前記第2金属部の何れか一方である
ことを特徴とする請求項4に記載の半導体モジュール。 - 前記キャビティの底面となる前記第1金属層の前記第1表面は、前記半導体素子の熱が伝達されるように、前記半導体素子と接続される
ことを特徴とする請求項5に記載の半導体モジュール。 - 前記第1金属層における金属の残存率が前記第2金属層における金属の残存率よりも高い
ことを特徴とする請求項1に記載の半導体モジュール。 - 最下層の金属層となる第1金属層の第1表面および第1裏面は、平坦に形成されている
ことを特徴とする請求項1に記載の半導体モジュール。 - 第1表面と、前記第1表面と反対側の第1裏面と、を有する第1金属層と、第2表面と、前記第2表面と反対側の第2裏面と、を有し、前記第1表面が前記第2裏面側を向くように前記第1金属層に積層される第2金属層と、第3表面と、前記第3表面と反対側の第3裏面と、を有し、前記第2表面が前記第3裏面側を向くように前記第2金属層に積層される第3金属層と、を備える金属コア層と、
前記第2金属層および前記第3金属層が取り除かれて、前記第1金属層が露出して形成される底面と、前記第2金属層および前記第3金属層に前記底面と連続して形成される側面と、の少なくとも一方が、前記第1表面よりも滑らかになるように形成されるキャビティと、
樹脂成分を含む固着材を介して前記キャビティの底面に設けられる半導体素子と、
前記第3表面および前記半導体素子を覆う絶縁層に設けられ、前記半導体素子と電気的に接続される第1導電パターンと、
前記第1裏面を被覆する絶縁層に設けられ、前記半導体素子と電気的に接続される第2導電パターンと、
を備えることを特徴とする半導体モジュール。 - 前記金属コア層は、前記第1金属層よりも前記第2金属層の方が薄く、前記第2金属層よりも前記第3金属層の方が薄く形成される
ことを特徴とする請求項9に記載の半導体モジュール。 - 前記第1金属層における金属の残存率が前記第2金属層および前記第3金属層における金属の残存率よりも高い
ことを特徴とする請求項9又は請求項10に記載の半導体モジュール。 - 最下層に設けられた最も厚い下層金属層と、最上層に積層されて設けられ、最も薄い上層金属層を有するコア層と、
前記コア層の上面およびコア層の下面に積層された絶縁層および導電パターンと、
前記コア層の上面の導電パターンと電気的に接続される前記上層金属層による配線と、前記上層金属層を取り除くことで成るキャビティと
を有し、
前記下層金属層の金属の残存率は、上層金属層の金属の残存率より高い
ことを特徴とする回路基板。 - 請求項12に記載の回路基板と、
前記回路基板の前記下層金属層を底面とした前記キャビティに実装される半導体素子と、
前記コア層の下面に設けられる導電パターンと電気的に接続され、前記半導体素子と電気的に接続される前記下層金属層による電極とを有する
ことを特徴とする半導体モジュール。 - 前記上層金属層および前記下層金属層は、Cu、AlまたはFeを主材料とする
ことを特徴とする請求項13に記載の半導体モジュール。 - 最下層に設けられた最も厚い第1金属層と、最上層に積層されて設けられ、最も薄い第2の厚みの第2金属層を有するコア層と、
前記コア層の上面およびコア層の下面に積層された絶縁層および導電パターンと、
前記コア層の上面の導電パターンと電気的に接続される前記第2金属層による配線とを有し、
前記第1金属層の金属の残存率は、他の金属層の残存率より高い
ことを特徴とする回路基板。
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US16/057,655 US10607940B2 (en) | 2017-08-08 | 2018-08-07 | Semiconductor module |
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WO2021192245A1 (ja) * | 2020-03-27 | 2021-09-30 | 太陽誘電株式会社 | 高放熱モジュール構造 |
WO2022185692A1 (ja) * | 2021-03-02 | 2022-09-09 | 株式会社村田製作所 | 高周波モジュール及び通信装置 |
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US10804188B2 (en) | 2018-09-07 | 2020-10-13 | Intel Corporation | Electronic device including a lateral trace |
TWI690947B (zh) * | 2018-11-30 | 2020-04-11 | 台灣愛司帝科技股份有限公司 | 導電物質的布局方法、布局結構及包含其之led顯示器 |
CN112349700B (zh) * | 2020-09-28 | 2023-05-09 | 中国电子科技集团公司第二十九研究所 | 一种气密高导热lcp封装基板及多芯片系统级封装结构 |
CN115884495A (zh) * | 2021-09-29 | 2023-03-31 | 奥特斯科技(重庆)有限公司 | 部件承载件及其制造方法 |
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JP2003332752A (ja) * | 2002-05-14 | 2003-11-21 | Shinko Electric Ind Co Ltd | メタルコア基板およびその製造方法 |
TWI220782B (en) | 2002-10-14 | 2004-09-01 | Siliconware Precision Industries Co Ltd | Cavity-down ball grid array package with heat spreader |
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JP4361826B2 (ja) * | 2004-04-20 | 2009-11-11 | 新光電気工業株式会社 | 半導体装置 |
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KR102277800B1 (ko) * | 2019-12-11 | 2021-07-16 | 현대모비스 주식회사 | 방열판 일체형 파워 모듈 및 이의 제조방법 |
WO2021192245A1 (ja) * | 2020-03-27 | 2021-09-30 | 太陽誘電株式会社 | 高放熱モジュール構造 |
WO2022185692A1 (ja) * | 2021-03-02 | 2022-09-09 | 株式会社村田製作所 | 高周波モジュール及び通信装置 |
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