JP2018526832A - 基板を被膜する方法 - Google Patents
基板を被膜する方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 104
- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000000576 coating method Methods 0.000 title claims abstract description 13
- 239000011248 coating agent Substances 0.000 title claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 131
- 239000004065 semiconductor Substances 0.000 claims abstract description 102
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 238000010030 laminating Methods 0.000 claims abstract description 14
- 238000001020 plasma etching Methods 0.000 claims description 21
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 6
- 238000009616 inductively coupled plasma Methods 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 229910002704 AlGaN Inorganic materials 0.000 claims description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000009966 trimming Methods 0.000 claims description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 2
- 229910052582 BN Inorganic materials 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- 238000012545 processing Methods 0.000 description 10
- 238000005259 measurement Methods 0.000 description 9
- 238000011109 contamination Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000013459 approach Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910017115 AlSb Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000012864 cross contamination Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- -1 InN Chemical compound 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
- 238000004876 x-ray fluorescence Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
Abstract
【選択図】図2−1
Description
Claims (22)
- 少なくともCMOSデバイス層、シリコンとは異なる第一の半導体材料層と、第二の半導体材料層とを含み、前記第一の半導体材料層が前記CMOSデバイス層と前記第二の半導体材料層との間に配置される基板を被膜する方法であって、
(i)前記基板のエッジの一部を円周方向に沿って取り除くことと、
(ii)ステップ(i)で取り除かれた部分に置き換えて前記基板に誘電体を積層し、少なくとも前記CMOSデバイス層および前記第一の半導体材料層を被膜することと
を含む、方法。 - 前記第一の半導体材料がIII−V族半導体材料または互いに異なる複数のIII−V族半導体材料を組み合わせて形成される材料を含む、請求項1に記載の方法。
- 前記III−V族半導体材料がGaN、InGaP、AlGaAs、InGaAsP、InGaN、AlGaN、GaAs、GeまたはInGaAsを含む、請求項2に記載の方法。
- 前記第二の半導体材料がシリコンまたはCMOS互換性材料を含む、請求項1乃至3のうちのいずれか一項に記載の方法。
- 前記CMOSデバイス層がシリコンオンインシュレータをベースにしたデバイスを含む、請求項1乃至4のうちのいずれか一項に記載の方法。
- 前記基板の一部を円周方向に沿って取り除くことが、反応性イオンエッチングまたは誘導結合型プラズマ反応性イオンエッチングを用いて取り除くことを含む、請求項1乃至5のうちのいずれか一項に記載の方法。
- 反応性イオンエッチングまたは誘導結合型プラズマ反応性イオンエッチングが用いられる場合、ステップ(i)に先立って、カプトンテープを用いて前記CMOSデバイス層にウエハーマスクを着脱可能に取り付けることをさらに含む、請求項6に記載の方法。
- 前記ウエハーマスクがシリコンから形成される、請求項7に記載の方法。
- 前記基板の一部を円周方向に沿って取り除くことが、エッジトリミングを用いて取り除くことを含む、請求項1乃至5のうちのいずれか一項に記載の方法。
- 前記基板に誘電体を積層することが、前記CMOSデバイス層において、前記第一の半導体材料の層とは反対側に位置し、前記基板の水平軸と実質的に平行な面に前記誘電体の層を積層することを含み、さらに、前記方法は、(iii)前記CMOSデバイス層の前記面に積層された前記誘電体の層を少なくとも部分的に取り除いて前記基板を平面化することを含む、請求項1乃至9のうちのいずれか一項に記載の方法。
- 前記基板を平面化することが、化学機械研磨を用いて前記平面化を行うことを含む、請求項10に記載の方法。
- 前記誘電体が、酸化アルミニウム、窒化アルミニウム、二酸化ケイ素、窒化ケイ素、合成ダイヤモンドおよび窒化ホウ素から成る群から選択される、請求項1乃至11のうちのいずれか一項に記載の方法。
- 前記基板に誘電体を積層することが、プラズマ化学気相成長を用いて前記積層を行うことを含む、請求項1乃至12のうちのいずれか一項に記載の方法。
- ステップ(iii)の後に、
(iv)前記第二の半導体材料層において、前記第一の半導体材料層とは反対側に位置する面に誘電体を積層することをさらに含む、請求項10に記載の方法。 - ステップ(iii)またはステップ(iv)の後に、(v)積層された前記誘電体の密度を高めるために前記基板をアニール処理することをさらに含む、請求項10または14に記載の方法。
- 前記基板の一部を円周方向に沿って取り除くことが、前記第二の半導体材料層のエッジの一部を部分的に取り除くことを含む、請求項1乃至15のうちのいずれか一項に記載の方法。
- ステップ(ii)の実行中、前記CMOSデバイス層の前記ウエハーマスクが取り付けられたままであることをさらに含む、請求項7に記載の方法。
- ステップ(i)の後かつステップ(ii)の前に前記ウエハーマスクを取り除きくこと、および
ステップ(ii)において前記基板上の前記誘電体としてスピンオングラス材料を積層することをさらに含む、請求項17に記載の方法。 - 少なくともCMOSデバイス層と、
シリコンとは異なる第一の半導体材料層と、
第二の半導体材料層とを備え、
前記第一の半導体材料層が前記CMOSデバイス層と前記第二の半導体材料層との間に配置され、
少なくとも前記CMOSデバイス層および前記第一の半導体材料層が誘電体により円周方向に沿って被膜されるように構成されてなる、基板。 - 前記第一の半導体材料がIII−V族半導体材料または互いに異なる複数のIII−V族半導体材料を組み合わせて形成される材料を含む、請求項19に記載の基板。
- 前記第二の半導体材料がシリコンまたはCMOS互換性材料を含む、請求項19または20に記載の基板。
- 前記CMOSデバイス層がシリコンオンインシュレーターをベースにするデバイスを含む、請求項19乃至21のうちのいずれか一項に記載の基板。
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US201562283648P | 2015-09-04 | 2015-09-04 | |
US62/283,648 | 2015-09-04 | ||
PCT/SG2016/050423 WO2017039542A1 (en) | 2015-09-04 | 2016-08-31 | Method of encapsulating a substrate |
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JP2018526832A true JP2018526832A (ja) | 2018-09-13 |
JP6887992B2 JP6887992B2 (ja) | 2021-06-16 |
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US (1) | US10510560B2 (ja) |
EP (1) | EP3345209A4 (ja) |
JP (1) | JP6887992B2 (ja) |
KR (1) | KR102632041B1 (ja) |
CN (1) | CN107924810B (ja) |
TW (1) | TWI719047B (ja) |
WO (1) | WO2017039542A1 (ja) |
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TW201719716A (zh) | 2017-06-01 |
TWI719047B (zh) | 2021-02-21 |
KR102632041B1 (ko) | 2024-02-01 |
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US20180254197A1 (en) | 2018-09-06 |
JP6887992B2 (ja) | 2021-06-16 |
KR20180048706A (ko) | 2018-05-10 |
EP3345209A4 (en) | 2018-11-14 |
CN107924810B (zh) | 2022-09-30 |
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CN107924810A (zh) | 2018-04-17 |
US10510560B2 (en) | 2019-12-17 |
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