US8592297B2 - Wafer and method of processing wafer - Google Patents

Wafer and method of processing wafer Download PDF

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Publication number
US8592297B2
US8592297B2 US13/328,346 US201113328346A US8592297B2 US 8592297 B2 US8592297 B2 US 8592297B2 US 201113328346 A US201113328346 A US 201113328346A US 8592297 B2 US8592297 B2 US 8592297B2
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Prior art keywords
layer
substrate
conductive layer
distance
periphery
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US20130154060A1 (en
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Tung-Ti Yeh
Wu-Chang Lin
Chung-Yi HUANG
Ya Wen WU
Hui-Mei JAO
Ting-Chun Wang
Chia-Hung Chung
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, CHUNG-YI, WANG, TING-CHUN, CHUNG, CHIA-HUNG, JAO, HUI-MEI, LIN, WU-CHANG, WU, YA WEN, YEH, TUNG-TI
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02082—Cleaning product to be cleaned
    • H01L21/02087—Cleaning of wafer edges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Definitions

  • An integrated circuit (IC) chip incorporates millions of active and passive electrical components on a semiconductor substrate within an area usually less than 100 mm 2 . Layers of materials are deposited, implanted, patterned, and/or removed in order to form the active and passive electrical components and interconnection structures of the IC chip. Usually, tens or even hundreds of similar or identical IC chips are arranged to be manufactured on a single wafer for efficient mass production. The larger the wafer size, the more IC chips can be manufactured on a single wafer, and thus the fabrication cost for each IC chip is lower.
  • an edge portion of the wafer tends to be more vulnerable to various kinds of process variations, such as poor step-coverage when forming a film thereon, trapped voids when filling openings, or damages caused by material exposure, plasma-arcing, or other uniformity issues of the processes. These issues not only result in defective chips at the edge portion of the wafer.
  • the defects, such as cracks or delaminated layers, at the edge portion of the wafer may further propagate inward toward the center of the wafer and thus lead to more defective chips at an inner portion of the wafer.
  • FIG. 1 is a schematic top view of a semiconductor wafer in accordance with one or more embodiments
  • FIG. 2 is cross-sectional view of the semiconductor wafer taken at line A, as depicted in FIG. 1 , in accordance with one or more embodiments;
  • FIG. 3 is a flow chart of a method of manufacturing a semiconductor structure in accordance with one or more embodiments
  • FIGS. 4A-4F are cross-sectional views of a semiconductor structure at various manufacture stages in accordance with one or more embodiments.
  • FIG. 5 is a schematic perspective view of an example of the removal of an edge portion of a photoresist layer or a layer of conductive material formed over a substrate in accordance with one or more embodiments.
  • a feature on, connected to, and/or coupled to another feature in the present disclosure may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact.
  • spatially relative terms for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature.
  • the spatially relative terms are intended to cover different orientations of the device including the features.
  • FIG. 1 is a schematic top view of a semiconductor wafer 100 in accordance with one or more embodiments.
  • the wafer 100 has a circular shape having a diameter D.
  • the wafer 100 has at least one notch portion 110 indicative of a lattice orientation of the semiconductor substrate 120 ( FIG. 2 ) of the wafer 100 .
  • the wafer 100 is arranged to have a plurality of IC chips (not shown) formed thereon.
  • the diameter D of the wafer is about 12 inches (304.8 mm). In some embodiments, the diameter D of the wafer is greater or less than 304.8 mm, such as 6 inches, 8 inches, or 18 inches.
  • the substrate 120 has a main portion 122 ( FIG. 2 ) and a bevel portion 124 ( FIG. 2 ).
  • the main portion 122 is the flat portion of the substrate 120 and has a substantially constant thickness
  • the bevel portion 124 has a tapered shape extending from a periphery 126 of the substrate 120 inward toward a center of the substrate 120 and ending at the main portion 122 .
  • the bevel portion 124 is at the edge of the substrate 120 and surrounds the main portion 122 , and the interface between the main portion 122 and the bevel portion 124 defines a periphery 128 of the main portion 122 .
  • the wafer 100 also includes a dielectric layer 140 ( FIG. 2 ) over the semiconductor substrate 120 and a conductive layer 150 ( FIG. 2 ) over the dielectric layer 140 .
  • the dielectric layer 140 has a circular shape, and a periphery 142 of the dielectric layer 140 defines a dielectric layer area S 1 .
  • the conductive layer 150 has a circular shape, and a periphery 152 of the conductive layer 150 defines a conductive layer area S 2 .
  • FIG. 2 is a cross-sectional view of the wafer 100 taken at line A, as depicted in FIG. 1 , in accordance with one or more embodiments.
  • the wafer 100 includes the semiconductor substrate 120 , an intermediate structure 130 , the dielectric layer 140 over the semiconductor substrate 120 and the intermediate structure 130 , and the conductive layer 150 over the dielectric layer 140 .
  • the substrate 120 has a diameter, which is the same as the diameter D ( FIG. 1 ) of the wafer 100 .
  • the substrate 120 has the main portion 122 and the bevel portion 124 , and the bevel portion 124 extends from the periphery 126 of the substrate 120 inwardly for about a distance L B .
  • the distance L B is set to be large enough to allow various processing machines to hold the wafer 100 securely, but small enough to maximize an area of the main portion 122 on which a plurality of IC chips will be formed. In some embodiments, the distance L B is about 1 mm.
  • the substrate 120 includes: an elementary semiconductor such as silicon or germanium in crystal, polycrystalline, or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlinAs, AlGaAs, GaInAs, GalnP, and/or GaInAsP; or combinations thereof.
  • the substrate 120 is an alloy semiconductor substrate having a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location of the gradient SiGe feature.
  • the alloy SiGe is formed over a silicon substrate.
  • a SiGe substrate is strained.
  • the semiconductor substrate is a semiconductor on insulator.
  • the semiconductor substrate includes a doped epitaxial layer or a buried layer.
  • the compound semiconductor substrate has a multilayer structure or the substrate includes a multilayer compound semiconductor structure.
  • the intermediate structure 130 includes a plurality of active or passive electrical components, such as a transistor, e.g., a metal-oxide semiconductor field effect transistor (MOSFET), a resistor, a capacitor, and/or an inductor formed over and, in some embodiments, partially embedded within the substrate 120 .
  • a transistor e.g., a metal-oxide semiconductor field effect transistor (MOSFET)
  • MOSFET metal-oxide semiconductor field effect transistor
  • the intermediate structure 130 also includes one or more conductive layers and one or more interlayer dielectric layers formed over the substrate 120 and the electrical components.
  • the dielectric layer 140 over the substrate 120 and the intermediate structure 130 , has a plurality of openings defined therein.
  • the openings include trenches and/or vias that are used for forming conductive lines and conductive via plugs, respectively.
  • the periphery 142 of the dielectric layer 140 and the periphery 128 of the main portion 122 of the substrate 120 are separated by a distance L 1 .
  • the periphery 142 of the dielectric layer 140 is defined by the outer-most edge of the dielectric layer 140 .
  • the periphery 152 of the conductive layer 150 and the periphery 128 of the main portion 122 of the substrate 120 are separated by a distance L 2 .
  • the periphery 152 of the conductive layer 150 is defined by the outer-most edge of the conductive layer 150 .
  • the conductive layer 150 overlays the periphery 142 of the dielectric layer 140 and/or extends over the periphery 142 of the dielectric layer 140 as depicted in FIG. 2 by the dotted line (reference 152 ′ is indicative of the embodiment in which the conductive layer 150 extends), and a gap between the periphery 152 ′ of the conductive layer 150 and the periphery 128 of the main portion 122 is still denoted as the distance L 2 .
  • the distances L 1 and L 2 are set to balance a tradeoff between the removal of defective films or patterns caused by non-uniformity or plasma-arcing and a number of IC chips to be formed on the substrate 120 .
  • the distances L 1 and L 2 are set to maximize the number of working IC chips able to be formed on a single wafer 100 .
  • the distance L 1 ranges from about 0.25% of the diameter D to about 0.45% of the diameter D. In some embodiments, the distance L 2 ranges from about a value that is 0.5% of the diameter D less than the distance L 1 to about a value that is 0.5% of the diameter D greater than the distance L 1 (i.e., L 2 is equal to or within L 1 +/ ⁇ 0.005*D).
  • the diameter D is about 12 inches or 304.8 mm
  • the distance L 1 ranges from about 0.7 mm to about 1.3 mm
  • the distance L 2 ranges from about 1.5 mm greater than the distance L 1 (i.e., about 2.2 mm to about 2.8 mm) to about 1.0 mm less than the distance L 1 (i.e., about ⁇ 0.3 mm to about 0.3 mm).
  • the negative value of L 2 means that the conductive layer 150 extends beyond the periphery 128 of the substrate 120 and to an upper surface of the bevel portion 124 .
  • the dielectric layer 140 and the conductive layer 150 are usable to form a portion of the interconnection structure for the IC chip.
  • the interconnection structure includes one upper-most metal layer (i.e., a top metal layer), one or more other metal layers (i.e., inter metal layers), and inter metal dielectric layers for insulating among different conductive paths and mechanically supporting the inter metal layers and the top metal layer.
  • the conductive layer 150 is a top metal layer
  • the distance L 2 ranges from about a value that equals the distance L 1 to about the value that is 0.5% of the diameter D less than the distance L 1 (i.e., L 1 ⁇ L 2 ⁇ L 1 ⁇ 0.005*D).
  • the distance L 2 ranges from about a value that equals the distance L 1 to about the value that is 0.5% of the diameter D greater than the distance L 1 (i.e., L 1 ⁇ L 2 ⁇ L 1 +0.005*D).
  • the relationship between the dielectric layer 140 , the conductive layer 150 , and the distances L 1 and L 2 are determined according to the relative sizes of the dielectric layer 140 and the conductive layer 150 .
  • the dielectric layer 140 defines a dielectric layer area S 1 (the area surrounded by the periphery 142 of the dielectric layer 140 as depicted in FIG. 1 )
  • the conductive layer 150 defines a conductive layer area S 2 (the area surrounded by the periphery 152 of the conductive layer 150 as depicted in FIG. 1 ).
  • the distances L 1 and L 2 are set such that a ratio of the conductive layer area S 2 to the dielectric layer area S 1 ranges from about 99.5% to about 110%.
  • the ratio of the conductive layer area S 2 to the dielectric layer area S 1 ranges from about 100% to about 110%. In at least one embodiment where the conductive layer 150 is a inter metal layer, the ratio of the conductive layer area S 2 to the dielectric layer area S 1 ranges from about 99.5% to about 100%.
  • the dielectric layer 140 comprises silicon dioxide or silicon nitride.
  • the conductive layer 150 comprises copper, aluminum copper, aluminum-copper alloy, silver, gold, silver alloy, gold alloy or combinations thereof.
  • FIG. 3 is a flow chart of a method 300 of manufacturing a semiconductor structure ( 400 in FIGS. 4A-4F ) in accordance with one or more embodiments. It is understood that additional processes may be performed before, during, and/or after the method 300 depicted in FIG. 3 , and that some other processes may only be briefly described herein.
  • a layer of dielectric material ( 440 in FIG. 4A ) is formed over a substrate ( 420 in FIG. 4A ).
  • the substrate 420 has a diameter (D in FIG. 1 ) as similarly depicted in FIG. 1 .
  • the substrate 420 also has a main portion 422 and a bevel portion 424 surrounding the main portion 422 as similarly depicted in FIGS. 1 and 2 , and the bevel portion 424 and the main portion 422 define a periphery 428 of the main portion 422 of the substrate 420 .
  • a photoresist layer ( 442 in FIG. 4A ) is formed over the layer of dielectric material 440 .
  • an edge portion of the photoresist layer 442 is removed to form an edge-processed photoresist layer ( 444 in FIG. 4B ).
  • the removal of the edge portion of the photoresist layer 454 includes spinning the substrate 420 and spraying a solution at the edge portion of the photoresist layer 442 to etch the edge portion of the photoresist layer 442 .
  • the solution comprises H 2 SO 4 or H 2 O 2 .
  • the process moves on to operation 340 , where the layer of dielectric material 440 is patterned using the edge-processed photoresist layer 444 to form a patterned dielectric layer ( 446 in FIG. 4C ). Then, the edge-processed photoresist layer 444 is removed by an ashing process. In some embodiments, operations 320 , 330 , and 340 are repeated until the patterning of the layer of dielectric material 440 is completed.
  • the periphery ( 448 in FIG. 4C ) of the patterned dielectric layer 446 and a periphery 428 of the main portion 422 of the substrate 420 are separated by a first distance L 1 . In some embodiments, the first distance L 1 ranges from about 0.25% of the diameter D to about 0.45% of the diameter D.
  • a layer of conductive material ( 450 in FIG. 4D ) is formed over the patterned dielectric layer 446 .
  • the layer of conductive material 440 comprises a metallic material and is formed by electroplating of the metallic material over the patterned dielectric layer 446 .
  • an edge portion of the metallic layer i.e., the layer of conductive material 450
  • the removal of the edge portion of the layer of conductive material 450 includes spinning the substrate 420 and spraying a solution at the edge portion of the metallic layer 450 to remove the edge portion of the metallic layer 450 .
  • the solution comprises H 2 SO 4 or H 2 O 2 .
  • the periphery ( 454 in FIG. 4D ) of the conductive layer 452 and a periphery 428 of the main portion 422 of the substrate 420 are separated by a second distance L 2 .
  • the conductive layer 452 is so formed that the second distance L 2 ranges from about a value that is 0.5% of the diameter D less than the first distance L 1 to about a value that is 0.5% of the diameter D greater than the first distance L 1 .
  • the second distance L 2 ranges from about a value that equals the first distance L 1 to about the value that is 0.5% of the diameter D less than the first distance L 1 .
  • the second distance L 2 ranges from about a value that equals the first distance L 1 to about the value that is 0.5% of the diameter D greater than the first distance L 1 .
  • operation 360 is indeed omitted.
  • the relationship between the dielectric layer 446 , the conductive layer 452 , and the distances L 1 and L 2 is determined according to their relative sizes.
  • the dielectric layer 446 defines a dielectric layer area (S 1 in FIG. 1 ) and the conductive layer 452 defines a conductive layer area (S 2 in FIG. 1 ).
  • a ratio of the conductive layer area S 2 to the dielectric layer area S 1 ranges from about 99.5% to about 110%.
  • the ratio of the conductive layer area S 2 to the dielectric layer area S 1 ranges from about 100% to about 110%.
  • the ratio of the conductive layer area S 2 to the dielectric layer area S 1 ranges from about 99.5% to about 100%.
  • the conductive layer 452 is formed to overlay the periphery 448 of the patterned dielectric layer 446 ; and in an embodiment where the conductive layer 452 is an inter metal layer, and the conductive layer 452 is formed to expose the periphery 448 of the patterned dielectric layer 446 .
  • the conductive layer 150 is subsequently planarized using a Chemical Mechanical Planarization (CMP) process, and one or more passivation layers and bump structures are formed thereon.
  • CMP Chemical Mechanical Planarization
  • FIGS. 4A-4F are cross-sectional views of a semiconductor structure 400 at various manufacture stages in accordance with one or more embodiments.
  • the semiconductor structure 400 has a substrate 420 , an intermediate structure 430 over the substrate 420 , a layer of dielectric material 440 over the semiconductor substrate 420 and the intermediate structure 430 , and a photoresist layer 442 over the layer of dielectric material 440 .
  • the substrate 420 is usable as the substrate 120 of the wafer 100 depicted in FIG. 1 and has a diameter, which is the same as the diameter D of the wafer 100 as depicted in FIG. 1 .
  • the substrate 420 has a main portion 422 and a bevel portion 424 .
  • the main portion 422 has a substantially constant thickness
  • the bevel portion 424 has a tapered shape extending from a periphery 426 of the substrate 420 inwardly.
  • the intermediate structure 430 corresponds to the intermediate structure 130 of the wafer 100 and includes a plurality of active or passive electrical components.
  • the layer of dielectric material 440 is formed over the intermediate structure 430 and the substrate 420 .
  • the layer of dielectric material 440 comprises silicon dioxide or silicon nitride.
  • the layer of dielectric material 440 is formed by performing a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal oxidation process, a furnace process, other deposition processes, or combinations thereof.
  • the photoresist layer 442 is then formed over the layer of dielectric material 440 by spin-coating or other suitable process. (Operation 320 ).
  • an edge portion of the photoresist layer 442 is removed to form an edge-processed photoresist layer 454 .
  • the edge-processed photoresist layer 444 is then patterned by a lithography process.
  • the layer of dielectric material 440 is patterned to form a patterned dielectric layer 446 .
  • the edge-processed photoresist layer 444 is subsequently removed by an ashing process. (Operation 340 ).
  • another photoresist layer is then formed over the patterned dielectric layer 446 , and operations 320 - 340 are repeated until the patterning of the layer of the dielectric material 440 is completed.
  • a layer of conductive material 450 is formed over the patterned dielectric layer 446 .
  • the layer of conductive material 450 comprises a metallic material such as copper, aluminum, aluminum-copper alloy, silver, gold, silver alloy, gold alloy, or combinations thereof.
  • the layer of conductive material 450 is formed by electroplating of the metallic material.
  • an edge portion of the layer of conductive material 450 is removed to form a conductive layer 452 .
  • operation 360 is omitted.
  • the periphery 448 of the dielectric layer and the periphery 428 of the main portion 422 of the substrate 420 are separated by a first distance L 1 .
  • a periphery 454 of the conductive layer 455 and the periphery 428 of the main portion 422 of the substrate 420 are separated by a second distance L 2 .
  • the first distance L 1 ranges from about 0.25% of the diameter D to about 0.45% of the diameter D.
  • the second distance L 2 ranges from about a value that is 0.5% of the diameter D less than the first distance L 1 to about a value that is 0.5% of the diameter D greater than the first distance L 1 .
  • the relationship between the first distance L 1 and the second distance L 2 is determined according to the relative sizes of the dielectric layer 446 and the conductive layer 452 .
  • the dielectric layer 446 defines a dielectric layer area (S 1 in FIG. 1 )
  • the conductive layer 452 defines a conductive layer area (S 2 in FIG. 1 ).
  • the first distance L 1 and the second distance L 2 are so determined that a ratio of the conductive layer area S 2 to the dielectric layer area S 1 ranges from about 99.5% to about 110%.
  • the conductive layer 452 is a top metal layer
  • the ratio of the conductive layer area S 2 to the dielectric layer area S 1 ranges from about 100% to about 110%.
  • the conductive layer 452 is a inter metal layer
  • the ratio of the conductive layer area S 2 to the dielectric layer area S 1 ranges from about 99.5% to about 100%.
  • the conductive layer 452 is subsequently planarized using a CMP process to form conductive lines and via plugs 456 , and one or more passivation layers and bump structures are formed thereon.
  • FIG. 5 is a schematic perspective view of an example of the removal of an edge portion of a photoresist layer 442 or a layer of conductive material 450 formed over a substrate 420 in accordance with one or more embodiments.
  • the substrate 420 of the wafer 100 is placed on a chuck table and spun by driving a motor of the chuck table.
  • a nozzle 510 is placed over the wafer 100 and sprays a solution 520 onto the wafer 100 at the edge portion 530 of the wafer 100 , and thus to etch the edge portion of the photoresist layer 442 .
  • the solution 520 used to remove the edge portion of the photoresist layer 442 comprises H 2 SO 4 or H 2 O 2 .
  • the substrate 420 of the wafer 100 is placed on the chuck table for spinning by the motor of the chuck table.
  • the nozzle 510 is placed over the wafer 100 and sprays a solution 520 onto the wafer 100 at the edge portion 530 of the wafer 100 , and thus to etch the edge portion of the layer of conductive material 450 .
  • the solution 520 used to remove the edge portion of the layer of conductive material 450 comprises H 2 SO 4 or H 2 O 2 .
  • a wafer includes a substrate, a dielectric layer over the substrate, and a conductive layer over the dielectric layer.
  • the substrate has a main portion having a substantially constant thickness.
  • a periphery of the dielectric layer and a periphery of the main portion being separated by a first distance, and a periphery of the conductive layer and the periphery of the main portion being separated by a second distance.
  • the second distance ranges from about a value that is 0.5% of a diameter of the substrate less than the first distance to about a value that is 0.5% of the diameter of the substrate greater than the first distance.
  • a method of forming a semiconductor structure is disclosed.
  • a layer of dielectric material is formed over a substrate, and the substrate has a main portion.
  • a photoresist layer is formed over the layer of dielectric material.
  • An edge portion of the photoresist layer is removed to form an edge-processed photoresist layer.
  • the layer of dielectric material is patterned based on the edge-processed photoresist layer to form a patterned dielectric layer.
  • a periphery of the patterned dielectric layer and a periphery of the main portion of the substrate are separated by a distance.
  • a conductive layer is formed over the patterned dielectric layer.
  • a periphery of the conductive layer is formed within about 0.5% of a diameter of the substrate to the periphery of the patterned dielectric layer.
  • a method of processing a wafer having a substrate is disclosed.
  • the substrate has a main portion.
  • a dielectric layer is formed over the substrate.
  • the dielectric layer has a periphery and defines a dielectric layer area, and the periphery of the dielectric layer and a periphery of the main portion of the substrate are separated by a distance ranging from about 0.25% to about 0.45% of a diameter of the substrate.
  • a conductive layer is formed over the dielectric layer, and the conductive layer defines a conductive layer area.
  • a ratio of the conductive layer area to the dielectric layer area ranging from about 99.5% to about 110%.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

A wafer including a substrate, a dielectric layer over the substrate, and a conductive layer over the dielectric layer is disclosed. The substrate has a main portion. A periphery of the dielectric layer and the periphery of the main portion of the substrate are separated by a first distance. A periphery of the conductive layer and the periphery of the main portion of the substrate are separated by a second distance. The second distance ranges from about a value that is 0.5% of a diameter of the substrate less than the first distance to about a value that is 0.5% of the diameter greater than the first distance.

Description

BACKGROUND
An integrated circuit (IC) chip incorporates millions of active and passive electrical components on a semiconductor substrate within an area usually less than 100 mm2. Layers of materials are deposited, implanted, patterned, and/or removed in order to form the active and passive electrical components and interconnection structures of the IC chip. Usually, tens or even hundreds of similar or identical IC chips are arranged to be manufactured on a single wafer for efficient mass production. The larger the wafer size, the more IC chips can be manufactured on a single wafer, and thus the fabrication cost for each IC chip is lower.
On the other hand, an edge portion of the wafer tends to be more vulnerable to various kinds of process variations, such as poor step-coverage when forming a film thereon, trapped voids when filling openings, or damages caused by material exposure, plasma-arcing, or other uniformity issues of the processes. These issues not only result in defective chips at the edge portion of the wafer. The defects, such as cracks or delaminated layers, at the edge portion of the wafer may further propagate inward toward the center of the wafer and thus lead to more defective chips at an inner portion of the wafer.
DESCRIPTION OF THE DRAWINGS
One or more embodiments are illustrated by way of examples, and not by limitation, in the figures of the accompanying drawings, wherein elements having the same reference numeral designations represent like elements throughout and wherein:
FIG. 1 is a schematic top view of a semiconductor wafer in accordance with one or more embodiments;
FIG. 2 is cross-sectional view of the semiconductor wafer taken at line A, as depicted in FIG. 1, in accordance with one or more embodiments;
FIG. 3 is a flow chart of a method of manufacturing a semiconductor structure in accordance with one or more embodiments;
FIGS. 4A-4F are cross-sectional views of a semiconductor structure at various manufacture stages in accordance with one or more embodiments; and
FIG. 5 is a schematic perspective view of an example of the removal of an edge portion of a photoresist layer or a layer of conductive material formed over a substrate in accordance with one or more embodiments.
 DETAILED DESCRIPTION
It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, examples and are not intended to be limiting. In accordance with the standard practice in the industry, various features in the drawings are not drawn to scale and are used for illustration purposes only.
The formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features.
FIG. 1 is a schematic top view of a semiconductor wafer 100 in accordance with one or more embodiments. The wafer 100 has a circular shape having a diameter D. The wafer 100 has at least one notch portion 110 indicative of a lattice orientation of the semiconductor substrate 120 (FIG. 2) of the wafer 100. The wafer 100 is arranged to have a plurality of IC chips (not shown) formed thereon. In at least one embodiment, the diameter D of the wafer is about 12 inches (304.8 mm). In some embodiments, the diameter D of the wafer is greater or less than 304.8 mm, such as 6 inches, 8 inches, or 18 inches. The substrate 120 has a main portion 122 (FIG. 2) and a bevel portion 124 (FIG. 2). The main portion 122 is the flat portion of the substrate 120 and has a substantially constant thickness, and the bevel portion 124 has a tapered shape extending from a periphery 126 of the substrate 120 inward toward a center of the substrate 120 and ending at the main portion 122. The bevel portion 124 is at the edge of the substrate 120 and surrounds the main portion 122, and the interface between the main portion 122 and the bevel portion 124 defines a periphery 128 of the main portion 122.
The wafer 100 also includes a dielectric layer 140 (FIG. 2) over the semiconductor substrate 120 and a conductive layer 150 (FIG. 2) over the dielectric layer 140. The dielectric layer 140 has a circular shape, and a periphery 142 of the dielectric layer 140 defines a dielectric layer area S1. The conductive layer 150 has a circular shape, and a periphery 152 of the conductive layer 150 defines a conductive layer area S2.
FIG. 2 is a cross-sectional view of the wafer 100 taken at line A, as depicted in FIG. 1, in accordance with one or more embodiments. The wafer 100 includes the semiconductor substrate 120, an intermediate structure 130, the dielectric layer 140 over the semiconductor substrate 120 and the intermediate structure 130, and the conductive layer 150 over the dielectric layer 140.
The substrate 120 has a diameter, which is the same as the diameter D (FIG. 1) of the wafer 100. The substrate 120 has the main portion 122 and the bevel portion 124, and the bevel portion 124 extends from the periphery 126 of the substrate 120 inwardly for about a distance LB. The distance LB is set to be large enough to allow various processing machines to hold the wafer 100 securely, but small enough to maximize an area of the main portion 122 on which a plurality of IC chips will be formed. In some embodiments, the distance LB is about 1 mm.
In some embodiments, the substrate 120 includes: an elementary semiconductor such as silicon or germanium in crystal, polycrystalline, or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlinAs, AlGaAs, GaInAs, GalnP, and/or GaInAsP; or combinations thereof. In at least one embodiment, the substrate 120 is an alloy semiconductor substrate having a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location of the gradient SiGe feature. In another embodiment, the alloy SiGe is formed over a silicon substrate. In yet another embodiment, a SiGe substrate is strained. In some further embodiments, the semiconductor substrate is a semiconductor on insulator. In some examples, the semiconductor substrate includes a doped epitaxial layer or a buried layer. In other examples, the compound semiconductor substrate has a multilayer structure or the substrate includes a multilayer compound semiconductor structure.
The intermediate structure 130 includes a plurality of active or passive electrical components, such as a transistor, e.g., a metal-oxide semiconductor field effect transistor (MOSFET), a resistor, a capacitor, and/or an inductor formed over and, in some embodiments, partially embedded within the substrate 120. In some embodiments, the intermediate structure 130 also includes one or more conductive layers and one or more interlayer dielectric layers formed over the substrate 120 and the electrical components.
The dielectric layer 140, over the substrate 120 and the intermediate structure 130, has a plurality of openings defined therein. The openings include trenches and/or vias that are used for forming conductive lines and conductive via plugs, respectively. The periphery 142 of the dielectric layer 140 and the periphery 128 of the main portion 122 of the substrate 120 are separated by a distance L1. The periphery 142 of the dielectric layer 140 is defined by the outer-most edge of the dielectric layer 140. The periphery 152 of the conductive layer 150 and the periphery 128 of the main portion 122 of the substrate 120 are separated by a distance L2. The periphery 152 of the conductive layer 150 is defined by the outer-most edge of the conductive layer 150. In at least one embodiment, the conductive layer 150 overlays the periphery 142 of the dielectric layer 140 and/or extends over the periphery 142 of the dielectric layer 140 as depicted in FIG. 2 by the dotted line (reference 152′ is indicative of the embodiment in which the conductive layer 150 extends), and a gap between the periphery 152′ of the conductive layer 150 and the periphery 128 of the main portion 122 is still denoted as the distance L2. The distances L1 and L2 are set to balance a tradeoff between the removal of defective films or patterns caused by non-uniformity or plasma-arcing and a number of IC chips to be formed on the substrate 120. The distances L1 and L2 are set to maximize the number of working IC chips able to be formed on a single wafer 100.
In some embodiments, the distance L1 ranges from about 0.25% of the diameter D to about 0.45% of the diameter D. In some embodiments, the distance L2 ranges from about a value that is 0.5% of the diameter D less than the distance L1 to about a value that is 0.5% of the diameter D greater than the distance L1 (i.e., L2 is equal to or within L1+/−0.005*D). In at least one embodiment, the diameter D is about 12 inches or 304.8 mm, the distance L1 ranges from about 0.7 mm to about 1.3 mm, and the distance L2 ranges from about 1.5 mm greater than the distance L1 (i.e., about 2.2 mm to about 2.8 mm) to about 1.0 mm less than the distance L1 (i.e., about −0.3 mm to about 0.3 mm). The negative value of L2 means that the conductive layer 150 extends beyond the periphery 128 of the substrate 120 and to an upper surface of the bevel portion 124.
In some embodiments, the dielectric layer 140 and the conductive layer 150 are usable to form a portion of the interconnection structure for the IC chip. In at least one embodiment, the interconnection structure includes one upper-most metal layer (i.e., a top metal layer), one or more other metal layers (i.e., inter metal layers), and inter metal dielectric layers for insulating among different conductive paths and mechanically supporting the inter metal layers and the top metal layer. In at least one embodiment where the conductive layer 150 is a top metal layer, the distance L2 ranges from about a value that equals the distance L1 to about the value that is 0.5% of the diameter D less than the distance L1 (i.e., L1≧L2≧L1−0.005*D). In at least one embodiment where the conductive layer 150 is an inter metal layer, the distance L2 ranges from about a value that equals the distance L1 to about the value that is 0.5% of the diameter D greater than the distance L1 (i.e., L1≦L2≦L1+0.005*D).
In some embodiments, the relationship between the dielectric layer 140, the conductive layer 150, and the distances L1 and L2 are determined according to the relative sizes of the dielectric layer 140 and the conductive layer 150. For example, the dielectric layer 140 defines a dielectric layer area S1 (the area surrounded by the periphery 142 of the dielectric layer 140 as depicted in FIG. 1), and the conductive layer 150 defines a conductive layer area S2 (the area surrounded by the periphery 152 of the conductive layer 150 as depicted in FIG. 1). In some embodiments, the distances L1 and L2 are set such that a ratio of the conductive layer area S2 to the dielectric layer area S1 ranges from about 99.5% to about 110%. In at least one embodiment where the conductive layer 150 is a top metal layer, the ratio of the conductive layer area S2 to the dielectric layer area S1 ranges from about 100% to about 110%. In at least one embodiment where the conductive layer 150 is a inter metal layer, the ratio of the conductive layer area S2 to the dielectric layer area S1 ranges from about 99.5% to about 100%.
In some embodiments, the dielectric layer 140 comprises silicon dioxide or silicon nitride. In some embodiments, the conductive layer 150 comprises copper, aluminum copper, aluminum-copper alloy, silver, gold, silver alloy, gold alloy or combinations thereof.
FIG. 3 is a flow chart of a method 300 of manufacturing a semiconductor structure (400 in FIGS. 4A-4F) in accordance with one or more embodiments. It is understood that additional processes may be performed before, during, and/or after the method 300 depicted in FIG. 3, and that some other processes may only be briefly described herein.
In operation 310, a layer of dielectric material (440 in FIG. 4A) is formed over a substrate (420 in FIG. 4A). The substrate 420 has a diameter (D in FIG. 1) as similarly depicted in FIG. 1. The substrate 420 also has a main portion 422 and a bevel portion 424 surrounding the main portion 422 as similarly depicted in FIGS. 1 and 2, and the bevel portion 424 and the main portion 422 define a periphery 428 of the main portion 422 of the substrate 420. In operation 320, a photoresist layer (442 in FIG. 4A) is formed over the layer of dielectric material 440. Then, in operation 330, an edge portion of the photoresist layer 442 is removed to form an edge-processed photoresist layer (444 in FIG. 4B). In some embodiments, the removal of the edge portion of the photoresist layer 454 includes spinning the substrate 420 and spraying a solution at the edge portion of the photoresist layer 442 to etch the edge portion of the photoresist layer 442. In some embodiments, the solution comprises H2SO4 or H2O2.
The process moves on to operation 340, where the layer of dielectric material 440 is patterned using the edge-processed photoresist layer 444 to form a patterned dielectric layer (446 in FIG. 4C). Then, the edge-processed photoresist layer 444 is removed by an ashing process. In some embodiments, operations 320, 330, and 340 are repeated until the patterning of the layer of dielectric material 440 is completed. The periphery (448 in FIG. 4C) of the patterned dielectric layer 446 and a periphery 428 of the main portion 422 of the substrate 420 are separated by a first distance L1. In some embodiments, the first distance L1 ranges from about 0.25% of the diameter D to about 0.45% of the diameter D.
The process moves on to operation 350, where a layer of conductive material (450 in FIG. 4D) is formed over the patterned dielectric layer 446. In at least one embodiment, the layer of conductive material 440 comprises a metallic material and is formed by electroplating of the metallic material over the patterned dielectric layer 446. Then, in operation 360, an edge portion of the metallic layer (i.e., the layer of conductive material 450) is removed to form the conductive layer 452. In some embodiments, the removal of the edge portion of the layer of conductive material 450 includes spinning the substrate 420 and spraying a solution at the edge portion of the metallic layer 450 to remove the edge portion of the metallic layer 450. In some embodiments, the solution comprises H2SO4 or H2O2. The periphery (454 in FIG. 4D) of the conductive layer 452 and a periphery 428 of the main portion 422 of the substrate 420 are separated by a second distance L2.
In at least one embodiment, the conductive layer 452 is so formed that the second distance L2 ranges from about a value that is 0.5% of the diameter D less than the first distance L1 to about a value that is 0.5% of the diameter D greater than the first distance L1. In at least one embodiment where the conductive layer 452 is a top metal layer, the second distance L2 ranges from about a value that equals the first distance L1 to about the value that is 0.5% of the diameter D less than the first distance L1. In at least another embodiment where the conductive layer 452 is an inter metal layer, the second distance L2 ranges from about a value that equals the first distance L1 to about the value that is 0.5% of the diameter D greater than the first distance L1. In at least one embodiment where the conductive layer 452 is a top metal layer, operation 360 is indeed omitted.
In some embodiments, the relationship between the dielectric layer 446, the conductive layer 452, and the distances L1 and L2 is determined according to their relative sizes. For example, the dielectric layer 446 defines a dielectric layer area (S1 in FIG. 1) and the conductive layer 452 defines a conductive layer area (S2 in FIG. 1). In some embodiments, a ratio of the conductive layer area S2 to the dielectric layer area S1 ranges from about 99.5% to about 110%. In at least one embodiment where the conductive layer 452 is a top metal layer, the ratio of the conductive layer area S2 to the dielectric layer area S1 ranges from about 100% to about 110%. In at least one embodiment where the conductive layer 452 is a inter metal layer, the ratio of the conductive layer area S2 to the dielectric layer area S1 ranges from about 99.5% to about 100%. In other words, in an embodiment where the conductive layer 452 is a top metal layer, the conductive layer 452 is formed to overlay the periphery 448 of the patterned dielectric layer 446; and in an embodiment where the conductive layer 452 is an inter metal layer, and the conductive layer 452 is formed to expose the periphery 448 of the patterned dielectric layer 446.
Other operations are subsequently performed to complete the fabrication of the IC chip on the wafer 100. For example, in some embodiments, the conductive layer 150 is subsequently planarized using a Chemical Mechanical Planarization (CMP) process, and one or more passivation layers and bump structures are formed thereon.
FIGS. 4A-4F are cross-sectional views of a semiconductor structure 400 at various manufacture stages in accordance with one or more embodiments.
As depicted in FIG. 4A, the semiconductor structure 400 has a substrate 420, an intermediate structure 430 over the substrate 420, a layer of dielectric material 440 over the semiconductor substrate 420 and the intermediate structure 430, and a photoresist layer 442 over the layer of dielectric material 440. The substrate 420 is usable as the substrate 120 of the wafer 100 depicted in FIG. 1 and has a diameter, which is the same as the diameter D of the wafer 100 as depicted in FIG. 1. The substrate 420 has a main portion 422 and a bevel portion 424. The main portion 422 has a substantially constant thickness, and the bevel portion 424 has a tapered shape extending from a periphery 426 of the substrate 420 inwardly. The intermediate structure 430 corresponds to the intermediate structure 130 of the wafer 100 and includes a plurality of active or passive electrical components.
The layer of dielectric material 440 is formed over the intermediate structure 430 and the substrate 420. (Operation 310). In some embodiments, the layer of dielectric material 440 comprises silicon dioxide or silicon nitride. The layer of dielectric material 440 is formed by performing a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal oxidation process, a furnace process, other deposition processes, or combinations thereof. The photoresist layer 442 is then formed over the layer of dielectric material 440 by spin-coating or other suitable process. (Operation 320).
As depicted in FIG. 4B, an edge portion of the photoresist layer 442 is removed to form an edge-processed photoresist layer 454. (Operation 330). The edge-processed photoresist layer 444 is then patterned by a lithography process. Then, as depicted in FIG. 4C, using the patterned photoresist layer 444, the layer of dielectric material 440 is patterned to form a patterned dielectric layer 446. The edge-processed photoresist layer 444 is subsequently removed by an ashing process. (Operation 340). In at least one embodiment, in order to form openings with various widths and depths for the formation of trenches and/or vias, another photoresist layer is then formed over the patterned dielectric layer 446, and operations 320-340 are repeated until the patterning of the layer of the dielectric material 440 is completed.
As depicted in FIG. 4D, a layer of conductive material 450 is formed over the patterned dielectric layer 446. (Operation 350). In some embodiments, the layer of conductive material 450 comprises a metallic material such as copper, aluminum, aluminum-copper alloy, silver, gold, silver alloy, gold alloy, or combinations thereof. In at least one embodiment, the layer of conductive material 450 is formed by electroplating of the metallic material. Then, as depicted in FIG. 4E, an edge portion of the layer of conductive material 450 is removed to form a conductive layer 452. In at least one embodiment where the conductive layer 452 is a top metal layer, operation 360 is omitted.
The periphery 448 of the dielectric layer and the periphery 428 of the main portion 422 of the substrate 420 are separated by a first distance L1. A periphery 454 of the conductive layer 455 and the periphery 428 of the main portion 422 of the substrate 420 are separated by a second distance L2. In some embodiments, the first distance L1 ranges from about 0.25% of the diameter D to about 0.45% of the diameter D. In some embodiments, the second distance L2 ranges from about a value that is 0.5% of the diameter D less than the first distance L1 to about a value that is 0.5% of the diameter D greater than the first distance L1.
In some embodiments, the relationship between the first distance L1 and the second distance L2 is determined according to the relative sizes of the dielectric layer 446 and the conductive layer 452. For example, the dielectric layer 446 defines a dielectric layer area (S1 in FIG. 1), and the conductive layer 452 defines a conductive layer area (S2 in FIG. 1). In some embodiments, the first distance L1 and the second distance L2 are so determined that a ratio of the conductive layer area S2 to the dielectric layer area S1 ranges from about 99.5% to about 110%. In at least one embodiment where the conductive layer 452 is a top metal layer, the ratio of the conductive layer area S2 to the dielectric layer area S1 ranges from about 100% to about 110%. In at least one embodiment where the conductive layer 452 is a inter metal layer, the ratio of the conductive layer area S2 to the dielectric layer area S1 ranges from about 99.5% to about 100%.
As depicted in FIG. 4F, other operations are subsequently performed to complete the fabrication of the IC chip on the wafer 100. For example, in some embodiments, the conductive layer 452 is subsequently planarized using a CMP process to form conductive lines and via plugs 456, and one or more passivation layers and bump structures are formed thereon.
FIG. 5 is a schematic perspective view of an example of the removal of an edge portion of a photoresist layer 442 or a layer of conductive material 450 formed over a substrate 420 in accordance with one or more embodiments.
In at least one embodiment for removing the edge portion of the photoresist layer 442, the substrate 420 of the wafer 100 is placed on a chuck table and spun by driving a motor of the chuck table. A nozzle 510 is placed over the wafer 100 and sprays a solution 520 onto the wafer 100 at the edge portion 530 of the wafer 100, and thus to etch the edge portion of the photoresist layer 442. In some embodiments, the solution 520 used to remove the edge portion of the photoresist layer 442 comprises H2SO4 or H2O2.
In at least one embodiment for removing the edge portion of the layer of conductive material 450, the substrate 420 of the wafer 100 is placed on the chuck table for spinning by the motor of the chuck table. The nozzle 510 is placed over the wafer 100 and sprays a solution 520 onto the wafer 100 at the edge portion 530 of the wafer 100, and thus to etch the edge portion of the layer of conductive material 450. In some embodiments, the solution 520 used to remove the edge portion of the layer of conductive material 450 comprises H2SO4 or H2O2.
In accordance with some embodiments, a wafer includes a substrate, a dielectric layer over the substrate, and a conductive layer over the dielectric layer. The substrate has a main portion having a substantially constant thickness. A periphery of the dielectric layer and a periphery of the main portion being separated by a first distance, and a periphery of the conductive layer and the periphery of the main portion being separated by a second distance. The second distance ranges from about a value that is 0.5% of a diameter of the substrate less than the first distance to about a value that is 0.5% of the diameter of the substrate greater than the first distance.
In accordance with some embodiments, a method of forming a semiconductor structure is disclosed. According to the method, a layer of dielectric material is formed over a substrate, and the substrate has a main portion. A photoresist layer is formed over the layer of dielectric material. An edge portion of the photoresist layer is removed to form an edge-processed photoresist layer. The layer of dielectric material is patterned based on the edge-processed photoresist layer to form a patterned dielectric layer. A periphery of the patterned dielectric layer and a periphery of the main portion of the substrate are separated by a distance. A conductive layer is formed over the patterned dielectric layer. A periphery of the conductive layer is formed within about 0.5% of a diameter of the substrate to the periphery of the patterned dielectric layer.
In accordance with some embodiments, a method of processing a wafer having a substrate is disclosed. The substrate has a main portion. A dielectric layer is formed over the substrate. The dielectric layer has a periphery and defines a dielectric layer area, and the periphery of the dielectric layer and a periphery of the main portion of the substrate are separated by a distance ranging from about 0.25% to about 0.45% of a diameter of the substrate. A conductive layer is formed over the dielectric layer, and the conductive layer defines a conductive layer area. A ratio of the conductive layer area to the dielectric layer area ranging from about 99.5% to about 110%.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

What is claimed is:
1. A method of forming a semiconductor structure, comprising:
forming a layer of dielectric material over a substrate, the substrate having a main portion, and the main portion having a substantially constant thickness;
forming a photoresist layer over the layer of dielectric material;
removing an edge portion of the photoresist layer to form an edge-processed photoresist layer;
patterning the layer of dielectric material based on the edge-processed photoresist layer to form a patterned dielectric layer, a periphery of the patterned dielectric layer and a periphery of the main portion of the substrate being separated by a distance;
forming a conductive layer over the patterned dielectric layer, a periphery of the conductive layer being within about 0.5% of a diameter of the substrate to the periphery of the patterned dielectric layer.
2. The method of claim 1, wherein the removal of the edge portion of the photoresist layer comprises:
spinning the substrate; and
spraying a solution at the edge portion of the photoresist layer to etch the edge portion of the photoresist layer.
3. The method of claim 2, wherein the solution comprises H2SO4 or H2O2.
4. The method of claim 1, wherein the formation of the conductive layer comprises:
electroplating a metallic layer over the patterned dielectric layer; and
removing an edge portion of the metallic layer to form the conductive layer.
5. The method of claim 4, wherein the removal of the edge portion of the metallic layer comprises:
spinning the substrate; and
spraying a solution at the edge portion of the metallic layer to remove the edge portion of the metallic layer.
6. The method of claim 5, wherein the solution comprises H2SO4 or H2O2.
7. The method of claim 1, wherein the conductive layer is a top metal layer, and the conductive layer is formed to overlay the periphery of the patterned dielectric layer.
8. The method of claim 1, wherein the conductive layer is an inter metal layer, and the conductive layer is formed to expose the periphery of the patterned dielectric layer.
9. A method of processing a wafer including a substrate, the substrate having a flat portion, the method comprising:
forming a dielectric layer over the substrate, the dielectric layer having a dielectric layer area, and a periphery of the dielectric layer and a periphery of the flat portion of the substrate being separated by a distance ranging from about 0.25% to about 0.45% of a diameter of the substrate; and
forming a conductive layer over the dielectric layer, the conductive layer having a conductive layer area,
a ratio of the conductive layer area to the dielectric layer area ranging from about 99.5% to about 110%.
10. The method of claim 9 wherein the formation of the dielectric layer comprises:
forming a layer of dielectric material over the substrate;
forming a photoresist layer over the layer of dielectric material;
spinning the substrate; and
spraying a solution at an edge portion of the photoresist layer to remove the edge portion of the photoresist layer.
11. The method of claim 10, wherein the solution comprises H2SO4 or H2O2.
12. The method of claim 9, wherein the formation of the conductive layer comprises:
electroplating a metallic layer over the dielectric layer;
spinning the substrate; and
spraying a solution at an edge portion of the metallic layer to remove the edge portion of the metallic layer.
13. The method of claim 12, wherein the solution comprises H2SO4 or H2O2.
14. The method of claim 9, wherein the conductive layer is a top metal layer, and the ratio of the conductive layer area to the dielectric layer area ranging from about 100% to about 110%.
15. A method of forming a semiconductor structure, comprising:
forming a layer of dielectric material over a substrate, the substrate having a main portion and a periphery portion, the main portion having a substantially constant thickness, and the periphery portion having a beveled edge;
patterning the layer of dielectric material to form a patterned dielectric layer, an outer edge of the patterned dielectric layer separated from the periphery of the substrate by a first distance;
forming a conductive layer over the patterned dielectric layer, wherein a ratio of a top surface area of the conductive layer to a top surface area of the patterned dielectric layer ranges from about 99.5% to about 110%.
16. The method of claim 15, wherein the ratio of the top surface area of the conductive layer to the top surface area of the patterned dielectric layer ranges from about 99.5% to about 100% if the conductive layer is an inter metal layer.
17. The method of claim 15, wherein the ratio of the top surface area of the conductive layer to the top surface area of the patterned dielectric layer ranges from about 100% to about 110% if the conductive layer is a top metal layer.
18. The method of claim 15, further comprising patterning the conductive layer to form a patterned conductive layer, an outer edge of the patterned conductive layer separated from the periphery of the substrate by a second distance, wherein the second distance is within 0.5% of a diameter of the substrate from the first distance.
19. The method of claim 18, wherein the second distance ranges from a value equal to the first distance to a value 0.5% of the diameter of the substrate less than the first distance if the patterned conductive layer is a top metal layer.
20. The method of claim 18, wherein the second distance ranges from a value equal to the first distance to a value 0.5% of the diameter of the substrate greater than the first distance if the patterned conductive layer is an inter metal layer.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6239035B1 (en) * 1997-07-18 2001-05-29 Agere Systems Guardian Corporation Semiconductor wafer fabrication

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