US9362176B2 - Uniform exposed raised structures for non-planar semiconductor devices - Google Patents

Uniform exposed raised structures for non-planar semiconductor devices Download PDF

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US9362176B2
US9362176B2 US14/319,640 US201414319640A US9362176B2 US 9362176 B2 US9362176 B2 US 9362176B2 US 201414319640 A US201414319640 A US 201414319640A US 9362176 B2 US9362176 B2 US 9362176B2
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uniform
dielectric material
raised
planar
substrate
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US20150380316A1 (en
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Hong Yu
Hongliang Shen
Zhao Lun
Zhenyu Hu
Richard J. Carter
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GlobalFoundries Inc
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GlobalFoundries Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present invention generally relates to non-planar semiconductor structures, and, more particularly, to uniformity among exposed portions of raised structures for non-planar semiconductor devices.
  • a layer of isolation material surrounds the fins.
  • Flowable oxide deposited by Chemical Vapor Deposition (CVD) is typically used as the isolation material, as it has a superior filling capability.
  • CVD Chemical Vapor Deposition
  • TEOS tetraethyl orthosilicate
  • the flowable oxide and HARP oxide have different etch rates, resulting in a non-uniform or unsymmetrical fin profile, which affects device performance and causes other downstream fabrication problems.
  • the shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, of a method of fabricating uniform exposed portions of raised semiconductor structures for non-planar semiconductor devices.
  • the method includes providing a starting non-planar semiconductor structure, the structure including a semiconductor substrate, a plurality of raised semiconductor structures coupled to the substrate and covered with a protective material, an isolation material surrounding the raised structures, and at least one trench through the non-planar structure and into the substrate filled with a dielectric material different than the isolation material.
  • the isolation material has a different etch rate than the dielectric material for a given etch.
  • the method further includes replacing a top portion of the layer of isolation material with the dielectric material to create a uniform top layer of the dielectric material, and recessing the uniform top layer to expose uniform portions of the raised structures.
  • a non-planar semiconductor structure in accordance with another aspect, includes a semiconductor substrate, a plurality of raised semiconductor structures coupled to the substrate, a non-uniform layer of isolation material surrounding bottom portions of the plurality of raised semiconductor structures, at least one trench through the non-planar structure and into the substrate, the at least one trench filled with only a dielectric material different from the isolation material and having a different etch rate than the isolation material for a given etch.
  • a top layer of the dielectric material is situated above the non-uniform layer of isolation material and in the at least one trench, and a top surface of the top layer has a uniform height below uniform exposed portions of the plurality of raised semiconductor structures.
  • FIG. 1 is a cross-sectional view of one example of a starting non-planar semiconductor structure, the structure including a substrate and multiple raised semiconductor structures coupled to the substrate, the raised structures being surrounded by a layer of isolation material and covered with a hard mask, the structure further including deep trenches filled with a dielectric material different than the isolation material, in accordance with one or more aspects of the present invention.
  • FIG. 2 depicts one example of the non-planar structure of FIG. 1 after recessing the isolation layer and the dielectric material, exposing a non-uniform portion of the raised structures, in accordance with one or more aspects of the present invention.
  • FIG. 3 depicts one example of the non-planar structure of FIG. 2 after filling openings created by the recessing with more of the dielectric material, in accordance with one or more aspects of the present invention.
  • FIG. 4 depicts one example of the non-planar structure of FIG. 3 after removal of the hard mask over the raised structures and planarizing a top surface of the non-planar structure, in accordance with one or more aspects of the present invention.
  • FIG. 5 depicts one example of the non-planar structure of FIG. 4 after recessing of the added dielectric material, exposing a uniform portion of the raised structures, in accordance with one or more aspects of the present invention.
  • Approximating language may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value.
  • a method or device that “comprises,” “has,” “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements.
  • a step of a method or an element of a device that “comprises,” “has,” “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features.
  • a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
  • connection when used to refer to two physical elements, means a direct connection between the two physical elements.
  • coupled can mean a direct connection or a connection through one or more intermediary elements.
  • the terms “may” and “may be” indicate a possibility of an occurrence within a set of circumstances; a possession of a specified property, characteristic or function; and/or qualify another verb by expressing one or more of an ability, capability, or possibility associated with the qualified verb. Accordingly, usage of “may” and “may be” indicates that a modified term is apparently appropriate, capable, or suitable for an indicated capacity, function, or usage, while taking into account that in some circumstances the modified term may sometimes not be appropriate, capable or suitable. For example, in some circumstances, an event or capacity can be expected, while in other circumstances the event or capacity cannot occur—this distinction is captured by the terms “may” and “may be.”
  • FIG. 1 is a cross-sectional view of one example of a starting non-planar semiconductor structure 100 , the structure including a substrate 102 and multiple raised semiconductor structures 104 coupled to the substrate, the raised structures being surrounded by a layer of isolation material 106 and covered with a protective material 108 (e.g., a hard mask), the structure further including deep trenches 110 filled with a dielectric material 112 different than the isolation material, in accordance with one or more aspects of the present invention.
  • the isolation material may be, for example, a flowable oxide, deposited, e.g., using Chemical Vapor Deposition (CVD), the dielectric material may be, for example, a HARP oxide, and the protective material may be, for example, silicon nitride (SiN).
  • CVD Chemical Vapor Deposition
  • SiN silicon nitride
  • the starting structure may generally be conventionally fabricated, for example, using known processes and techniques. For example, after filling the trenches with HARP oxide, the structure would be annealed and the HARP oxide planarized using, for example, a chemical-mechanical polishing (CMP) technique.
  • CMP chemical-mechanical polishing
  • substrate 102 may include any silicon-containing substrate including, but not limited to, silicon (Si), single crystal silicon, polycrystalline Si, amorphous Si, silicon-on-nothing (SON), silicon-on-insulator (SOI) or silicon-on-replacement insulator (SRI) or silicon germanium substrates and the like.
  • substrate 102 may in addition or instead include various isolations, dopings and/or device features.
  • the substrate may include other suitable elementary semiconductors, such as, for example, germanium (Ge) in crystal, a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb) or combinations thereof; an alloy semiconductor including GaAsP, AlInAs, GaInAs, GaInP, or GaInAsP or combinations thereof.
  • germanium germanium
  • SiC silicon carbide
  • GaAs gallium arsenide
  • GaP gallium phosphide
  • InP indium phosphide
  • InAs indium arsenide
  • InSb indium antimonide
  • raised structures 104 may take the form of “fins.”
  • the raised structure(s) may, for example, be etched from a bulk substrate, and may include, for example, any of the materials listed above with respect to the substrate. Further, some or all of the raised structure(s) may include added impurities (e.g., by doping), making them n-type or p-type.
  • FIG. 2 depicts one example of the non-planar structure of FIG. 1 after recessing the isolation material 106 and the dielectric material 112 , exposing a non-uniform portion of the raised structures, for example, raised structure 114 has less of side 116 exposed than side 118 , in accordance with one or more aspects of the present invention.
  • Recessing the isolation material and the dielectric material may be done, for example, with one or more etching processes.
  • a series of three processes are performed to remove the isolation and dielectric materials—a reactive ion etch, followed by a Chemical Oxide Removal (COR) process and ending with a SiCoNi dry etch.
  • COR Chemical Oxide Removal
  • a single SiCoNi dry etch may be used for a longer time.
  • FIG. 3 depicts one example of the non-planar structure of FIG. 2 after filling openings ( 120 , FIG. 2 ) created by the recessing with more of the dielectric material 112 , creating a top layer 122 of the dielectric material, in accordance with one or more aspects of the present invention.
  • the filling of the openings may be accomplished, for example, with a CVD process, and may be followed by an anneal in an atmosphere of nitrogen gas at a temperature of about 1050° for about 20 minutes to about 50 minutes. Further, the anneal may be followed by planarizing, for example, using CMP and stopping on the protective material 108 above the raised structures.
  • FIG. 4 depicts one example of the non-planar structure of FIG. 3 after removal of the protective material ( 108 , FIG. 3 ) and planarizing a top surface 124 of the non-planar structure 100 , in accordance with one or more aspects of the present invention.
  • Removal of the protective material over the raised structures and planarizing may be accomplished by, for example, a deglaze process followed by a strip process.
  • the deglaze process may take the form of a wet etch using, e.g., hydrofluoric acid, which removes the isolation material
  • the strip process may take the form of a wet etch using H 3 PO 4 (Phosphoric Acid), which is selective to nitrogen.
  • FIG. 5 depicts one example of the non-planar structure of FIG. 4 after recessing the top layer 122 of the dielectric material 112 , exposing a uniform portion of the raised structures (e.g., portion 126 of raised structure 114 ), in accordance with one or more aspects of the present invention. Recessing of the top layer of dielectric material may be accomplished, for example, in the same manner as described above with respect to the recess of FIG. 2 .
  • a method of fabricating uniform exposed portions of raised semiconductor structures for non-planar semiconductor devices includes providing a starting non-planar semiconductor structure, the structure including a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate and covered with a protective material, for example, a hard mask (e.g., silicon nitride), an isolation material (e.g., a flowable oxide) surrounding the raised structures, and at least one trench through the non-planar structure and into the substrate filled with a dielectric material that is different from the isolation material (e.g., a HARP oxide).
  • the isolation material also has a different etch rate than the dielectric material for a given etch.
  • the method further includes replacing a top portion of the layer of isolation material with additional dielectric material to create a uniform top layer of the dielectric material, and recessing the uniform top layer to expose uniform portions of the raised structures.
  • the replacing of a portion of the isolation material in the method of the first aspect may include, for example, recessing the layer of isolation material and the dielectric material to expose non-uniform portions of the raised structures, the recessing creating non-uniform openings, and filling the non-uniform openings with the additional dielectric material to create the uniform top layer of the dielectric material.
  • the recessing may include recessing about 80 nm to about 100 nm below a top surface of the protective material covering the raised structures.
  • the method of the first aspect may further include, for example, after the replacing and before the recessing, removing the protective material covering the raised structures, and planarizing the non-planar structure.
  • a non-planar semiconductor structure in a second aspect, disclosed above is a non-planar semiconductor structure.
  • the structure includes a semiconductor substrate (e.g., a bulk semiconductor substrate), multiple raised semiconductor structures coupled to the substrate, a non-uniform layer of isolation material between adjacent raised structures, at least one trench through the non-planar structure and into the substrate, the trench(s) filled with a dielectric material different from the isolation material and having a different etch rate than the isolation material for a given etch, and a top layer of the dielectric material above the non-uniform layer of isolation material and in the trench(s).
  • a top surface of the top layer has a uniform height below uniform exposed portions of the raised semiconductor structures.
  • a height of the uniform exposed portions of the non-planar semiconductor structure of the second aspect may be, for example, about 40 nm to about 60 nm.
  • the isolation material of the non-planar semiconductor structure of the second aspect may include, for example, flowable oxide, and the dielectric material may include, for example, a HARP oxide.

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Abstract

The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures.

Description

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to non-planar semiconductor structures, and, more particularly, to uniformity among exposed portions of raised structures for non-planar semiconductor devices.
2. Background Information
In the fabrication of non-planar semiconductor devices, for example, FinFETs (transistors with raised structures resembling fins on a bulk substrate), a layer of isolation material surrounds the fins. Flowable oxide deposited by Chemical Vapor Deposition (CVD) is typically used as the isolation material, as it has a superior filling capability. Also included are deep trenches into the bulk substrate filled with an oxide deposited by a High Aspect Ratio Process (HARP), which involves using O3 in the presence of tetraethyl orthosilicate (TEOS). However, the flowable oxide and HARP oxide have different etch rates, resulting in a non-uniform or unsymmetrical fin profile, which affects device performance and causes other downstream fabrication problems.
Therefore, a need exists for more uniform profiles of exposed portions of raised structures in the fabrication of non-planar semiconductor devices.
SUMMARY OF THE INVENTION
The shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, of a method of fabricating uniform exposed portions of raised semiconductor structures for non-planar semiconductor devices. The method includes providing a starting non-planar semiconductor structure, the structure including a semiconductor substrate, a plurality of raised semiconductor structures coupled to the substrate and covered with a protective material, an isolation material surrounding the raised structures, and at least one trench through the non-planar structure and into the substrate filled with a dielectric material different than the isolation material. The isolation material has a different etch rate than the dielectric material for a given etch. The method further includes replacing a top portion of the layer of isolation material with the dielectric material to create a uniform top layer of the dielectric material, and recessing the uniform top layer to expose uniform portions of the raised structures.
In accordance with another aspect, a non-planar semiconductor structure is provided. The structure includes a semiconductor substrate, a plurality of raised semiconductor structures coupled to the substrate, a non-uniform layer of isolation material surrounding bottom portions of the plurality of raised semiconductor structures, at least one trench through the non-planar structure and into the substrate, the at least one trench filled with only a dielectric material different from the isolation material and having a different etch rate than the isolation material for a given etch. A top layer of the dielectric material is situated above the non-uniform layer of isolation material and in the at least one trench, and a top surface of the top layer has a uniform height below uniform exposed portions of the plurality of raised semiconductor structures.
These, and other objects, features and advantages of this invention will become apparent from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view of one example of a starting non-planar semiconductor structure, the structure including a substrate and multiple raised semiconductor structures coupled to the substrate, the raised structures being surrounded by a layer of isolation material and covered with a hard mask, the structure further including deep trenches filled with a dielectric material different than the isolation material, in accordance with one or more aspects of the present invention.
FIG. 2 depicts one example of the non-planar structure of FIG. 1 after recessing the isolation layer and the dielectric material, exposing a non-uniform portion of the raised structures, in accordance with one or more aspects of the present invention.
FIG. 3 depicts one example of the non-planar structure of FIG. 2 after filling openings created by the recessing with more of the dielectric material, in accordance with one or more aspects of the present invention.
FIG. 4 depicts one example of the non-planar structure of FIG. 3 after removal of the hard mask over the raised structures and planarizing a top surface of the non-planar structure, in accordance with one or more aspects of the present invention.
FIG. 5 depicts one example of the non-planar structure of FIG. 4 after recessing of the added dielectric material, exposing a uniform portion of the raised structures, in accordance with one or more aspects of the present invention.
 DETAILED DESCRIPTION OF THE INVENTION
Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating aspects of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions, and/or arrangements, within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure.
Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value.
The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include (and any form of include, such as “includes” and “including”), and “contain” (and any form of contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises,” “has,” “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises,” “has,” “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
As used herein, the term “connected,” when used to refer to two physical elements, means a direct connection between the two physical elements. The term “coupled,” however, can mean a direct connection or a connection through one or more intermediary elements.
As used herein, the terms “may” and “may be” indicate a possibility of an occurrence within a set of circumstances; a possession of a specified property, characteristic or function; and/or qualify another verb by expressing one or more of an ability, capability, or possibility associated with the qualified verb. Accordingly, usage of “may” and “may be” indicates that a modified term is apparently appropriate, capable, or suitable for an indicated capacity, function, or usage, while taking into account that in some circumstances the modified term may sometimes not be appropriate, capable or suitable. For example, in some circumstances, an event or capacity can be expected, while in other circumstances the event or capacity cannot occur—this distinction is captured by the terms “may” and “may be.”
Reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers are used throughout different figures to designate the same or similar components.
FIG. 1 is a cross-sectional view of one example of a starting non-planar semiconductor structure 100, the structure including a substrate 102 and multiple raised semiconductor structures 104 coupled to the substrate, the raised structures being surrounded by a layer of isolation material 106 and covered with a protective material 108 (e.g., a hard mask), the structure further including deep trenches 110 filled with a dielectric material 112 different than the isolation material, in accordance with one or more aspects of the present invention. The isolation material may be, for example, a flowable oxide, deposited, e.g., using Chemical Vapor Deposition (CVD), the dielectric material may be, for example, a HARP oxide, and the protective material may be, for example, silicon nitride (SiN).
The starting structure may generally be conventionally fabricated, for example, using known processes and techniques. For example, after filling the trenches with HARP oxide, the structure would be annealed and the HARP oxide planarized using, for example, a chemical-mechanical polishing (CMP) technique. However, it will be understood that the fabrication of the starting structure forms no part of the present invention. Further, although only a portion of the overall structure is shown for simplicity, it will be understood that, in practice, many such structures are typically included on the same bulk substrate.
In one example, substrate 102 may include any silicon-containing substrate including, but not limited to, silicon (Si), single crystal silicon, polycrystalline Si, amorphous Si, silicon-on-nothing (SON), silicon-on-insulator (SOI) or silicon-on-replacement insulator (SRI) or silicon germanium substrates and the like. Substrate 102 may in addition or instead include various isolations, dopings and/or device features. The substrate may include other suitable elementary semiconductors, such as, for example, germanium (Ge) in crystal, a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb) or combinations thereof; an alloy semiconductor including GaAsP, AlInAs, GaInAs, GaInP, or GaInAsP or combinations thereof.
In one example, raised structures 104 may take the form of “fins.” The raised structure(s) may, for example, be etched from a bulk substrate, and may include, for example, any of the materials listed above with respect to the substrate. Further, some or all of the raised structure(s) may include added impurities (e.g., by doping), making them n-type or p-type.
FIG. 2 depicts one example of the non-planar structure of FIG. 1 after recessing the isolation material 106 and the dielectric material 112, exposing a non-uniform portion of the raised structures, for example, raised structure 114 has less of side 116 exposed than side 118, in accordance with one or more aspects of the present invention.
Recessing the isolation material and the dielectric material may be done, for example, with one or more etching processes. In one example, a series of three processes are performed to remove the isolation and dielectric materials—a reactive ion etch, followed by a Chemical Oxide Removal (COR) process and ending with a SiCoNi dry etch. In another example, a single SiCoNi dry etch may be used for a longer time.
FIG. 3 depicts one example of the non-planar structure of FIG. 2 after filling openings (120, FIG. 2) created by the recessing with more of the dielectric material 112, creating a top layer 122 of the dielectric material, in accordance with one or more aspects of the present invention. The filling of the openings may be accomplished, for example, with a CVD process, and may be followed by an anneal in an atmosphere of nitrogen gas at a temperature of about 1050° for about 20 minutes to about 50 minutes. Further, the anneal may be followed by planarizing, for example, using CMP and stopping on the protective material 108 above the raised structures.
FIG. 4 depicts one example of the non-planar structure of FIG. 3 after removal of the protective material (108, FIG. 3) and planarizing a top surface 124 of the non-planar structure 100, in accordance with one or more aspects of the present invention.
Removal of the protective material over the raised structures and planarizing may be accomplished by, for example, a deglaze process followed by a strip process. In one example, where the protective material includes silicon nitride, the deglaze process may take the form of a wet etch using, e.g., hydrofluoric acid, which removes the isolation material, and the strip process may take the form of a wet etch using H3PO4 (Phosphoric Acid), which is selective to nitrogen.
FIG. 5 depicts one example of the non-planar structure of FIG. 4 after recessing the top layer 122 of the dielectric material 112, exposing a uniform portion of the raised structures (e.g., portion 126 of raised structure 114), in accordance with one or more aspects of the present invention. Recessing of the top layer of dielectric material may be accomplished, for example, in the same manner as described above with respect to the recess of FIG. 2.
In a first aspect, disclosed above is a method of fabricating uniform exposed portions of raised semiconductor structures for non-planar semiconductor devices. The method includes providing a starting non-planar semiconductor structure, the structure including a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate and covered with a protective material, for example, a hard mask (e.g., silicon nitride), an isolation material (e.g., a flowable oxide) surrounding the raised structures, and at least one trench through the non-planar structure and into the substrate filled with a dielectric material that is different from the isolation material (e.g., a HARP oxide). The isolation material also has a different etch rate than the dielectric material for a given etch. The method further includes replacing a top portion of the layer of isolation material with additional dielectric material to create a uniform top layer of the dielectric material, and recessing the uniform top layer to expose uniform portions of the raised structures.
The replacing of a portion of the isolation material in the method of the first aspect may include, for example, recessing the layer of isolation material and the dielectric material to expose non-uniform portions of the raised structures, the recessing creating non-uniform openings, and filling the non-uniform openings with the additional dielectric material to create the uniform top layer of the dielectric material. In one example, the recessing may include recessing about 80 nm to about 100 nm below a top surface of the protective material covering the raised structures.
The method of the first aspect may further include, for example, after the replacing and before the recessing, removing the protective material covering the raised structures, and planarizing the non-planar structure.
In a second aspect, disclosed above is a non-planar semiconductor structure. The structure includes a semiconductor substrate (e.g., a bulk semiconductor substrate), multiple raised semiconductor structures coupled to the substrate, a non-uniform layer of isolation material between adjacent raised structures, at least one trench through the non-planar structure and into the substrate, the trench(s) filled with a dielectric material different from the isolation material and having a different etch rate than the isolation material for a given etch, and a top layer of the dielectric material above the non-uniform layer of isolation material and in the trench(s). A top surface of the top layer has a uniform height below uniform exposed portions of the raised semiconductor structures.
A height of the uniform exposed portions of the non-planar semiconductor structure of the second aspect may be, for example, about 40 nm to about 60 nm.
The isolation material of the non-planar semiconductor structure of the second aspect may include, for example, flowable oxide, and the dielectric material may include, for example, a HARP oxide.
While several aspects of the present invention have been described and depicted herein, alternative aspects may be effected by those skilled in the art to accomplish the same objectives. Accordingly, it is intended by the appended claims to cover all such alternative aspects as fall within the true spirit and scope of the invention.

Claims (4)

The invention claimed is:
1. A non-planar semiconductor structure, comprising:
a semiconductor substrate;
a plurality of raised semiconductor structures coupled to the substrate, a non-uniform layer of isolation material surrounding bottom portions of the plurality of raised semiconductor structures;
at least one trench through the non-planar structure and into the substrate, the at least one trench filled with only a dielectric material different from the isolation material and having a different etch rate than the isolation material for a given etch; and
wherein a top layer of the dielectric material is situated above the non-uniform layer of isolation material and in the at least one trench, and wherein a top surface of the top layer has a uniform height below uniform exposed portions of the plurality of raised semiconductor structures.
2. The non-planar semiconductor structure of claim 1, wherein a height of the uniform exposed portions is about 40 nm to about 60 nm.
3. The non-planar semiconductor structure of claim 1, wherein the isolation material comprises flowable oxide, and wherein the dielectric material comprises a HARP oxide.
4. The non-planar semiconductor structure of claim 1, wherein the top layer of the dielectric material is wider in cross-section taken through the plurality of raised semiconductor structures, than a remainder of the dielectric material therebelow.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9865598B1 (en) 2017-03-06 2018-01-09 International Business Machines Corporation FinFET with uniform shallow trench isolation recess

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102310076B1 (en) * 2015-04-23 2021-10-08 삼성전자주식회사 Semiconductor devices having a source/drain ofasymmetrical shape
KR102398862B1 (en) 2015-05-13 2022-05-16 삼성전자주식회사 Semiconductor device and the fabricating method thereof
CN106711213B (en) * 2015-07-20 2021-02-26 联华电子股份有限公司 Semiconductor element and manufacturing method thereof
US9799529B2 (en) * 2016-03-17 2017-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of planarizing a film layer
US10515952B2 (en) * 2017-08-04 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure and method for forming the same
JP7042726B2 (en) * 2018-10-04 2022-03-28 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
CN113838952B (en) * 2021-09-06 2023-10-27 厦门乾照半导体科技有限公司 Nano-LED application-based epitaxial structure, chip and preparation method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140051227A1 (en) * 2012-08-14 2014-02-20 Globalfoundries Inc. Methods of forming isolation structures for semiconductor devices by performing a dry chemical removal process
US20140264522A1 (en) * 2013-03-14 2014-09-18 International Business Machines Corporation Semiconductor structures with deep trench capacitor and methods of manufacture
US9048259B2 (en) * 2008-12-31 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric punch-through stoppers for forming FinFETs having dual fin heights

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9048259B2 (en) * 2008-12-31 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric punch-through stoppers for forming FinFETs having dual fin heights
US20140051227A1 (en) * 2012-08-14 2014-02-20 Globalfoundries Inc. Methods of forming isolation structures for semiconductor devices by performing a dry chemical removal process
US20140264522A1 (en) * 2013-03-14 2014-09-18 International Business Machines Corporation Semiconductor structures with deep trench capacitor and methods of manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9865598B1 (en) 2017-03-06 2018-01-09 International Business Machines Corporation FinFET with uniform shallow trench isolation recess

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