JP2018518828A5 - - Google Patents

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Publication number
JP2018518828A5
JP2018518828A5 JP2017555753A JP2017555753A JP2018518828A5 JP 2018518828 A5 JP2018518828 A5 JP 2018518828A5 JP 2017555753 A JP2017555753 A JP 2017555753A JP 2017555753 A JP2017555753 A JP 2017555753A JP 2018518828 A5 JP2018518828 A5 JP 2018518828A5
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JP
Japan
Prior art keywords
insulated wire
wire
die
insulated
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2017555753A
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English (en)
Japanese (ja)
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JP2018518828A (ja
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Publication date
Application filed filed Critical
Priority claimed from PCT/US2015/038109 external-priority patent/WO2016209286A1/en
Publication of JP2018518828A publication Critical patent/JP2018518828A/ja
Publication of JP2018518828A5 publication Critical patent/JP2018518828A5/ja
Pending legal-status Critical Current

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JP2017555753A 2015-06-26 2015-06-26 集合化された絶縁ワイヤを含むパッケージ・アセンブリ Pending JP2018518828A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/038109 WO2016209286A1 (en) 2015-06-26 2015-06-26 Package assembly with gathered insulated wires

Publications (2)

Publication Number Publication Date
JP2018518828A JP2018518828A (ja) 2018-07-12
JP2018518828A5 true JP2018518828A5 (enExample) 2018-08-23

Family

ID=57585304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017555753A Pending JP2018518828A (ja) 2015-06-26 2015-06-26 集合化された絶縁ワイヤを含むパッケージ・アセンブリ

Country Status (8)

Country Link
US (1) US9935036B2 (enExample)
EP (1) EP3314651B1 (enExample)
JP (1) JP2018518828A (enExample)
KR (1) KR102422980B1 (enExample)
CN (1) CN108064417B (enExample)
SG (1) SG11201708367SA (enExample)
TW (1) TWI741983B (enExample)
WO (1) WO2016209286A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10734321B2 (en) 2017-09-28 2020-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit and method of manufacturing same
DE102018123548B4 (de) 2017-09-28 2025-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrierte schaltung und verfahren zur herstellung derselben
US11562979B2 (en) 2018-06-27 2023-01-24 Mitsubishi Electric Corporation Power module and method of manufacturing the same, and power conversion apparatus
JP6971952B2 (ja) 2018-11-07 2021-11-24 三菱電機株式会社 半導体装置
TWI763110B (zh) * 2020-11-04 2022-05-01 瑞昱半導體股份有限公司 球柵陣列封裝及其封裝基板
US20230402818A1 (en) * 2022-06-08 2023-12-14 Airoha Technology Corp. Semiconductor package having ground bonding wire that crosses over signal bonding wire for crosstalk reduction and associated method
JP7784974B2 (ja) * 2022-09-08 2025-12-12 三菱電機株式会社 半導体装置の製造方法
WO2025177212A1 (en) * 2024-02-21 2025-08-28 Baker Hughes Inteq Gmbh Mechanically coupling multiple wires to improve robustness of wire bond interconnections against mechanical vibrations and shock

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5818949A (ja) * 1981-07-28 1983-02-03 Nec Corp 半導体装置
JP2880734B2 (ja) * 1989-08-31 1999-04-12 株式会社東芝 集積回路及びその接続回路
JP3690342B2 (ja) * 2001-12-10 2005-08-31 凸版印刷株式会社 ボンディングワイヤ及びそれを用いた半導体装置
JP4271435B2 (ja) * 2002-12-09 2009-06-03 シャープ株式会社 半導体装置
US20040119172A1 (en) 2002-12-18 2004-06-24 Downey Susan H. Packaged IC using insulated wire
US6812580B1 (en) * 2003-06-09 2004-11-02 Freescale Semiconductor, Inc. Semiconductor package having optimized wire bond positioning
US20060175712A1 (en) * 2005-02-10 2006-08-10 Microbonds, Inc. High performance IC package and method
US7675168B2 (en) * 2005-02-25 2010-03-09 Agere Systems Inc. Integrated circuit with staggered differential wire bond pairs
US7626123B2 (en) * 2005-12-12 2009-12-01 Raytheon Sarcos, Llc Electrical microfilament to circuit interface
US7538413B2 (en) 2006-12-28 2009-05-26 Micron Technology, Inc. Semiconductor components having through interconnects
US7825527B2 (en) * 2008-06-13 2010-11-02 Altera Corporation Return loss techniques in wirebond packages for high-speed data communications
US7718471B1 (en) 2008-11-12 2010-05-18 White Electronic Designs Corporation Method and apparatus for stacked die package with insulated wire bonds
US9184151B2 (en) * 2011-03-11 2015-11-10 Cypress Semiconductor Corporation Mixed wire bonding profile and pad-layout configurations in IC packaging processes for high-speed electronic devices
US8723338B2 (en) 2012-08-15 2014-05-13 Stats Chippac Ltd. Integrated circuit packaging system with array contacts and method of manufacture thereof
US9078352B2 (en) * 2012-10-29 2015-07-07 Avago Technologies General Ip (Singapore) Pte. Ltd. Low inductance flex bond with low thermal resistance
US9613877B2 (en) * 2013-10-10 2017-04-04 UTAC Headquarters Pte. Ltd. Semiconductor packages and methods for forming semiconductor package

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