JP2018190760A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2018190760A JP2018190760A JP2017089407A JP2017089407A JP2018190760A JP 2018190760 A JP2018190760 A JP 2018190760A JP 2017089407 A JP2017089407 A JP 2017089407A JP 2017089407 A JP2017089407 A JP 2017089407A JP 2018190760 A JP2018190760 A JP 2018190760A
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- Prior art keywords
- power supply
- circuit
- switch circuit
- region
- power switch
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】半導体基板に形成された第1回路と、前記半導体基板に形成された第2回路と、第1電源線と、前記第1回路に接続する第2電源線と、第1接地線と、第3電源線と、前記第2回路に接続する第4電源線と、第2接地線と、ソース・ドレインの一端が前記第1電源線に接続し、他端が前記第2電源線に接続する第1スイッチトランジスタと、前記第2電源線と電気的に接続する前記半導体基板のウェルタップと、を有する第1スイッチ回路と、ソース・ドレインの一端が前記第3電源線に接続し、他端が前記第4電源線に接続する第2スイッチトランジスタを有し、前記第4電源線と電気的に接続する前記半導体基板のウェルタップを有さない第2スイッチ回路と、を有することを特徴とする半導体装置である。
【選択図】図3
Description
以下に図面を参照して、第一の実施形態の説明に先立ち、パワーゲーティングについて説明する。
以下に図面を参照して第二の実施形態について説明する。第二の実施形態では、電源スイッチ部が、2段のバッファ及びトランジスタを有する2入力2出力である点が、第一の実施形態と相違する。よって、以下の第二の実施形態の説明では、第一の実施形態との相違点についてのみ説明し、第一の実施形態と同様の機能構成を有するものには、第一の実施形態の説明で用いた符号と同様の符号を付与し、その説明を省略する。
以下に図面を参照して第三の実施形態について説明する。第三の実施形態では、トランジスタ25のソース・ドレイン領域を形成するP型不純物領域221と、電源配線205、206との接続点を増やした点が、第一の実施形態と相違する。よって、以下の第三の実施形態の説明では、第一の実施形態との相違点についてのみ説明し、第一の実施形態と同様の機能構成を有するものには、第一の実施形態の説明で用いた符号と同様の符号を付与し、その説明を省略する。
22−1、22−2 ウェルタップ領域
25、35、45、55 トランジスタ
26、36、46、56 バッファ
30 半導体装置
32−1、32−2 エンドキャップ領域
40 スタンダードセル
42 第1領域
43 第2領域
50 RAM
200、200A、200B、210、210A、210B 電源スイッチ回路
202〜204、302〜304 N型ウェル
205〜207、305〜307 電源配線
208、308 ゲート電極
221〜226、321〜324 P型不純物領域
231〜234、331〜336 N型不純物領域
281〜283、381〜383 STI
Claims (10)
- 半導体基板に形成された第1回路と、
前記半導体基板に形成された第2回路と、
第1電源線と、
前記第1回路に接続する第2電源線と、
第1接地線と、
第3電源線と、
前記第2回路に接続する第4電源線と、
第2接地線と、
ソース・ドレインの一端が前記第1電源線に接続し、他端が前記第2電源線に接続する第1スイッチトランジスタと、前記第2電源線と電気的に接続する前記半導体基板のウェルタップと、を有する第1スイッチ回路と、
ソース・ドレインの一端が前記第3電源線に接続し、他端が前記第4電源線に接続する第2スイッチトランジスタを有し、前記第4電源線と電気的に接続する前記半導体基板のウェルタップを有さない第2スイッチ回路と、を有することを特徴とする半導体装置。 - 前記第2電源線及び前記第4電源線、前記第1接地線、前記第2接地線が第1方向に延在し、
前記第1方向における前記第2スイッチ回路の長さは、前記第1方向における前記第1スイッチ回路の長さよりも短い、ことを特徴とする請求項1記載の半導体装置。 - 前記第1スイッチ回路は、前記第1回路と隣接して配置され、
前記第2スイッチ回路は、前記第2回路と隣接して配置される、ことを特徴とする請求項2記載の半導体装置。 - 複数の前記第2スイッチ回路は、前記第2回路に隣接して配置され、
複数の前記第2スイッチ回路が、前記第1方向と直交する第2方向に向かって配置される、ことを特徴とする請求項2又は3記載の半導体装置。 - 前記第2スイッチ回路は、平面視で複数の前記第2回路の間に配置される、ことを特徴とする請求項2乃至4の何れか一項に記載の半導体装置。
- 前記第4電源線及び前記第2接地線は、前記第1回路及び前記第2回路が配置される設計領域の端で途切れ、
前記第2スイッチ回路は、前記第2回路と前記設計領域の端との間に配置される、ことを特徴とする請求項2乃至5の何れか一項に記載の半導体装置。 - 前記第2スイッチ回路は、前記第1方向における、前記第2スイッチトランジスタの両側に、前記第2スイッチトランジスタと隣接して設けられたエンドキャップ領域を有する、ことを特徴とする請求項2乃至6の何れか一項に記載の半導体装置。
- 前記第2回路は、前記第1回路と電気的に接続する端子を有し、前記第2スイッチ回路は、前記端子が配置されていない側の前記第2回路の端に隣接して配置される、
ことを特徴とする請求項2乃至7の何れか一項に記載の半導体装置。 - 前記第1電源線及び前記第2電源線は、前記第1スイッチトランジスタ上で分岐し、
前記第1スイッチトランジスタの不純物領域と、複数箇所で接続し、
前記第3電源線及び前記第4電源線は、前記第2スイッチトランジスタ上で分岐し、
前記第2スイッチトランジスタの不純物領域と、複数箇所で接続する、ことを特徴とする請求項2乃至8の何れか一項に記載の半導体装置。 - 前記第1スイッチトランジスタと、前記第2スイッチトランジスタとは、同じ構造である、ことを特徴とする請求項1乃至9の何れか一項に記載の半導体装置。
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