JP2018148211A - 半導体装置、及び半導体装置の作製方法 - Google Patents
半導体装置、及び半導体装置の作製方法 Download PDFInfo
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- JP2018148211A JP2018148211A JP2018036724A JP2018036724A JP2018148211A JP 2018148211 A JP2018148211 A JP 2018148211A JP 2018036724 A JP2018036724 A JP 2018036724A JP 2018036724 A JP2018036724 A JP 2018036724A JP 2018148211 A JP2018148211 A JP 2018148211A
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- metal oxide
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Classifications
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- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
Abstract
Description
本実施の形態では、本発明の一態様の半導体装置と、その作製方法について説明する。ここでは半導体装置の一態様であるトランジスタについて説明する。
本発明の一態様の半導体装置であるトランジスタ100Aの上面図を図1(A)、断面図を図1(B)及び図1(C)に示す。図1(B)は、図1(A)に示す一点鎖線X1−X2における切断図の断面図に相当し、図1(C)は、図1(A)に示す一点鎖線Y1−Y2における切断図の断面図に相当する。なお、図1(A)において、煩雑になることを避けるため、トランジスタ100Aの構成要素の一部(ゲート絶縁層等)を省略して図示している。また、一点鎖線X1−X2方向をチャネル長方向、一点鎖線Y1−Y2方向をチャネル幅方向と呼称する場合がある。また、トランジスタの上面図においては、以降の図面においても図1(A)と同様に、構成要素の一部を省略して図示する場合がある。
本発明の一態様の半導体装置であるトランジスタ100Bの上面図を図4(A)、断面図を図4(B)及び図4(C)に示す。図4(B)は、図4(A)に示す一点鎖線X1−X2における切断図の断面図に相当し、図4(C)は、図4(A)に示す一点鎖線Y1−Y2における切断図の断面図に相当する。
本発明の一態様の半導体装置であるトランジスタ100Cの上面図を図5(A)、断面図を図5(B)及び図5(C)に示す。図5(B)は、図5(A)に示す一点鎖線X1−X2における切断図の断面図に相当し、図5(C)は、図5(A)に示す一点鎖線Y1−Y2における切断図の断面図に相当する。
本発明の一態様の半導体装置であるトランジスタ100Dの上面図を図6(A)、断面図を図6(B)及び図6(C)に示す。図6(B)は、図6(A)に示す一点鎖線X1−X2における切断図の断面図に相当し、図6(C)は、図6(A)に示す一点鎖線Y1−Y2における切断図の断面図に相当する。
本発明の一態様の半導体装置であるトランジスタ100Gの上面図を図9(A)、断面図を図9(B)及び図9(C)に示す。図9(B)は、図9(A)に示す一点鎖線X1−X2における切断図の断面図に相当し、図9(C)は、図9(A)に示す一点鎖線Y1−Y2における切断図の断面図に相当する。
以下では、本実施の形態の半導体装置に含まれる構成要素について、詳細に説明する。
基板102の材質などに大きな制限はないが、少なくとも、後の加熱処理に耐えうる程度の耐熱性を有している必要がある。例えば、ガラス基板、セラミック基板、石英基板、サファイア基板等を、基板102として用いてもよい。また、シリコンや炭化シリコンを材料とした単結晶半導体基板、多結晶半導体基板、シリコンゲルマニウム等の化合物半導体基板、SOI基板等を適用することも可能であり、これらの基板上に半導体素子が設けられたものを、基板102として用いてもよい。なお、基板102として、ガラス基板を用いる場合、第6世代(1500mm×1850mm)、第7世代(1870mm×2200mm)、第8世代(2200mm×2400mm)、第9世代(2400mm×2800mm)、第10世代(2950mm×3400mm)等の大面積基板を用いることで、大型の表示装置を作製することができる。
導電層104、導電層112a、導電層112b、導電層120a、導電層120bとしては、クロム、銅、アルミニウム、金、銀、亜鉛、モリブデン、タンタル、チタン、タングステン、マンガン、ニッケル、鉄、コバルトから選ばれた金属元素、または前述した金属元素を成分とする合金か、前述した金属元素を組み合わせた合金等を用いてそれぞれ形成することができる。
ゲート絶縁層として機能する絶縁層106には、プラズマ化学気相堆積(PECVD:Plasma Enhanced Chemical Vapor Deposition)法、スパッタリング法等により形成された、窒化酸化シリコン膜、窒化シリコン膜、窒化アルミニウム膜、窒化酸化アルミニウム膜等を一種以上含む絶縁層を用いることができる。なお、絶縁層106を2層以上の積層構造としてもよい。
第1の金属酸化物層108a、第2の金属酸化物層108b及び第3の金属酸化物層108cとしては、先に示す材料を用いることができる。
以下では、本発明の一態様のトランジスタの作製方法例について説明する。ここでは、前述構成例3で例示したトランジスタ100Cを例に挙げて説明する。
基板102上に導電膜を形成し、当該導電膜をリソグラフィ工程及びエッチング工程を行い加工して、ゲート電極として機能する導電層104を形成する。
導電層104及び基板102を覆う絶縁層106を形成する(図10(A))。絶縁層106は、例えばPECVD法等を用いて形成することができる。
続いて、絶縁層106に対して酸素130aを添加し、表面近傍に、酸素を含む領域106aを形成すると好適である(図10(B))。
続いて、絶縁層106上に金属酸化物膜128a及び金属酸化物膜128bを形成する(図10(C))。
続いて、後に導電層121a及び導電層121bとなる導電膜121と、後に導電層122a及び導電層122bとなる導電膜122を積層して形成する。
続いて、導電層112a、導電層112b、及び金属酸化物層108等を覆うように、絶縁層114及び絶縁層116を形成する。
以下では、トランジスタの作製方法1に示した作製方法と異なる、トランジスタ100Cの作製方法について説明する。なお、導電層112a及び導電層112bの形成までは、前述のトランジスタの作製方法1と同じである(図12(B)参照)。
次に、導電層112a、導電層112b、及び金属酸化物層108等を覆うように、絶縁層114を形成する(図13(A))。絶縁層114の形成方法については、トランジスタの作製方法1の記載を参照できるため、詳細な記載は省略する。なお、絶縁層114は、絶縁層114a及び絶縁層114bの2層構造としてもよい。本発明の一態様はこれに限定されず、例えば、絶縁層114a又は絶縁層114bのどちらか一方の単層構造としてもよい。絶縁層114を単層構造とすることで、生産性を高めることができ好ましい。また、絶縁層114を3層以上の積層構造としてもよい。
絶縁層114を形成した後に、加熱処理を行う。絶縁層114形成後に加熱処理を行うことにより、絶縁層114に含まれる窒素酸化物を低減することができる。また、加熱処理により、絶縁層114に含まれる酸素の一部を金属酸化物層108に移動させ、金属酸化物層108に含まれる酸素欠損及びVoHを低減することができる。
次に、絶縁層114を覆うように、絶縁層116を形成する。絶縁層116の形成方法については、トランジスタの作製方法1の記載を参照できるため、詳細な記載は省略する。
以下では、トランジスタの作製方法1に示した作製方法と異なる、トランジスタ100Cの作製方法について説明する。なお、導電層112a及び導電層112bの形成までは、前述のトランジスタの作製方法1と同じである(図12(B)参照)。
次に、導電層112a、導電層112b、及び金属酸化物層108等を覆うように、絶縁層114a及び絶縁層114bを形成する(図13(A))。絶縁層114a及び絶縁層114bの形成方法については、トランジスタの作製方法1の記載を参照できるため、詳細な記載は省略する。
次に、絶縁層114を覆うように、絶縁層116を形成する。
以下では、トランジスタの作製方法1及びトランジスタの作製方法3に示した作製方法と異なる、トランジスタ100Cの作製方法について説明する。なお、導電層112a及び導電層112bの形成までは、前述のトランジスタの作製方法1と同じである(図12(B)参照)。
次に、導電層112a、導電層112b、及び金属酸化物層108等を覆うように、絶縁層114a及び絶縁層114bを形成する(図13(A))。絶縁層114a及び絶縁層114bの形成方法については、トランジスタの作製方法1の記載を参照できるため、詳細な記載は省略する。
次に、絶縁層114bを覆って導電膜134を形成する(図14(A))。
次に、絶縁層114を覆うように、絶縁層116を形成する。絶縁層116の形成方法については、トランジスタの作製方法1の記載を参照できるため、詳細な記載は省略する。
本実施の形態においては、先の実施の形態で例示したトランジスタを有する表示装置の一例について説明を行う。
図15(A)は、表示装置の一例を示す上面図である。図15(A)に示す表示装置700は、第1の基板701上に設けられた画素部702と、第1の基板701に設けられたソースドライバ回路部704及びゲートドライバ回路部706と、画素部702、ソースドライバ回路部704、及びゲートドライバ回路部706を囲むように配置されるシール材712と、第1の基板701に対向するように設けられる第2の基板705と、を有する。なお、第1の基板701と第2の基板705は、シール材712によって封止されている。すなわち、画素部702、ソースドライバ回路部704、及びゲートドライバ回路部706は、第1の基板701とシール材712と第2の基板705によって封止されている。なお、図15(A)には図示しないが、第1の基板701と第2の基板705の間には表示素子が設けられる。
以下では、表示素子として液晶素子及びEL素子を用いる構成について、図16乃至図18を用いて説明する。なお、図16及び図17は、図15(A)に示す一点鎖線Q−Rにおける断面図であり、表示素子として液晶素子を用いた構成である。また、図18は、図15に示す一点鎖線Q−Rにおける断面図であり、表示素子としてEL素子を用いた構成である。
図16乃至図18に示す表示装置700は、引き回し配線部711と、画素部702と、ソースドライバ回路部704と、FPC端子部708と、を有する。また、引き回し配線部711は、信号線710を有する。また、画素部702は、トランジスタ750及び容量素子790を有する。また、ソースドライバ回路部704は、トランジスタ752を有する。
図16に示す表示装置700は、液晶素子775を有する。液晶素子775は、導電膜772、導電膜774、及び液晶層776を有する。導電膜774は、第2の基板705側に設けられ、対向電極としての機能を有する。図16に示す表示装置700は、導電膜772と導電膜774に印加される電圧によって、液晶層776の配向状態が変わることによって光の透過、非透過が制御され画像を表示することができる。
図18に示す表示装置700は、発光素子782を有する。発光素子782は、導電膜772、EL層786、及び導電膜788を有する。図18に示す表示装置700は、画素毎に設けられる発光素子782が有するEL層786が発光することによって、画像を表示することができる。なお、EL層786は、有機化合物、または量子ドットなどの無機化合物を有する。
また、図16乃至図18に示す表示装置700に入出力装置を設けてもよい。当該入出力装置としては、例えば、タッチパネル等が挙げられる。
本実施の形態では、本発明の一態様の半導体装置を有する表示装置について、図21を用いて説明を行う。
図21(A)に示す表示装置は、表示素子の画素を有する領域(以下、画素部502という)と、画素部502の外側に配置され、画素を駆動するための回路を有する回路部(以下、駆動回路部504という)と、素子の保護機能を有する回路(以下、保護回路506という)と、端子部507と、を有する。なお、保護回路506は、設けない構成としてもよい。
本実施の形態では、本発明の一態様の電子機器について、図面を参照して説明する。
本実施の形態では、本発明の一態様の表示装置を適用することのできるテレビジョン装置の例について、図面を参照して説明する。
まず、本実施例で作製した各試料について、説明する。
次に、試料A1、試料A2及び試料A3のX線光電子分光法(XPS)を行った。
次に、試料A1乃至試料A3を集束イオンビーム(FIB:Focused Ion Beam)により薄片化し、試料の断面をTEMで観察した。TEM観察には、日立ハイテクノロジーズ社製透過電子顕微鏡H−9500を用い、加速電圧は300kVとした。
まず、本実施例で作製した各試料について、説明する。
次に、試料B1乃至試料B29と、試料C1乃至試料C25のX線回折(XRD)測定を行った。XRDを行ったガラス基板の座標を図28に示す。図28は、600mm×720mmサイズのガラス基板のXRDを行った場所を表す座標である。XRDを行った座標としては、図28に白抜き丸印で示すB、E、Hに対応する位置とした。
まず、基板102上に導電層104を形成した。基板102としては、ガラス基板を用いた。また、厚さ100nmのタングステン膜を、スパッタリング装置を用いて成膜し、これを加工して導電層104を形成した。
試料D2は、先に示す試料D1と金属酸化物層108の成膜条件が異なる。それ以外の工程については、試料D1と同様とした。
試料D3は、先に示す試料D1と金属酸化物層108の成膜条件が異なる。それ以外の工程については、試料D1と同様とした。
試料D4は、先に示す試料D1と金属酸化物層108の成膜条件が異なる。それ以外の工程については、試料D1と同様とした。
次に、上記作製した試料について、トランジスタのId−Vg特性を測定した。なお、トランジスタのId−Vg特性の測定条件としては、ゲート電圧(Vg)を、−15Vから+20Vまで0.25Vのステップで印加した。また、ソース電圧(Vs)を0Vとし、ドレイン電圧(Vd)を、0.1V及び15Vとした。また、測定数は、各試料それぞれ10とした。
100B トランジスタ
100C トランジスタ
100D トランジスタ
100E トランジスタ
100F トランジスタ
100G トランジスタ
102 基板
104 導電層
106 絶縁層
106a 領域
108 金属酸化物層
108a 金属酸化物層
108b 金属酸化物層
108c 金属酸化物層
112a 導電層
112b 導電層
112c 導電層
114 絶縁層
114a 絶縁層
114b 絶縁層
116 絶縁層
120a 導電層
120b 導電層
121 導電膜
121a 導電層
121b 導電層
121c 導電層
122 導電膜
122a 導電層
122b 導電層
122c 導電層
123 導電膜
123a 導電層
123b 導電層
123c 導電層
128a 金属酸化物膜
128b 金属酸化物膜
130a 酸素
130b 酸素
130c 酸素
131 レジストマスク
132 レジストマスク
134 導電膜
142a 接続部
142b 接続部
150 絶縁層
152a 接続部
152b 接続部
180 空隙部
501 画素回路
502 画素部
504 駆動回路部
504a ゲートドライバ
504b ソースドライバ
506 保護回路
507 端子部
550 トランジスタ
552 トランジスタ
554 トランジスタ
560 容量素子
562 容量素子
570 液晶素子
572 発光素子
600 テレビジョン装置
601 制御部
602 記憶部
603 通信制御部
604 画像処理回路
605 デコーダ回路
606 映像信号受信部
607 タイミングコントローラ
608 ソースドライバ
609 ゲートドライバ
610 ニューラルネットワーク
611 入力層
612 中間層
613 出力層
615 ニューロン
620 表示パネル
621 画素
630 システムバス
664 電極
665 電極
667 電極
700 表示装置
700A 表示装置
701 基板
702 画素部
704 ソースドライバ回路部
705 基板
706 ゲートドライバ回路部
708 FPC端子部
710 信号線
711 配線部
712 シール材
716 FPC
721 ソースドライバIC
722 ゲートドライバ回路
723 FPC
724 プリント基板
730 絶縁膜
732 封止膜
734 絶縁膜
736 着色膜
738 遮光膜
750 トランジスタ
752 トランジスタ
760 接続電極
770 平坦化絶縁膜
772 導電膜
773 絶縁膜
774 導電膜
775 液晶素子
776 液晶層
778 構造体
780 異方性導電膜
782 発光素子
786 EL層
788 導電膜
790 容量素子
791 タッチパネル
792 絶縁膜
793 電極
794 電極
795 絶縁膜
796 電極
797 絶縁膜
7000 表示部
7100 テレビジョン装置
7101 筐体
7103 スタンド
7111 リモコン操作機
7200 ノート型パーソナルコンピュータ
7211 筐体
7212 キーボード
7213 ポインティングデバイス
7214 外部接続ポート
7300 デジタルサイネージ
7301 筐体
7303 スピーカ
7311 情報端末機
7400 デジタルサイネージ
7401 柱
7411 情報端末機
Claims (11)
- ゲート電極と、
前記ゲート電極上の第1の絶縁層と、
前記第1の絶縁層上の金属酸化物層と、
前記金属酸化物層上の一対の電極と、
前記一対の電極上の第2の絶縁層と、を有し、
前記金属酸化物層は、
インジウムと、元素M(Mは、ガリウム、アルミニウム、シリコン、ホウ素、イットリウム、スズ、銅、バナジウム、ベリリウム、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステンまたはマグネシウムの一以上)と、亜鉛と、を有し、
前記第1の絶縁層は、第1の領域と、第2の領域と、を有し、
前記第1の領域は、前記金属酸化物層と接し、且つ前記第2の領域よりも酸素の含有量が多い領域を有し、
前記第2の領域は、前記第1の領域よりも窒素の含有量が多い領域を有し、
前記金属酸化物層は、
膜厚方向において、少なくとも酸素の濃度勾配を有し、
前記濃度勾配は、
前記第1の領域側と、前記第2の絶縁層側とで、高くなる、
ことを特徴とする半導体装置。 - 請求項1において、
前記第1の領域は、膜厚方向において、1nm以上10nm以下の領域を有する、
ことを特徴とする半導体装置。 - 請求項1又は請求項2において、
前記金属酸化物層は、
前記Inの原子数比が1の場合、前記Mの原子数比が0.5以上1.5以下であり、且つ前記Znの原子数比が0.1以上2以下である、
ことを特徴とする半導体装置。 - 請求項1又は請求項2において、
前記金属酸化物層は、
前記Inの原子数比が4の場合、前記Mの原子数比が1.5以上2.5以下であり、且つ前記Znの原子数比が2以上4以下である、
ことを特徴とする半導体装置。 - 請求項1又は請求項2において、
前記金属酸化物層は、
前記Inの原子数比が5の場合、前記Mの原子数比が0.5以上1.5以下であり、且つ前記Znの原子数比が5以上7以下である、
ことを特徴とする半導体装置。 - 請求項1乃至請求項5のいずれか一において、
前記金属酸化物層は、第1の金属酸化物層と、
前記第1の金属酸化物層上の第2の金属酸化物層と、を有し、
前記第1の金属酸化物層は、前記第2の金属酸化物層よりも結晶性が低い領域を有する、
ことを特徴とする半導体装置。 - 請求項1乃至請求項5のいずれか一において、
前記金属酸化物層は、第1の金属酸化物層と、
前記第1の金属酸化物層上の第2の金属酸化物層と、
前記第1の金属酸化物層の下側に接する第3の金属酸化物層と、を有し、
前記第1の金属酸化物層は、前記第2の金属酸化物層及び前記第3の金属酸化物層のいずれか一方または双方よりも結晶性が低い領域を有する、
ことを特徴とする半導体装置。 - 請求項1乃至請求項7のいずれか一において、
前記第2の絶縁層上に、さらに第3の絶縁層を有し、
前記第3の絶縁層は、シリコンと、窒素とを含む、
ことを特徴とする半導体装置。 - 請求項1乃至請求項7のいずれか一において、
前記第2の絶縁層上に、さらに第3の絶縁層を有し、
前記第3の絶縁層は、元素X(Xは、アルミニウム、インジウム、ガリウム又は亜鉛の一以上)と、酸素と、を含む、
ことを特徴とする半導体装置。 - ゲート電極を形成する工程と、
前記ゲート電極上に、第1の絶縁層を形成する工程と、
前記第1の絶縁層の表面近傍に、酸素を添加する工程と、
前記第1の絶縁層上に、金属酸化物層を形成する工程と、
前記金属酸化物層上に、一対の電極を形成する工程と、
前記一対の電極上に、第2の絶縁層を形成する工程と、を有し、
前記金属酸化物層を形成する工程において、
前記金属酸化物層は、第1の工程及び第2の工程に分けて、真空中で連続して成膜され、
前記第1の工程は、前記第2の工程の前に行われ、
前記第2の工程は、前記第1の工程よりも成膜ガス全体に占める酸素流量比が高い、
ことを特徴とする半導体装置の作製方法。 - ゲート電極を形成する工程と、
前記ゲート電極上に、第1の絶縁層を形成する工程と、
前記第1の絶縁層の表面近傍に、酸素を添加する工程と、
前記第1の絶縁層上に、金属酸化物層を形成する工程と、
前記金属酸化物層上に、一対の電極を形成する工程と、
前記一対の電極上に、第2の絶縁層を形成する工程と、を有し、
前記金属酸化物層を形成する工程において、
前記金属酸化物層は、第1の工程乃至第3の工程に分けて、真空中で連続して成膜され、
前記第1の工程は、前記第2の工程の前に行われ、
前記第2の工程は、前記第1の工程よりも成膜ガス全体に占める酸素流量比が高く、
前記第3の工程は、前記第1の工程の前に行われ、且つ、前記第1の工程よりも成膜ガス全体に占める酸素流量比が高い、
ことを特徴とする半導体装置の作製方法。
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