JP2018098788A5 - - Google Patents

Download PDF

Info

Publication number
JP2018098788A5
JP2018098788A5 JP2017234085A JP2017234085A JP2018098788A5 JP 2018098788 A5 JP2018098788 A5 JP 2018098788A5 JP 2017234085 A JP2017234085 A JP 2017234085A JP 2017234085 A JP2017234085 A JP 2017234085A JP 2018098788 A5 JP2018098788 A5 JP 2018098788A5
Authority
JP
Japan
Prior art keywords
calibration
gain
lsb
signal
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2017234085A
Other languages
English (en)
Japanese (ja)
Other versions
JP6894360B2 (ja
JP2018098788A (ja
Filing date
Publication date
Priority claimed from EP16202934.2A external-priority patent/EP3334047B1/en
Application filed filed Critical
Publication of JP2018098788A publication Critical patent/JP2018098788A/ja
Publication of JP2018098788A5 publication Critical patent/JP2018098788A5/ja
Application granted granted Critical
Publication of JP6894360B2 publication Critical patent/JP6894360B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2017234085A 2016-12-08 2017-12-06 逐次比較レジスタ型ad変換器における利得較正方法、及び逐次比較レジスタ型アナログデジタル変換器 Active JP6894360B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP16202934.2A EP3334047B1 (en) 2016-12-08 2016-12-08 A method of gain calibration in a two-stage pipelined successive approximation register analog-to-digital converter and a two-stage pipelined successive approximation register analog-to-digital converter
EP16202934.2 2016-12-08

Publications (3)

Publication Number Publication Date
JP2018098788A JP2018098788A (ja) 2018-06-21
JP2018098788A5 true JP2018098788A5 (enExample) 2021-02-25
JP6894360B2 JP6894360B2 (ja) 2021-06-30

Family

ID=57530578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017234085A Active JP6894360B2 (ja) 2016-12-08 2017-12-06 逐次比較レジスタ型ad変換器における利得較正方法、及び逐次比較レジスタ型アナログデジタル変換器

Country Status (3)

Country Link
US (1) US10050638B2 (enExample)
EP (1) EP3334047B1 (enExample)
JP (1) JP6894360B2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10425094B2 (en) * 2017-12-01 2019-09-24 Intel Corporation Method and apparatus for preventing inherent error propagation of successive approximation register analog-to-digital converter through digital correction
US10686463B1 (en) * 2019-02-14 2020-06-16 United States Of America As Represented By The Secretary Of The Air Force Method for calibration of digital readout with split counter and residual bits
CN110768671B (zh) * 2019-10-17 2022-04-22 西安交通大学 一种用于逐次逼近型模数转换器的片外校准方法及系统
CN112600557B (zh) * 2020-12-16 2023-08-01 东南大学 一种流水线adc数字域增益校准方法
CN113114247B (zh) * 2021-04-19 2022-05-24 电子科技大学 基于比较时间探测器的流水线adc级间增益校准方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5272481A (en) * 1991-07-02 1993-12-21 David Sarnoff Research Center, Inc. Successive approximation analog to digital converter employing plural feedback digital to analog converters
US7221299B2 (en) * 2004-06-12 2007-05-22 Nordic Semiconductor Asa Method and apparatus for an ADC circuit with wider input signal swing
US7378999B1 (en) * 2007-03-06 2008-05-27 Xilinx, Inc. Method and apparatus for digital calibration of an analog-to-digital converter
US8269657B2 (en) * 2009-06-26 2012-09-18 Intersil Americas Inc. Background calibration of offsets in interleaved analog to digital converters
US8040264B2 (en) * 2010-03-04 2011-10-18 Analog Devices, Inc. Pipeline analog to digital converter and a residue amplifier for a pipeline analog to digital converter
TWI545903B (zh) * 2011-03-17 2016-08-11 安娜卡敦設計公司 類比轉數位轉換器(adc)之校正
US9059730B2 (en) * 2013-09-19 2015-06-16 Qualcomm Incorporated Pipelined successive approximation analog-to-digital converter
EP2953265B1 (en) * 2014-06-06 2016-12-14 IMEC vzw Method and circuit for bandwidth mismatch estimation in an a/d converter
US9219492B1 (en) * 2014-09-19 2015-12-22 Hong Kong Applied Science & Technology Research Institute Company, Limited Loading-free multi-stage SAR-assisted pipeline ADC that eliminates amplifier load by re-using second-stage switched capacitors as amplifier feedback capacitor
EP3059867B1 (en) * 2015-02-19 2020-07-08 Stichting IMEC Nederland Circuit and method for dac mismatch error detection and correction in an adc
JP2017005332A (ja) * 2015-06-05 2017-01-05 日本放送協会 巡回型ad変換器、並びに巡回型ad変換器用のデジタル補正器及びその方法
US9584150B2 (en) * 2015-07-07 2017-02-28 Infineon Technologies Ag Gain calibration for ADC with external reference
US9654132B2 (en) * 2015-07-08 2017-05-16 Marvell World Trade Ltd. Hybrid charge-sharing charge-redistribution DAC for successive approximation analog-to-digital converters
US9432044B1 (en) * 2015-12-18 2016-08-30 Texas Instruments Incorporated Mismatch correction of attenuation capacitor in a successive approximation register analog to digital converter
US9602119B1 (en) * 2016-02-09 2017-03-21 Applied Micro Circuits Corporation Gain calibration by applying a portion of an input voltage to voltage associated with a capacitor array

Similar Documents

Publication Publication Date Title
JP2018098790A5 (enExample)
JP2018098788A5 (enExample)
JP4890561B2 (ja) 補正dacを含むデジタル補正sar変換器
US7612703B2 (en) Pipelined analog-to-digital converter with calibration of capacitor mismatch and finite gain error
JP6886394B2 (ja) 逐次比較レジスタ型アナログデジタル変換器におけるデジタルアナログ変換器のミスマッチ較正方法、及び逐次比較レジスタ型アナログデジタル変換器
US9438260B1 (en) Semiconductor apparatus and calibration method for analog to digital converter
JP4532808B2 (ja) A/dコンバータの較正
JP5826944B2 (ja) パイプライン式アナログデジタル変換器における中間ステージ利得誤差および非線形性を減少させるための相関に基づくバックグラウンド較正
US9397679B1 (en) Circuit and method for DAC mismatch error detection and correction in an ADC
US9059730B2 (en) Pipelined successive approximation analog-to-digital converter
KR101666575B1 (ko) Sar 방식의 adc에서 커패시터 어레이 정합장치 및 방법
KR920001859A (ko) 다단계 파이프라인 서브레인징 아날로그-대-디지탈 변환기용 디지탈 에러보정 시스템
TWI556585B (zh) 類比至數位轉換裝置及相關的校正方法及校正模組
CN118659783B (zh) 一种应用于流水线逐次逼近型adc的校准方法及电路
JP6894360B2 (ja) 逐次比較レジスタ型ad変換器における利得較正方法、及び逐次比較レジスタ型アナログデジタル変換器
CN113114247A (zh) 基于比较时间探测器的流水线adc级间增益校准方法
JP7115841B2 (ja) 逐次比較レジスタ型ad変換器におけるオフセット較正方法、及び逐次比較レジスタ型アナログデジタル変換器
US7187317B2 (en) A/D conversion apparatus
US10763886B1 (en) Dithering and calibration technique in multi-stage ADC
KR101783745B1 (ko) 저해상도 adc를 이용한 고해상도 adc 구현 기법 및 장치
TWI568192B (zh) 類比至數位轉換裝置及相關的校正方法與校正模組
CN119582844B (zh) 一种基于平方与前后项关系的斐波那契电容阵列的校准方法及校准装置
JP2004112662A (ja) アナログ−デジタル変換回路
KR102837041B1 (ko) 비교기 오프셋 오류를 수정하는 고해상도 파이프라인 아날로그 디지털 변환기
TWI665875B (zh) 數位背景式校正電路