JP5826944B2 - パイプライン式アナログデジタル変換器における中間ステージ利得誤差および非線形性を減少させるための相関に基づくバックグラウンド較正 - Google Patents
パイプライン式アナログデジタル変換器における中間ステージ利得誤差および非線形性を減少させるための相関に基づくバックグラウンド較正 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
- H03M1/1057—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by trimming, i.e. by individually adjusting at least part of the quantisation value generators or stages to their nominal values
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
- H03M1/0673—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using random selection of the elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
- H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
- H03M1/167—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters
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Description
[関連出願の相互参照]
本出願は、米国特許法第119条(e)の下、2011年11月14日に出願された米国特許仮出願第61/559、388号に対する利点を主張するものであり、その内容は、参照によりその全体が本明細書に組み込まれる。
100 ステージ1
110 ステージ2
120 ステージN
150 システム
200 較正回路
210 ディザ導入回路
220 相関回路
230 補正回路
Claims (24)
- パイプライン式アナログデジタル変換器(ADC)を較正するための方法であって、
前記ADCにおける少なくとも1つのステージで、無作為に判定される量のディザをフラッシュ構成要素および複式デジタルアナログ変換器(MDAC)のうちの1つに導入することと、
少なくとも1つのステージの各々のステージについて、
前記ADCの出力に基づいて、前記ステージを伝播した後、前記導入されたディザにより経験される利得の量を推定するために、相関手順を実施することと、
そのそれぞれの利得推定値に基づいて前記ステージを較正することと、を含み、
前記ディザの振り幅が前記ADCの最大測定限界値の真分数であって、前記真分数の分母は奇数である、方法。 - 前記較正が前記利得推定値と理想的な利得値との間の偏差を補正する、請求項1に記載の方法。
- 前記ディザが所定の範囲の離散値から選択される、請求項1に記載の方法。
- 前記離散値の範囲が等間隔に離れる奇数の値を有する、請求項3に記載の方法。
- 前記ディザが因数Fにより前記ADCの最大測定限界値より小さく、前記離散値の数はFの関数として判定される、請求項4に記載の方法。
- 前記ディザを生成するコンデンサ一式に静電容量シャフリングスキームを適用することをさらに含む、請求項1に記載の方法。
- パイプラインで少なくとも1つのステージに続く少なくとも1つの追加のステージでサンプリングコンデンサ一式に静電容量シャフリングスキームを適用することをさらに含む、請求項1に記載の方法。
- 前記ディザが、パイプラインにおける全ての前記ステージ未満、および前記ADCの入力に最も近い少なくとも1つのステージに導入される、請求項1に記載の方法。
- 複数の利得推定値に基づき、前記ADCの利得伝達関数の近似値を生成することと、
前記利得伝達関数の近似値に基づき少なくとも1つのステージの各々のステージを較正することと、をさらに含む、請求項1に記載の方法。 - 前記近似値が区分的線形近似値である、請求項9に記載の方法。
- 前記近似値が多項式近似値である、請求項9に記載の方法。
- 前記少なくとも1つのステージから選択されるステージおよび前記少なくとも1つのステージの最早のステージに先行するステージで、少なくとも1つのMDACおよびフラッシュ構成要素に、追加の無作為に判定されるディザの量を、導入することと、前記追加のディザが所定の範囲の離散値から選択されることと、
最終のADC出力を形態化するとき前記追加のディザを考慮にいれることと、をさらに含む、請求項1に記載の方法。 - パイプライン式アナログデジタル変換器(ADC)を較正するためのデバイスであって、
無作為に判定されたディザの量を前記ADCにおける少なくとも1つのステージで1つのフラッシュ構成要素および複式デジタルアナログ変換器(MDAC)に導入する、導入配置と、
較正配置であって、少なくとも1つのステージの各々のステージで、
前記ADCの出力に基づき、ステージを伝播した後導入したディザにより経験される利得の量を推定するために、相関手順を実施して、そのそれぞれの利得の推定値に基づいてステージを較正する、較正配置と、を含み、
前記ディザの振り幅が前記ADCの最大測定限界値の真分数であって、前記真分数の分母は奇数である、デバイス。 - 前記較正が、前記利得の推定値と理想的な利得値との間の偏差を補正する、請求項13に記載のデバイス。
- 前記ディザが、所定の範囲の離散値から選択される、請求項13に記載のデバイス。
- 前記離散値の範囲が等間隔に離れる奇数の値を有する、請求項15に記載のデバイス。
- 前記ディザが因数Fにより前記ADCの最大測定限界値より小さく、前記離散値の数はFの関数として判定される、請求項16に記載のデバイス。
- 前記ディザを生成するコンデンサ一式に静電容量シャフリングスキームを適用する制御配置をさらに含む、請求項13に記載のデバイス。
- パイプラインで少なくとも1つのステージに続く少なくとも1つの追加のステージでサンプリングコンデンサ一式に静電容量シャフリングスキームを適用する制御配置をさらに含む、請求項13に記載のデバイス。
- 前記ディザが、パイプラインにおける全ての前記ステージ未満、および前記ADCの入力に最も近い少なくとも1つのステージに導入される、請求項13に記載のデバイス。
- 前記較正配置が、
複数の利得の推定値に基づき、前記ADCの利得伝達関数の近似値を生成し、
前記利得伝達関数の近似値に基づき少なくとも1つのステージの各々のステージを較正する、請求項13に記載のデバイス。 - 前記近似値が区分的線形近似値である、請求項21に記載のデバイス。
- 前記近似値が多項式近似値である、請求項21に記載のデバイス。
- 前記導入配置が、前記少なくとも1つのステージから選択されるステージおよび前記少なくとも1つのステージの最早のステージに先行するステージのうちの1つで、MDACおよびフラッシュ構成要素のうちの少なくとも1つに、追加の無作為に判定されるディザの量を導入し、
前記較正配置が、最終のADC出力を形成するとき前記追加のディザを考慮にいれる、請求項13に記載のデバイス。
Applications Claiming Priority (5)
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US201161559388P | 2011-11-14 | 2011-11-14 | |
US61/559,388 | 2011-11-14 | ||
US13/560,226 US8723707B2 (en) | 2011-11-14 | 2012-07-27 | Correlation-based background calibration for reducing inter-stage gain error and non-linearity in pipelined analog-to-digital converters |
US13/560,226 | 2012-07-27 | ||
PCT/US2012/054740 WO2013074192A1 (en) | 2011-11-14 | 2012-09-12 | Correlation-based background calibration for reducing inter-stage gain error and non-linearity in pipelined analog-to-digital converters |
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JP2014533469A JP2014533469A (ja) | 2014-12-11 |
JP5826944B2 true JP5826944B2 (ja) | 2015-12-02 |
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