JP2018006362A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 172
- 238000000034 method Methods 0.000 claims description 21
- 238000003825 pressing Methods 0.000 claims description 2
- 229920005989 resin Polymers 0.000 description 20
- 239000011347 resin Substances 0.000 description 20
- 239000000919 ceramic Substances 0.000 description 14
- 239000011521 glass Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000005496 eutectics Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- -1 eutectic Inorganic materials 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/6875—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68785—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Die Bonding (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】 下面が平坦であり、半導体素子を載置可能な上面、または半導体素子が載置された上面を備える基板を準備する工程と、基板が載置される平坦な支持面を備えた支持台と、支持面側に配置され上下方向に可動な複数の支持ピンと、を備えた作業台を準備する工程と、支持ピンの先端部に前記基板の下面を当接させて支持ピンを押し下げ、基板の下面を支持台の支持面に当接させる工程と、基板を、支持面の上に固定させた後に、基板に対して作業を行う工程と、を備える半導体装置の製造方法。
【選択図】図1A
Description
下面が平坦であり、半導体素子を載置可能な上面、または半導体素子が載置された上面を備える基板を準備する工程と、基板が載置される平坦な支持面を備えた支持台と、支持面側に配置され上下方向に可動な複数の支持ピンと、を備えた作業台を準備する工程と、支持ピンの先端部に前記基板の下面を当接させて支持ピンを押し下げ、基板の下面を支持台の支持面に当接させる工程と、基板を、支持面の上に固定させた後に、基板に対して作業を行う工程と、を備える半導体装置の製造方法。
下面が平坦であり、半導体素子を載置可能な上面、または半導体素子が載置された上面を備える基板を準備する工程と、
基板が載置される平坦な支持面を備えた支持台と、支持面側に配置され上下方向に可動な複数の支持ピンと、を備えた作業台を準備する工程と、
支持ピンの先端部に基板の下面を当接させて支持ピンを押し下げ、基板の下面を支持台の支持面に当接させる工程と、
基板を、支持面の上に固定させた後に、基板に対して作業を行う工程と、
を備える。
以下、各工程について詳説する。
図1Aは、基板10と、基板を載置する支持台21を備えた作業台20と、を準備した状態を示し、図1Bは図1Aの基板10及び作業台20の断面図を示す。
基板10として、上面10aと、上面10aと反対の下面10bと、を備えた板状の基板10を準備する。基板10は、複数の半導体装置を得るための部材であり、上面10aは半導体素子等の電子部品が載置される面、または半導体素子等の電子部品が載置された面であり、下面10bは2次基板の上面と対向配置される面である。更に、基板10は、最終的に個片化して半導体装置となる製品予定部10c(図1Aの薄墨部分)と、その周りに設けられる除去予定部10dと、を備える。
(1)セラミックと配線とを備えた基板
(2)セラミック基板にダイボンド樹脂が配置された基板
(3)セラミック基板にダイボンド樹脂を介して発光素子が載置された基板
(4)セラミック基板にダイボンド樹脂を介して発光素子が載置され、その発光素子にワイヤが接続された基板
(5)セラミック基板にダイボンド樹脂を介して発光素子が載置され、その発光素子にワイヤが接続され、発光素子とワイヤとを透光性樹脂で被覆した基板
作業台20は、基板が載置される支持面21aを備えた支持台21と、支持面21a側に配置された支持ピン22と、を備える。支持ピン22は、支持面21aに設けられた開口部21bの中に挿通されている。支持ピン22は、バネなどの弾性部材23の上に配置されており、弾性部材23は、ネジなどの固定部材24によって支持台21又は別部材に固定されている。
作業台20に基板10を載置する工程は、まず、図2に示すように、支持ピン22の先端部22aに基板10の下面10bを当接させる。これにより、基板10は複数の支持ピン22のみに指示された状態となる。この段階では、基板10の下面10bと支持台21の上面21aとは接しておらず、両者の間には空気が存在する。
上述のように作業台上に位置精度よく配置された基板10を、固定治具を用いて支持第21に固定する。更に、カメラ、センサ等を用いて、より精度の高い位置決め作業を行った後、各工程における作業を行う。
(1)セラミックと配線とを備えた基板に対して、ダイボンド樹脂を配置する工程
(2)セラミック基板に配置されたダイボンド樹脂を備えた基板に対して、ダイボンド樹脂上に発光素子を載置する工程
(3)セラミック基板にダイボンド樹脂を介して発光素子が載置された基板に対して、発光素子にワイヤを接続する工程
(4)セラミック基板にダイボンド樹脂を介して発光素子が載置され、その発光素子にワイヤが接続された基板に対して、発光素子とワイヤとを覆う透光性樹脂を形成する工程
(5)セラミック基板にダイボンド樹脂を介して発光素子が載置され、その発光素子にワイヤが接続され、発光素子とワイヤとを透光性樹脂で被覆した基板に対して、透光性樹脂を覆う薄膜を形成する工程
10a…上面
10b…下面
10c…製品予定部
10d…除去予定部
20…作業台
21…支持台
21a…支持面(上面)
21b…開口部
22…支持ピン
22a…先端部
23…弾性部材
24…固定部材
Claims (2)
- 下面が平坦であり、半導体素子を載置可能な上面、または半導体素子が載置された上面を備える基板を準備する工程と、
前記基板が載置される平坦な支持面を備えた支持台と、前記支持面側に配置され上下方向に可動な複数の支持ピンと、を備えた作業台を準備する工程と、
前記支持ピンの先端部に前記基板の下面を当接させて前記支持ピンを押し下げ、前記基板の下面を前記支持台の前記支持面に当接させる工程と、
前記基板を、前記支持面の上に固定させた後に、前記基板に対して作業を行う工程と、
を備えることを特徴とする半導体装置の製造方法。 - 前記支持ピンの先端部は、前記基板と接する前は、前記支持面よりも10μm〜30μm高い位置に配置される請求項1記載の半導体装置の製造方法。
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JP2016126244A JP6512182B2 (ja) | 2016-06-27 | 2016-06-27 | 半導体装置の製造方法 |
US15/632,513 US10263167B2 (en) | 2016-06-27 | 2017-06-26 | Method of manufacturing semiconductor device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11420431B2 (en) | 2019-11-27 | 2022-08-23 | Nichia Corporation | Adhering jig and adhering method |
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JPS6039248U (ja) * | 1983-08-26 | 1985-03-19 | 株式会社日立製作所 | 板状物の吸着チャック |
US6065381A (en) * | 1997-09-13 | 2000-05-23 | Samsung Electronics Co., Ltd. | Apparatus for cutting tie bars of semiconductor packages |
JPH11233291A (ja) * | 1998-02-17 | 1999-08-27 | Fron Tec:Kk | プラズマ処理装置 |
JP2000237983A (ja) * | 1999-02-22 | 2000-09-05 | Hitachi Electronics Eng Co Ltd | 基板チャック装置 |
JP2006049747A (ja) * | 2004-08-09 | 2006-02-16 | Seiko Epson Corp | 半導体基板処理装置及び半導体装置の製造方法 |
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JP2011176213A (ja) * | 2010-02-25 | 2011-09-08 | Shin Etsu Handotai Co Ltd | 気相成長用半導体基板支持サセプタおよびエピタキシャルウェーハ製造装置およびエピタキシャルウェーハの製造方法 |
WO2012014442A1 (ja) * | 2010-07-28 | 2012-02-02 | 株式会社アルバック | 基板搬送装置及び保持装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US11420431B2 (en) | 2019-11-27 | 2022-08-23 | Nichia Corporation | Adhering jig and adhering method |
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US10263167B2 (en) | 2019-04-16 |
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