JP2017188507A - Method for manufacturing silicon epitaxial wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for growing a silicon epitaxial layer on a main surface of a monocrystalline silicon substrate low in resistivity in a vapor phase, by which a silicon epitaxial wafer reduced in lamination defects can be obtained.SOLUTION: A sequence for vapor phase growth of a silicon epitaxial layer comprises the steps of: preparing a monocrystalline silicon substrate of which the resistivity is regulated to be 1.4 mΩ or less by doping of red phosphorus; etching, by a hydrogen chloride gas, a surface of the monocrystalline silicon substrate in a vapor phase for the purpose of surface property modification of the monocrystalline silicon substrate, in which the rate of etching the substrate by the hydrogen chloride gas is controlled to be 0.04-0.37 μm/min, and the etching amount is controlled to be 0.025-1.000 μm; and forming the silicon epitaxial layer on the resultant main surface of the monocrystalline silicon substrate by vapor phase growth after the etching in the gaseous phase.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a low resistance silicon epitaxial wafer.

  An epitaxial wafer is used for a semiconductor device used for a mobile terminal or the like. In order to save power in mobile terminals, such wafers require low-resistivity epitaxial wafers in which an epitaxial layer is vapor-grown on a low-resistivity silicon single crystal substrate doped with a high concentration of dopant. The The silicon single crystal substrate that is the basis of this epitaxial wafer is fabricated from an ingot that is pulled up by doping with a high concentration of dopant, but the doped dopant evaporates during the pulling. Therefore, if the silicon single crystal substrate on which the epitaxial layer is vapor-grown is n-type, a silicon single crystal substrate doped with red phosphorus (phosphorus) having a relatively low volatility as a dopant is used. Then, by epitaxially growing an epitaxial layer on the main surface of such a silicon single crystal substrate, a low resistance epitaxial wafer is manufactured.

  However, when an epitaxial layer is vapor-phase grown on a low resistivity silicon single crystal substrate doped with red phosphorus at a high concentration, many stacking faults (stacking faults) are generated on the main surface of the epitaxial wafer after vapor phase growth. (For example, refer to Patent Document 1). When a semiconductor element is manufactured using an epitaxial wafer in which this stacking fault has occurred, the characteristics of the semiconductor element (device) are degraded. Therefore, it is necessary to reduce the number of stacking faults to a level that does not affect the device characteristics.

  The stacking faults observed on the main surface of the epitaxial wafer are observed as crystal defects generated on the low resistivity silicon single crystal substrate propagate to the main surface of the epitaxial wafer. Therefore, it is considered that the state of the substrate surface in the low resistivity silicon single crystal substrate affects the occurrence of stacking faults.

  Therefore, before vapor-depositing an epitaxial layer on a low resistivity silicon single crystal substrate, the main surface of the silicon single crystal substrate is vapor-phase etched with hydrogen chloride gas to clean the substrate surface, thereby causing stacking faults. Control measures are taken.

  Here, as a conventional technique, Patent Document 2 describes that an epitaxial layer is vapor-phase grown after etching a surface of a silicon wafer in which phosphorus is embedded at a high concentration with hydrogen chloride gas.

JP 2014-11293 A Japanese Patent Laid-Open No. 4-72718

  However, even if vapor phase growth is performed on a low resistivity silicon single crystal substrate that has been subjected to such vapor phase etching, stacking defects having a concentration that adversely affects the characteristics of semiconductor elements still occur in the epitaxial wafer.

  The present invention has been made in view of the above circumstances, and in a method for vapor-phase growth of a silicon epitaxial layer on the main surface of a low resistivity silicon single crystal substrate, a method capable of obtaining a silicon epitaxial wafer with a reduced number of stacking faults. The issue is to provide.

  In order to solve the above-mentioned problems, the present invention provides a method for vapor-depositing a silicon epitaxial layer on a main surface of a silicon single crystal substrate having a resistivity of 1.4 mΩcm or less. The main surface of the crystal substrate is subjected to vapor phase etching with hydrogen chloride gas at an etching rate of 0.04 μm / min or more and 0.37 μm / min or less.

  The main surface of the silicon single crystal substrate can be cleaned by this vapor phase etching. That is, crystal defects or the like (hereinafter referred to as stacking fault nuclei) that are the starting points for generating stacking faults in the epitaxial wafer can be removed from the main surface of the silicon single crystal substrate. Furthermore, a silicon epitaxial wafer with a reduced number of stacking faults can be manufactured by limiting the etching rate in the vapor phase etching to the above conditions.

In the present invention, the silicon single crystal substrate is doped with red phosphorus at 5 × 10 ¹⁹ atoms / cm ³ or more. As a result, the resistivity of the silicon single crystal substrate can be made 1.4 mΩcm or less.

  In addition, the etching amount in vapor phase etching is preferably 0.025 μm or more and 1.000 μm or less. The inventor has confirmed that the number of stacking faults can be suppressed when the etching amount is 0.025 μm or more. In view of productivity, the etching amount is preferably 1.000 μm or less.

6 is a graph showing the relationship between the etching rate and the number of stacking faults (pieces / cm ² ) generated on an epitaxial wafer when the etching amount with hydrogen chloride gas is fixed at 0.5 μm. It is a graph which shows the relationship between the etching amount when the etching rate by hydrogen chloride gas is fixed to 0.090 μm / min, and the number of stacking faults (pieces / cm ² ) generated in the epitaxial wafer.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, a schematic configuration of a single wafer type vapor phase growth apparatus will be described as an example of a silicon epitaxial wafer manufacturing apparatus.

  A single wafer type vapor phase growth apparatus is an apparatus in which substrates are loaded one by one and an epitaxial layer is formed by vapor phase growth on the main surface of the loaded single substrate. Specifically, the vapor phase growth apparatus is disposed so as to surround a reaction furnace in which a substrate to be processed is loaded, a susceptor that is disposed in the reaction furnace and horizontally supports the loaded substrate, and the reaction furnace. A heater for heating the inside of the reaction furnace and a temperature measuring unit for measuring the temperature of the substrate disposed in the reaction furnace are configured. The susceptor is provided so as to be rotatable about its central axis, and the susceptor rotates during vapor phase growth.

  A gas supply port for supplying various gases onto the surface of the substrate in the reaction furnace is formed on one end side of the reaction furnace. The gas supplied from the gas supply port is silicon source gas, carrier gas (for example, hydrogen gas), dopant gas for adjusting the conductivity type and conductivity of the epitaxial layer, and the like. A gas discharge port for discharging the gas that has passed over the surface of the substrate is formed on the opposite side of the reaction furnace from the gas supply port. The heater can be, for example, a halogen lamp provided above and below the reactor. The temperature measurement unit can be, for example, a pyrometer (radiation thermometer) that measures the surface temperature of the substrate without contacting the substrate.

Next, a method for manufacturing a silicon epitaxial wafer will be described. First, a silicon single crystal substrate serving as a growth substrate on which an epitaxial layer is vapor-phase grown is manufactured. For example, a silicon single crystal ingot is produced by immersing and pulling up a seed crystal silicon rod on the surface of a melt obtained by adding polycrystalline silicon and red phosphorus for adjusting resistivity in a quartz crucible and melting it. Next, the produced silicon single crystal ingot is cut out to a predetermined thickness, and a silicon single crystal substrate obtained by subjecting the cut wafer to rough polishing, etching, polishing and the like is produced. This silicon single crystal substrate is adjusted to have a resistivity of, for example, 1.4 mΩ · cm or less by red phosphorus added as a dopant when the silicon single crystal ingot is manufactured. When the red phosphorus concentration in the silicon single crystal substrate is 5 × 10 ¹⁹ atoms / cm ³ , the resistivity of the silicon single crystal substrate is 1.4 mΩ · cm. That is, the resistivity of the silicon single crystal substrate can be made 1.4 mΩ · cm or less by adjusting the red phosphorus concentration in the silicon single crystal substrate to 5 × 10 ¹⁹ atoms / cm ³ or more. In order to obtain a silicon single crystal substrate having a lower resistivity, for example, the amount of red phosphorus added may be adjusted so that the resistivity is 0.85 mΩcm or less. Note that the silicon single crystal ingot that is the basis of the silicon single crystal substrate is not limited to the CZ method, and may be obtained by other methods such as the FZ method.

  Next, the produced silicon single crystal substrate is put into a reaction furnace of a vapor phase growth apparatus and placed on a susceptor. At this time, hydrogen gas is supplied as atmospheric gas in the reactor.

  Next, the temperature of the silicon single crystal substrate is heated by the heater so that the temperature of the silicon single crystal substrate is increased at a constant temperature increase rate, and is suitable for vapor phase etching of the silicon single crystal substrate (for example, 1050 ° C. to 1200 ° C.). Heat until. At this time, for example, the power of the heater is adjusted based on the measurement value of the temperature measurement unit provided in the vapor phase growth apparatus.

  When the temperature of the silicon single crystal substrate reaches a temperature suitable for vapor phase etching, an etching process for performing vapor phase etching on the main surface of the silicon single crystal substrate while maintaining the temperature of the silicon single crystal substrate. I do. In the etching step, hydrogen chloride gas (HCl gas) is supplied onto the main surface of the silicon single crystal substrate in the reaction furnace, and the main surface of the silicon single crystal substrate is vapor-phase etched with the hydrogen chloride gas. At this time, the vapor-phase etching rate (etching rate) is preferably set to 0.04 μm / min or more and 0.37 μm / min or less. By setting the etching rate to this condition, the number of stacking faults generated in the silicon epitaxial wafer can be reduced as shown in the following examples. The etching rate can be adjusted by the flow rate and concentration of hydrogen chloride gas. The concentration of the hydrogen chloride gas can be adjusted based on, for example, the flow rate of the hydrogen chloride gas and the flow rate of the dilution gas (for example, hydrogen gas) supplied into the reaction furnace together with the hydrogen chloride gas.

  In the vapor phase etching, the etching amount of the silicon single crystal substrate is set to 0.025 μm or more and 1.000 μm or less based on the direction from the main surface of the silicon single crystal substrate to the depth direction of the silicon single crystal substrate. It is preferable to set. By setting the etching amount to this condition, the number of stacking faults generated in the silicon epitaxial wafer can be reduced as shown in the following examples. The etching amount can be adjusted based on, for example, the supply time and flow rate of hydrogen chloride gas.

  When the etching process is completed, a purging process for discharging hydrogen chloride gas from the reaction furnace is performed. In this purge process, the supply of hydrogen chloride gas to the reaction furnace is stopped and hydrogen gas is supplied into the reaction furnace. At this time, the supply time of the hydrogen gas, that is, the purge time may be appropriately set so that the hydrogen chloride gas does not remain in the reaction furnace after the purge process, but can be set to, for example, 30 seconds or more. Further, the temperature in the reaction furnace (the temperature of the silicon single crystal substrate) may be maintained at the temperature in the previous vapor phase etching or may be different from the temperature in the vapor phase etching.

When the purge step is completed, the temperature of the silicon single crystal substrate is adjusted to a growth temperature (for example, 1050 ° C. to 1200 ° C.) for vapor phase growth of the epitaxial layer by adjusting the power of the heater. The main surface of the silicon single crystal substrate is a silicon source gas, for example, trichlorosilane (TCS), a hydrogen gas that is a carrier gas for diluting the trichlorosilane, and the resistivity and conductivity type of the epitaxial layer are adjusted. A dopant gas (for example, PH ₃ ) is supplied to grow a silicon epitaxial layer (silicon single crystal film) on the main surface of the silicon single crystal substrate. At this time, the vapor phase growth conditions (growth time, gas flow rate, etc.) may be appropriately set according to the conditions (film thickness, resistivity, etc.) of the epitaxial layer to be formed. The resistivity of the epitaxial layer may be set to 1.4 mΩcm or less like the resistivity of the silicon single crystal substrate, or may be set to a value greater than 1.4 mΩcm.

  Thereafter, after the temperature in the reaction furnace is lowered at a constant temperature drop rate, the manufactured silicon epitaxial wafer is taken out from the reaction furnace. From the above, a low resistance silicon epitaxial wafer is obtained.

  Thus, in this embodiment, since the main surface of the silicon single crystal substrate is subjected to gas phase etching with hydrogen chloride gas before vapor phase growth, stacking fault nuclei existing on the main surface can be removed. At this time, as the conditions for vapor phase etching, the etching rate is set to 0.04 μm / min or more and 0.37 μm / min or less, and the etching amount is set to 0.025 μm or more and 1.000 μm or less. As shown in the examples, the number of stacking faults generated in the silicon epitaxial wafer can be greatly reduced. Further, since the number of stacking faults can be reduced without performing any special process other than vapor phase etching, it is possible to suppress the complexity of the manufacturing process of the silicon epitaxial wafer.

  EXAMPLES Hereinafter, the present invention will be specifically described with reference to examples, but these do not limit the present invention.

Example 1
FIG. 1 shows the relationship between the etching rate of vapor-phase etching with hydrogen chloride gas and the stacking fault concentration on the main surface of the wafer when an epitaxial layer is vapor-grown on a low-resistance silicon single crystal substrate subjected to this vapor-phase etching. Is shown. The horizontal axis shows the etching rate of vapor phase etching with hydrogen chloride gas, and the vertical axis shows the number of stacking faults per unit area generated on the main surface of the epitaxial wafer measured by a particle counter (MAGICS manufactured by Lasertec Corporation). Show. The number of stacking faults on the vertical axis is a value converted to the number per unit area by obtaining the number of stacking faults per wafer and dividing the number of stacking faults by the surface area of the wafer.

In the experiment of FIG. 1, a silicon single crystal substrate having a red phosphorus concentration of 1.0 × 10 ²⁰ atoms / cm ³ , a resistivity of 0.75 mΩcm, and a diameter of 200 mm was used. In the experiment of FIG. 1, the etching amount in the gas phase etching is 0.5 μm, and purging is performed for 30 seconds for the purpose of discharging the hydrogen chloride gas from the chamber after the etching, and then the main surface of the silicon single crystal substrate A 4.0 [mu] m silicon epitaxial layer was vapor-phase grown thereon.

In FIG. 1, the number of stacking faults takes the minimum value at point A where the etching rate is 0.090 μm / min, and the number of stacking faults that reaches the minimum value is 4.9 pieces / cm ² . In the region where the etching rate is greater than 0.090 μm / min, the number of stacking faults increases almost in proportion to the increase in the etching rate. At point B where the etching rate was 0.371 μm / min, the number of stacking faults was 9.6 / cm ² , which is about twice that of point A (slightly less than twice). When the etching rate is greater than 0.371 μm / min, the number of stacking faults is greater than 9.6 / cm ² .

In the region where the etching rate is smaller than 0.090 μm / min, the number of stacking faults increases rapidly as the etching rate decreases, and when the etching rate is 0.015 μm / min, the number of stacking faults is 50 / cm ^2. It increased to the above. Further, at point C where the etching rate was 0.037 μm / min, the number of stacking faults was 8.8 pieces / cm ² , which is about twice that of point A (slightly less than twice). When the etching rate is smaller than 0.037 μm / min, the number of stacking faults is more than 8.8 / cm ² .

As described above, the effect of reducing the number of stacking faults can be improved by setting the etching rate in the vapor phase etching in the vicinity of 0.090 μm / min. Specifically, by setting the etching rate to 0.037 μm / min or more and 0.371 μm / min or less, the number of stacking faults is set to a value near the minimum value (4.9 pieces / cm ² ) (the minimum value of 2). (A value less than double). In other words, by setting the etching rate to 0.037 μm / min or more and 0.371 μm / min or less, the number of stacking faults can be suppressed to 10 pieces / cm ² or less. When 0.037 μm / min and 0.371 μm / min are rounded off to the third decimal place, 0.04 μm / min and 0.37 μm / min are obtained. Therefore, a silicon epitaxial wafer with a reduced number of stacking faults can be manufactured by performing vapor phase etching at an etching rate of 0.04 μm / min or more and 0.37 μm / min or less.

(Example 2)
FIG. 2 shows the relationship between the etching amount of vapor phase etching using hydrogen chloride gas and the concentration of stacking faults on the main surface of the wafer when the epitaxial layer is vapor grown on the low resistance silicon single crystal substrate subjected to the vapor phase etching. Is shown. The horizontal axis shows the etching amount of gas phase etching with hydrogen chloride gas, and the vertical axis shows the number of stacking faults per unit area generated on the main surface of the epitaxial wafer measured by a particle counter (MAGICS manufactured by Lasertec Corporation). Show. The number of stacking faults on the vertical axis is a value converted to the number per unit area by obtaining the number of stacking faults per wafer and dividing the number of stacking faults by the surface area of the wafer.

In the experiment of FIG. 2, a silicon single crystal substrate having a red phosphorus concentration of 1.0 × 10 ²⁰ atoms / cm ³ , a resistivity of 0.75 mΩcm, and a diameter of 200 mm was used. In the experiment of FIG. 2, the etching rate in the vapor phase etching is set to 0.090 μm / min at which the number of stacking faults is minimized in the first embodiment. After the vapor phase etching, purging for discharging hydrogen chloride gas from the chamber was performed for 30 seconds, and then a 4.0 μm silicon epitaxial layer was vapor grown on the main surface of the silicon single crystal substrate.

In FIG. 2, in the region where the etching amount is smaller than 0.025 μm, the number of stacking faults increases, and the number of stacking faults increases rapidly as the etching amount decreases. When the etching amount is 0.025 μm or more, the number of stacking faults converges to a constant value (about 5 / cm ² ). This result indicates that an etching amount of 0.025 μm or more is required for cleaning the substrate surface for the purpose of suppressing stacking faults, and the stacking fault nucleus is 0.025 μm or more deep from the substrate surface. It is considered to be localized in the region. Further, when the etching amount exceeds 1.000 μm, the productivity is lowered. Therefore, the etching amount is preferably 1.000 μm or less.

  From the above, the etching amount in the vapor phase etching is preferably 0.025 μm or more and 1.000 μm or less. This makes it possible to effectively remove stacking fault nuclei on the main surface of the silicon single crystal substrate, and as a result, a silicon epitaxial wafer with a reduced number of stacking faults can be obtained.

  The present invention is not limited to the above embodiment. The above embodiment is merely an example, and has the same configuration as the technical idea described in the claims of the present invention, and can produce any similar effects. It is included in the technical scope of the present invention.

Claims (3)

  In a method of vapor-phase-growing a silicon epitaxial layer on a main surface of a silicon single crystal substrate having a resistivity of 1.4 mΩcm or less, the main surface of the silicon single-crystal substrate is zeroed with hydrogen chloride gas before vapor phase growth of the epitaxial layer. A method for producing a silicon epitaxial wafer, comprising performing vapor phase etching at an etching rate of 0.04 μm / min or more and 0.37 μm / min or less. 2. The method for producing a silicon epitaxial wafer according to claim 1, wherein the silicon single crystal substrate is doped with at least 5 × 10 ¹⁹ atoms / cm ³ of red phosphorus.   3. The method for producing a silicon epitaxial wafer according to claim 1, wherein an etching amount in the vapor phase etching is 0.025 μm or more and 1.000 μm or less.

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