TW202233908A - Manufacturing method of monocrystal silicon stably producing an epitaxial substrate without depending on the epitaxial growth method and/or the process variation of an epitaxial growth method - Google Patents

Abstract

This invention provides a manufacturing method of a monocrystal silicon. The growth of Si-P defect generated in the process of pulling a monocrystal silicon ingot is suppressed, and an epitaxial substrate can stably be produced without depending on the epitaxial growth method and/or the process variation of an epitaxial growth method. The manufacturing method provided by this invention is to grow a monocrystal silicon by the Czochralski method by adding phosphorus as a dopant, and monitor and adjust the duration of each portion of the monocrystal in passing from 700 DEG C to 600 DEG C cooling process during the growth of the monocrystal silicon, thereby producing a monocrystal silicon with a resistivity of 0.6 m[Omega].cm to 1.0 m[Omega].cm.

Description

Manufacturing method of single crystal silicon

The present invention relates to a method for producing low-resistivity single-crystal silicon added with phosphorus (P).

In epitaxial silicon wafers for power MOSFETs (metal oxide semiconductor field effect transistors), lower resistivity of substrates is required, and 1 mΩ has been known so far. · cm or less substrates. In order to reduce the substrate resistivity of silicon wafers, there are the following methods: adding arsenic (As) and antimony (Sb) to molten silicon in the pulling step of single crystal silicon ingot as n-type resistivity adjustment dopant (n-type dopant). However, since these dopants are very easily volatilized, it is difficult to increase the dopant concentration in single-crystal silicon, and as a result, the substrate resistivity cannot be sufficiently reduced. Therefore, the n-type dopant species are transferred from As and Sb to phosphorus, and the concentration of phosphorus is about 1×10 ²⁰ atoms/cc.

However, when a high concentration of phosphorus is added during the growth of a single crystal ingot, for example, when the resistivity is set to 1.1 mΩ·cm or less, epitaxial growth is performed on a silicon wafer cut out from such a single crystal ingot. As the film grows, many stacking faults (stacking faults (hereinafter also referred to as "SF")) are generated in the epitaxial film. The SF appears on the surface of the epitaxial silicon wafer as a level difference, and the number of light point defects (LPD: light point defects) on the surface of the epitaxial silicon wafer increases.

The cause of SF after epitaxial growth is the cluster defect of phosphorus and oxygen (O) generated in the crystal pulling, and a single crystal silicon ingot growth method and a single crystal silicon ingot growth method are reported. SF suppression technology in subsequent heat treatment and epitaxial growth. For example, Patent Document 1 describes that an epitaxial silicon wafer obtained by growing an epitaxial film on the surface of a silicon wafer to which phosphorus has been added so that the resistivity becomes 0.6 mΩ·cm to 0.9 mΩ·cm In the manufacturing method, a wafer cut out from a single crystal silicon ingot at a passing temperature of 570±70° C. for each crystallization part in the crystallization cooling process does not exceed a passing time of 200 minutes; and in order to remove P-O clusters, After removing the backside oxide film of the silicon wafer, it is introduced into an argon annealing step of heat treatment at a temperature of 1200°C to 1220°C under an argon gas atmosphere before epitaxial growth.

Patent Document 2 discloses a method of manufacturing an epitaxial silicon wafer, which includes the steps of: forming an oxide film on the back surface of a single-crystal silicon wafer manufactured by the Czochralski method; The aforementioned steps of the backside oxide film; the step of performing heat treatment in an argon atmosphere for the silicon wafer from which the backside oxide film has been removed; and the step of forming an epitaxial film on the surface of the silicon wafer after argon annealing. Further, Patent Document 2 discloses a method for manufacturing an epitaxial silicon wafer: the above-mentioned epitaxial film forming step includes: subjecting the silicon wafer to a heat treatment in a gas atmosphere containing hydrogen and hydrogen chloride, thereby etching the silicon wafer. The prebake step of the surface layer of the wafer; and the step of growing an epitaxial film on the surface of the silicon wafer after the prebake step; the argon annealing step is to make the phosphorus and oxygen existing in the surface layer of the silicon wafer The clusters are solutionize; the aforementioned prebaking step is performed in such a way that the machining allowance of the silicon wafer surface layer is smaller than the thickness of the surface layer where the clusters would dissolve during the argon annealing step. .

However, in the techniques of Patent Document 1 and Patent Document 2, argon annealing is performed at a high temperature before epitaxial growth, so that defects related to phosphorus will re-grow at this time, so the suppression of SF after epitaxial growth is: opposite effect.

Patent Document 3 discloses a method of pulling a single crystal silicon, in which a seed crystal is brought into contact with a dopant-added melt obtained by adding red phosphorus to a silicon melt, and the pulling method is performed. In the method of Patent Document 3, a straight body portion with a length of 550 mm or less is formed so that the resistivity of single crystal silicon becomes 0.9 mΩ·cm or less; a tail portion with a length of 100 mm to 140 mm is formed at the lower end of the straight body portion; And the single-crystal silicon is cut|disconnected from the dopant addition melt in the state which made the upper end of a straight body part 590 degreeC or more.

However, if a tail of 100 mm to 140 mm is formed, the growth of aggregate (Si-P) defects formed from P and Si cannot be sufficiently suppressed, and the SF after epitaxial growth will increase, and it is necessary to stably produce epitaxial wafers. difficult. In addition, if the length of the straight body portion is 550 mm, there is a possibility that the profitability will deteriorate due to a decrease in productivity.

Patent Document 4 discloses a method for pulling up single crystal silicon, which is to add red phosphorus to a silicon melt so that the resistivity of single crystal silicon becomes 0.7 mΩ·cm to 0.9 mΩ·cm, and from the single crystal Silicon obtained evaluation The silicon wafer was heated in a hydrogen atmosphere at 1200°C for 30 seconds, and the number of pits generated was 0.1/cm ² or less, while the pulling temperature was 570°C±70°C for a period of time. The single crystal silicon is pulled up while controlling. [Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent No. 5845143. [Patent Document 2] Japanese Patent No. 6477210. [Patent Document 3] Japanese Patent No. 5892232. [Patent Document 4] International Patent Publication No. 2014/175120. [Non-patent literature]

[Non-Patent Document 1] The 29th International Conference on Defects in Semiconductors, Atomic Structure of Primary Si-P Precipitates in Red Phosphorus-Doped Czikolarski Crystals structures of grown-in Si-P precipitates in red-phosphorus heavily doped CZ-Si crystals (TuP-16)). [Non-Patent Document 2] The 78th Autumn Symposium of Applied Physics Society Structural Analysis of Si-P Precipitates in Red Phosphorus-Doped Czikolarski Crystals (7p-PB6-6). [Non-Patent Document 3] The 6th Research Conference on Silicon for Power Devices and Related Semiconductor Materials (December 17 (Mon.) to 18 (Tue.), 2018, Electric Power Central Research Institute) "Red Phosphorus High Doping Structural Analysis of Si-P Precipitates in Miscellaneous Chaikraski Silicon Crystals by Takeshi Senda (Global Wafer Japan)".

[The problem to be solved by the invention]

It is known that Si—P defects in which phosphorus is aggregated in an atomic % order amount exist in the inner system of single crystal silicon (Non-Patent Document 1 to Non-Patent Document 3). This defect cannot be completely eliminated by the heat treatment before epitaxial growth, and a build-up defect occurs, which is presumably determined that the defect remains in the vicinity of the surface layer before epitaxial growth, and is transmitted to the film-forming layer during the formation of the epitaxial film. and produce SF.

An object of the present invention is to provide a method for producing a single crystal silicon, which suppresses the growth of Si-P defects generated when a single crystal silicon ingot is pulled, and can stably produce an epitaxial substrate without depending on the epitaxial growth. Non-uniformity in the process of the growth method and/or the epitaxial growth method. [means to solve the problem]

The present invention is constituted by the following matters. The manufacturing method of the single crystal silicon of the present invention is to add phosphorus as a dopant in the Tchaikolaski (CZ) method, and to monitor and adjust the relationship between each single crystal part in the cooling process during the growth of the single crystal silicon. The passing time of 700°C to 600°C is used to produce single crystal silicon with resistivity of 0.6 mΩ·cm to 1.0 mΩ·cm.

The passing time from 700°C to 600°C in the single crystal silicon growth is preferably less than 300 minutes. The length of the tail made in the final stage of monocrystalline silicon growth is preferably 0 mm to 50 mm. In the growth of single crystal silicon, Si and P systems form Si-P defects. The average maximum side length of the aforementioned Si-P defects is preferably 50 nm or less, and the density of Si-P defects whose maximum side length is 35 nm or more is preferred. Preferably it is 3×10 ¹¹ pieces/cm ³ or less. [Inventive effect]

According to the present invention, the single crystal silicon ingot can be pulled while adjusting the passage time from 700° C. to 600° C. in the cooling process, whereby the growth of Si—P defects can be effectively suppressed, and the epitaxial growth after epitaxial growth can be controlled. SF produced by the crystal layer. Specifically, according to this invention, the average value of the maximum side length of Si-P defects can be set to 50 nm or less, and the density of Si-P defects with a maximum side length of 35 nm or more can be set to 3×10 ¹¹ Pieces/cm ³ or less can reduce the generation of SF in an epitaxial silicon wafer using the aforementioned silicon wafer. By using the silicon wafer of the present invention, the epitaxial substrate can be stably produced without depending on the method of epitaxial growth and/or the unevenness in the process of the method of epitaxial growth.

The method for producing single crystal silicon of the present invention is characterized in that: adding phosphorus as a dopant in the Tchaikolaski (CZ) method, and adjusting the temperature between 700°C and 600°C during the cooling process in the growth of the single crystal silicon. Through time, single-crystal silicon having a resistivity of 0.6 mΩ·cm to 1.0 mΩ·cm is thereby formed.

The CZ method is used in the production of the single crystal silicon of the present invention. The so-called CZ method is a method of filling a quartz crucible with polycrystalline silicon, heating/melting it with a heater, and immersing a small single crystal that is the basis for crystal growth as a seed crystal in the liquid surface (hydrothermal surface) of the silicon melt. , while rotating the quartz crucible and the seed crystal while pulling the large-diameter crystal rod. When single-crystal silicon is produced by the CZ method, the oxygen atoms dissolved from the quartz crucible will gather with each other at high temperature. Therefore, in the CZ method, by controlling the temperature of the crucible, the rotation speed of the quartz crucible, and the seed crystal, etc., a raw silicon wafer containing oxygen at a desired concentration can be produced.

In ordinary single crystal silicon, the void-like defects (COP (Crystal Originated Particle)) belonging to the aggregate of oxygen precipitates and voids are contained to 10 ⁸ /cm ³ and to 10 ⁶ , respectively. pieces/cm ³ . Since the COP is caused by the deterioration of the voltage resistance of the gate oxide film and the increase of the junction leakage current, etc., it is desirable to complete the process from the wafer surface to the device formation depth (up to 10 μm). removed.

In order to manufacture silicon wafers with low resistivity, if a dopant containing phosphorus is added to the silicon melt at a high concentration during the growth of a single crystal silicon ingot, it has the effect of reducing the COP. On the other hand, as described above, Since Si-P defects are generated when the dopant is phosphorus, it has a negative effect in the suppression of SF after epitaxy.

In view of this, in the present invention, the temperature conditions in the cooling process of pulling the single crystal ingot from the silicon melt added with phosphorus as a dopant and the passage time of the single crystal ingot under the conditions are adjusted, thereby This suppresses Si-P defect generation.

In terms of phosphorus, although there are yellow phosphorus, purple phosphorus, black phosphorus, red phosphorus and red phosphorus, etc., red phosphorus is usually used. The amount of phosphorus added is 0.10 wt % to 0.30 wt %, preferably 0.15 wt % to 0.25 wt %, with respect to the silicon melt. When the amount of phosphorus added is within the aforementioned range, the pulled single crystal silicon can achieve the low resistivity required for power MOSFETs.

The pulling of the single crystal silicon is performed while monitoring and adjusting the passage time of 700°C to 600°C during the cooling process of the pulling of the single crystal silicon. When Si—P defects reach a temperature close to 700° C. in the cooling process, growth is accelerated. Therefore, the size and density of Si-P defects can be adjusted by using a radiation thermometer, process information of a pulling device, etc., while monitoring and managing the transit time around 700°C during the cooling process while pulling the single crystal silicon. From the growth temperature region of Si—P defects, it can be said that the monitoring and adjustment range is preferably set to 700°C to 600°C.

If the temperature to be monitored and adjusted is less than 600° C., the growth of Si—P defects will be slow, and the degree of influence on the growth of defects will be small.

Under the condition that the passing time during the cooling process is monitored and adjusted in the temperature range of 700° C. to 600° C., the passing time of single crystal silicon is preferably less than 300 minutes. When the pulling time was less than 300 minutes, the average value of the maximum side lengths of Si—P defects was 50 nm or less. In FIG. 1 , when the passage time from 700° C. to 600° C. in the cooling process is less than 300 minutes, the average value of the maximum side length of Si—P defects is 50 nm or less. If the average value of the maximum side lengths of Si-P defects is 50 nm or less, the following silicon wafers can be manufactured with good yields: both the reduction of Si-P defects and the resulting reduction of SF can be achieved in the inspection steps and The occurrence rate of defective products in the delivery stage is low.

In addition, the density of Si—P defects having a maximum side length of 35 nm or more is preferably 3×10 ¹¹ cm ⁻³ or less. Since the density of Si—P defects with a maximum side length of 35 nm or more is 3×10 ¹¹ cm ⁻³ or less, SF after epitaxial growth can be suppressed.

By setting the average value of the maximum side length of Si-P defects to 50 nm or less, and setting the density of Si-P defects with a maximum side length of 35 nm or more to 3×10 ¹¹ pieces/cm ³ or less, it can be used in In the epitaxial silicon wafer obtained from the aforementioned silicon wafer, the generation of SF after epitaxial growth is reduced. FIG. 2 shows that the SF density is about 1×10 ³ cm ^-2 or less in the case where the passage time from 700° C. to 600° C. during the cooling process is less than 300 minutes, and the SF density is sufficiently reduced situation.

The length of the tail formed in the final stage of monocrystalline silicon growth is preferably 0 mm to 50 mm. The single crystal silicon ingot is composed of the following: a body part, where the crystal diameter is fixed; and a tail part, where the crystal diameter gradually decreases. The length of the main body is usually about 500 mm to 2000 mm, but when the length of the main body is less than 1200 mm, the yield is poor and the profitability is deteriorated. Therefore, it is preferable to set the length of the main body to 1200 mm to 2000 mm. On the other hand, by setting the length of the tail to be 0 mm to 50 mm, the pulling time of single crystal silicon at 700° C. to 600° C., which is the growth temperature of Si-P defects, is shortened. As a result, Si - The growth of P defects is suppressed, and the SF after epitaxial growth is reduced, which is related to the stable production of epitaxial wafers.

The resistivity of the obtained single crystal silicon is 0.6 mΩ·cm to 1.0 mΩ·cm, specifically, 0.7 mΩ·cm to 0.9 mΩ·cm. The resistivity of 0.6 mΩ·cm to 1.0 mΩ·cm is the optimum resistivity for front-end power MOSFETs. In addition, resistivity is the bulk resistivity (bulk resistivity) which measured the single crystal silicon ingot or the wafer cut out from this single crystal silicon ingot by the four-probe method.

The silicon epitaxial growth system is usually on a CZ substrate, using gases such as hydrogen (H ₂ ) as a carrier gas and trichlorosilane (SiHCl ₃ ) as a source gas to form a chemical gas. Phase growth method (CVD: Chemical Vapor Deposition) forms single crystal silicon. In conventional silicon wafers, SF is generated after epitaxial growth due to Si-P defects caused by high-concentration phosphorus doping; however, in the present invention, the largest edge of Si-P defects is The average length is 50 nm or less, and the density of Si—P defects with a maximum side length of 35 nm or more is 3×10 ¹¹ /cm ³ or less, so that an epitaxial silicon wafer with low SF density can be produced. Furthermore, as described above, by setting the passage time from 700° C. to 600° C. in the cooling process to be less than 300 minutes to pull up the single crystal silicon, such a single crystal silicon ingot can be stably produced. [Example]

Hereinafter, although an Example is shown and this invention is demonstrated more concretely, this invention is not limited to this. [Example 1] Using the CZ method, from a silicon melt to which phosphorus was added as an n-type dopant, the passage time from 700°C to 600°C during cooling was monitored and controlled, and a diameter of 200 mm and a crystal orientation ( 001) single crystal ingot. Here, the phosphorus concentration is set to be about 0.7×10 ²⁰ atoms/cm ³ to 1.3×10 ²⁰ atoms/cm ³ and the oxygen concentration to be 1.2×10 ¹⁸ atoms/cm ³ to 1.2×10 18 atoms/cm 3 from the beginning to the end of the single crystal ingot, respectively. 0.7×10 ¹⁸ atoms/cm ³ so that the resistivity of the silicon wafer cut out from the obtained single crystal ingot is 1.1 mΩ·cm to 0.6 mΩ·cm.

From the temperature profile at the time of pulling the single crystal silicon, the time for passing through 700° C. to 600° C. of each single crystal part in the cooling process was obtained. The transit time at 700°C to 600°C and any bulk crystal defects at each single crystal site were observed with a transmission electron microscope (TEM: transmission electron microscope), and the maximum Si-P defect was obtained. Average side length. As shown in FIG. 1 , the average value of the maximum side lengths of Si—P defects was 50 nm or less in the sites that passed in less than 300 minutes.

The single crystal ingot is sliced into wafers with a wire saw. Next, the silicon wafer is chamfered, strain layer removed, and etched by a known method, and then the wafer surface is mirror-finished.

After the surface of the mirror-finished wafer was cleaned by hydrogen baking (H ₂ baking), epitaxial growth of single-crystal silicon was carried out so as to have a thickness of 10 μm. The density of SF existing on the surface of the obtained epitaxial silicon wafer was observed with a microscope. According to FIG. 2 , the SF was reduced to about 1×10 ³ cm ⁻² or less in the portion that passed in less than 300 minutes.

The correlation between the size of Si-P defects and LPD was confirmed, and it was found that Si-P above 35 nm had a great influence (Fig. 3). In addition, the distribution of Si-P defects is assumed to be a normal distribution.

[ Fig. 1] Fig. 1 shows the Si- ingot in the single crystal silicon ingot with respect to the passing time in the case of pulling the single crystal silicon ingot while adjusting the passing time from 700°C to 600°C in the cooling process. A graph showing the dependency of the average size of P defects. FIG. 2 is a graph showing the relationship between the number of SFs observed on the surface of the epitaxial wafer and the passage time from 700° C. to 600° C. in the cooling process. Fig. 3 is a graph showing the relationship between the number of SFs observed on the epitaxial wafer surface and the density of Si-P defects with a maximum side length of 35 nm or more.

Claims (4)

A method for manufacturing single crystal silicon, which is cultivated by the method of Tchaikovsky; The above-mentioned method for manufacturing single crystal silicon is to add phosphorus as a dopant, and monitor and adjust the passage time of 700° C. to 600° C. of each single crystal part in the cooling process during the growth of single crystal silicon, thereby making the resistivity of 0.6 Monocrystalline silicon from mΩ·cm to 1.0 mΩ·cm. The method for producing single crystal silicon according to claim 1, wherein the passage time from 700°C to 600°C in the single crystal silicon growth is less than 300 minutes. The method for producing single crystal silicon as claimed in claim 1, wherein the length of the tails formed in the final stage of growing the single crystal silicon is 0 mm to 50 mm. The method for producing single crystal silicon according to any one of claims 1 to 3, wherein in the single crystal silicon growth, silicon and phosphorus systems form silicon-phosphorus defects; the average value of the maximum side lengths of the aforementioned silicon-phosphorus defects is 50 nm or less; the density of silicon-phosphorus defects with a maximum side length of 35 nm or more is 3×10 ¹¹ /cm ³ or less.

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