JP2008169109A - Single crystal, single crystal wafer and epitaxial wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a single crystal from which wafers excellent in nano-topology characteristics, especially excellent in nano-topology characteristics in the measurement of 2 mm×2 mm square can be cut out by improving the nano-topology characteristics from the aspect different from the processing conditions of the surface of the wafer, and to provide a method for growing the single crystal. <P>SOLUTION: The single crystal is obtained by a single crystal pulling method and characterized in that the intervals of uneven stripes which originate in the temperature variation of a melt of the crystal during crystal growth and are incorporated in the single crystal are controlled. The method for growing the single crystal is based on a single crystal pulling method, and in the method, when the growth rate during single crystal growth is defined as V (mm/min), the variation period of the temperature of the melt of the crystal is defined as F (min), and the angle of the crystal growth interface with respect to the horizontal plane is θ, the single crystal is grown while controlling the growth rate and/or the variation period of temperature so that V×F/sinθ becomes within a certain range. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a material used for a semiconductor device, specifically, a single crystal capable of obtaining a wafer having excellent nanotopological characteristics, a single crystal wafer cut from the single crystal, and The present invention relates to an epitaxial wafer in which an epitaxial layer is formed on the surface of the single crystal wafer.

  One material used for semiconductor devices is an epitaxial wafer. This epitaxial wafer is obtained by epitaxially growing silicon on, for example, a silicon single crystal wafer, and has been widely used as a wafer for manufacturing individual semiconductors, bipolar ICs and the like because of its excellent characteristics. MOS LSIs are also widely used in microprocessor units and flash memory devices because of their excellent soft error and latch-up characteristics. As an example of the excellent characteristics of an epitaxial wafer, since a so-called Grown-in defect introduced at the time of manufacturing a single crystal does not substantially exist in the epitaxial layer, defects such as DRAM reliability are reduced. That demand is growing.

  In particular, an epitaxial wafer epitaxially grown on a low resistivity wafer having a resistivity of 0.1 Ωcm or less is excellent in latch-up characteristics and has a gettering capability. Its importance is increasing.

  On the other hand, in recent years, in a semiconductor device manufacturing process, a metal wiring is formed on a wafer, an insulating film is formed thereon, and the insulating film is planarized by chemical mechanical polishing (CMP). When the metal oxide film and the second metal wiring are formed thereon, the irregularities of the nanometer order in the micro area (also referred to as nanotopography) called nanotopology existing on the polished surface of the wafer described above, This is considered to be one of the causes of the loss of uniformity in the thickness of the insulating film and causing a breakdown voltage failure, and has been regarded as a problem in the device manufacturer industry.

  This nanotopology indicates a surface shape with a period longer than the microroughness of the wafer surface and shorter than the surface flatness, and having a wavelength of about 0.1 mm to 20 mm and an amplitude of about several nm to 100 nm. It is.

  Further, the flatness of the wafer surface has been promoted by a request from lithography, and as the line width of lithography is miniaturized to 0.18 μm or more due to the recent high integration of semiconductor devices, Nanotopology has become a major problem. Furthermore, when polishing the surface by filling STI (Shallow Trench Isolation) with an insulating film, it is indispensable to improve not only the uniformity of polishing of CMP itself but also the nanotopology of the original wafer. .

  Therefore, research and examination of this nanotopology is conducted not only in device manufacturers but also in various parts including material manufacturers, public institutions, and academia, and active discussions are currently underway regarding measurement methods and quantitative definitions. . However, although there is recognition as described above for nanotopology, it has not yet reached a stage where official standards that are completely unified with respect to measurement methods and quantitative definitions for nanotopology have been compiled.

  As a nanotopology evaluation method that is currently mainly performed, in a region of a square block having a side of about 0.1 mm to 10 mm or a circular block having a diameter of about 0.1 mm to 10 mm (also called WINDOW SIZE etc.), There is a method for evaluating the level difference (PV value: Peak to Valley) of the unevenness on the wafer surface. This PV value is also referred to as Nanotopography Height. In the evaluation of semiconductor wafers by nanotopography, it is desired that the maximum value of the unevenness existing in the wafer surface is small, and usually a measurement is performed on a plurality of block ranges with a square of 2 mm × 2 mm. The maximum value of the PV value is evaluated, and the smaller the maximum value of the PV value, the higher the quality of the wafer.

  For such nanotopology measurement, WIS-CR83-SQM or NanoMapper made by ADE, Surfscan-SP1-STN made by KLA-Tencor, DynaSearch made by New Creation, NanoMetro made by Kuroda Seiko, etc. are used. Has been done. All of these measuring devices optically measure unevenness by utilizing surface reflection.

  In general, the nanotopology of the wafer surface is considered to be determined by the etching conditions and polishing conditions in the wafer surface processing step. For this reason, as disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-141311, improvement of nanotopology characteristics is mainly sought for a solution by examining the processing conditions of the wafer surface from the recognition of the problem of CMP in wafer surface processing. However, there has been almost no attempt to improve the wafer surface from a viewpoint other than the processing conditions.

  In the future, with regard to nanotopology characteristics, it will become necessary to meet stricter standards as device sizes become smaller. In particular, it is clear that materials for the next generation will be used in the state-of-the-art ultra-fine lithography line, and it is clear that a wafer having excellent nanotopological characteristics will be required.

  Therefore, it is necessary to manufacture a wafer having very excellent nanotopology characteristics by improving the nanotopology characteristics not only from the processing conditions of the wafer surface as in the past but also from other viewpoints. come.

JP 2002-141111 (paragraphs (0016)-(0023), FIGS. 1 to 3)

  Therefore, the present invention has been made in view of the above points, and improved the nanotopology characteristics from a viewpoint different from the processing conditions of the wafer surface, and the nanotopology characteristics, particularly the nanotopology characteristics in the measurement of 2 mm × 2 mm square. A single crystal capable of cutting out an excellent wafer, a single crystal wafer cut out from the single crystal, an epitaxial wafer in which an epitaxial layer is formed on the surface of the single crystal wafer, and a single crystal growth method for growing the single crystal The purpose is to provide.

  In order to achieve the above object, according to the present invention, a single crystal obtained by a single crystal pulling method, wherein the non-uniformity is incorporated into the single crystal due to temperature fluctuation of the crystal melt during crystal growth. There is provided a single crystal characterized in that the distance between stripes is controlled.

  The present inventors have newly found that the nanotopological characteristics of the wafer surface depend on the spacing of non-uniform stripes taken into the single crystal due to temperature fluctuations of the crystal melt during crystal growth. Therefore, as described above, the single crystal obtained by the single crystal pulling method has a controlled interval of non-uniform stripes taken into the single crystal due to temperature fluctuation of the crystal melt during crystal growth. If it exists, it can be set as the single crystal which can cut out the outstanding single crystal wafer by which the nanotopological characteristic was controlled.

  At this time, it is preferable that the interval between the non-uniform stripes is controlled to 1.5 mm or less or 2.3 mm or more in a plane perpendicular to the crystal growth axis direction.

  As described above, if the interval between the non-uniform stripes taken into the single crystal is controlled to 1.5 mm or less or 2.3 mm or more in a plane perpendicular to the crystal growth axis direction, It is possible to obtain a single crystal capable of cutting out a single crystal wafer having a very excellent nanotopology level in a 2 mm × 2 mm square region measured in (1).

Furthermore, it is preferable that the single crystal is silicon and the resistivity is 0.1 Ω · cm or less.
As a result of repeated research on nanotopological characteristics, the present inventors have found that conventional low resistivity single crystal wafers have excellent gettering ability, but due to the action of dopants added for resistivity control, nonuniform stripes are obtained. It has been found that the degradation of nanotopology due to the influence of is serious. Therefore, if the single crystal of the present invention is silicon as described above and has a resistivity as low as 0.1 Ω · cm or less, nanotopology deterioration can be reliably prevented and gettering can be achieved. It is very useful because it can be made a single crystal that has a superior ability and a wafer with excellent nanotopological characteristics.

The single crystal silicon may have a diameter of 200 mm or more.
In general, a large-diameter crystal having a diameter of 200 mm or more is difficult to grow at a certain high speed, and is often grown in a slightly slow speed range. As a result, the nanotopology characteristics have to be deteriorated in large-diameter crystals, particularly crystals having a diameter of 200 mm or more. In the present invention, it has been found that the nanotopology characteristics can be improved by increasing the growth rate to some extent, and therefore a wafer having excellent nanotopology characteristics can be obtained even with a single crystal having a diameter of 200 mm or more. In addition, improving the nanotopological characteristics by increasing the growth rate can improve productivity as well as quality.

  According to the present invention, it is possible to provide a single crystal wafer characterized by being cut out from the single crystal of the present invention. At this time, the entire surface of the single crystal wafer is 2 mm × 2 mm square. The average of the maximum value of the nanotopology level in the region can be 14 nm or less.

  Such a single-crystal wafer of the present invention can be a high-quality wafer excellent in nanotopology characteristics, particularly when the 2 mm × 2 mm square nanotopology level is measured over the entire surface of the wafer. A single crystal wafer having a good average value of 14 nm or less is achieved.

  Furthermore, according to the present invention, there can be provided an epitaxial wafer characterized in that an epitaxial layer is formed on the surface of the above-described single crystal wafer of the present invention, and at this time, the wafer of the epitaxial wafer is provided. The average of the maximum value of the nanotopology level in a 2 mm × 2 mm square region over the entire surface can be 14 nm or less.

  The nanotopology characteristics of an epitaxial wafer reflect the nanotopology characteristics of the substrate. Therefore, if the epitaxial wafer has an epitaxial layer formed on the surface of the single crystal wafer of the present invention as described above, the nanotopology It can be excellent in characteristics. In particular, when the 2 mm × 2 mm square nanotopology level of the epitaxial wafer is measured over the entire surface of the epitaxial wafer, a satisfactory level with an average of the maximum values of 14 nm or less is achieved. Further, an epitaxial wafer having excellent nanotopology characteristics generates little internal stress (strain) due to unevenness between the surface of the single crystal wafer and the epitaxial layer, so that no slip line is generated in the epitaxial layer. As a result, an epitaxial wafer having high gettering ability due to misfit can be obtained by using a low-resistivity single crystal wafer having a high thermal mechanical strength as a substrate during device manufacture. Furthermore, a latch-up characteristic is excellent if the wafer has a low resistivity.

  According to the present invention, there is also provided a single crystal growth method for growing a single crystal by a single crystal pulling method, wherein the growth rate during single crystal growth is V (mm / min), and the temperature fluctuation period of the crystal melt is set to A single crystal is grown by controlling the growth rate and / or the temperature fluctuation period so that V × F / sin θ is in a certain range, where F (min) is θ and the angle of the crystal growth interface with respect to the horizontal plane is θ. A single crystal growth method characterized by the above can be provided.

  Thus, when a single crystal is grown by the single crystal pulling method, V × F / sin θ is within a certain range with respect to the growth rate V, the temperature fluctuation period F of the crystal melt, and the angle θ of the crystal growth interface with respect to the horizontal plane. By controlling the growth rate and / or the temperature fluctuation period so as to be, the spacing of the non-uniform stripes taken into the single crystal due to the temperature fluctuation of the crystal melt during crystal growth is controlled to an appropriate size. be able to. Therefore, a single crystal capable of cutting out an excellent single crystal wafer with controlled nanotopology characteristics can be produced. As will be described later, V × F / sin θ corresponds to a non-uniform fringe interval caused by a temperature change of the melt in a plane perpendicular to the crystal growth axis direction.

At this time, it is preferable to grow the single crystal so that the V × F / sin θ is 1.5 mm or less or 2.3 mm or more.
Thus, when a single crystal is grown, a single crystal having a very excellent nanotopology level of 2 mm × 2 mm square is obtained by making V × F / sin θ 1.5 mm or less or 2.3 mm or more. A single crystal capable of cutting a wafer can be obtained.

Furthermore, it is preferable that the single crystal to be grown is silicon and its resistivity is 0.1 Ω · cm or less.
As described above, the single crystal grown by the present invention is made of silicon and its resistivity is set to 0.1 Ω · cm or less, thereby preventing nanotopology deterioration which is a problem in the low resistivity single crystal, and an excellent getter. A single crystal capable of cutting a wafer having ring ability and excellent nanotopological characteristics can be produced.

  In addition, the temperature fluctuation period of the crystal melt is controlled by controlling any one or more of the magnetic field strength applied to the crystal melt, the crucible rotation speed, the single crystal rotation speed, the introduced gas flow rate, and the crystal melt amount. It is preferable to do so.

  In this way, the temperature fluctuation cycle is controlled by controlling one or more of the magnetic field strength applied to the crystal melt, the crucible rotation speed, the single crystal rotation speed, the introduced gas flow rate, and the crystal melt amount. The temperature fluctuation period can be controlled easily and with high accuracy.

  According to the present invention, the nanotopology characteristics can be improved by controlling the spacing of the non-uniform stripes taken into the single crystal by controlling the single crystal growth conditions. Therefore, a single crystal capable of cutting a wafer having excellent nanotopology characteristics, particularly a nanotopology characteristic in a 2 mm × 2 mm square region, a single crystal wafer cut from the single crystal, and an epitaxial layer formed on the single crystal wafer An epitaxial wafer can be provided. Furthermore, the epitaxial wafer of the present invention is excellent in film thickness uniformity of the epitaxial layer, and a high yield in an LSI device can be expected.

Hereinafter, although an embodiment is described about the present invention, the present invention is not limited to these.
Conventionally, it is thought that nanotopology characteristics are mainly determined by the etching conditions and polishing conditions in the wafer surface processing process, and attempts to improve nanotopology characteristics from a viewpoint other than wafer surface processing There wasn't.

  In order to improve the nanotopological characteristics from various angles, the present inventors have conducted research on the nanotopological characteristics of the single crystal wafer. As a result, when growing a single crystal, the spacing of the non-uniform stripes incorporated in the single crystal due to temperature fluctuations of the crystal melt during crystal growth is close to the size of the measurement area when measuring the nanotopology Occasionally, we have found that the nanotopological properties of single crystal wafers are degraded.

  In particular, the conventional low resistivity silicon single crystal doped with, for example, boron or phosphorus has the advantage of excellent gettering ability, but the hardness of the wafer is high due to the large amount of dopant controlling the resistivity. As a result, the non-uniformity of the dopant concentration causes a difference in hardness of the single crystal and tends to appear as fine irregularities on the surface of the silicon wafer cut out from the single crystal. Therefore, it has been found that the conventional low resistivity silicon single crystal has a very serious deterioration in nanotopology caused by nonuniform stripes caused by crystal growth.

  Therefore, the present inventors, when growing a single crystal, the non-uniform fringe spacing due to the temperature fluctuation of the crystal melt is different from a certain range, that is, the size of the measurement region when measuring the nanotopology. The inventors have found that by controlling to the range, the nanotopological characteristics can be improved from a viewpoint other than the wafer surface processing, and the present invention has been completed.

  That is, according to the present invention, a single crystal obtained by a single crystal pulling method is used, and the interval of nonuniform stripes taken into the single crystal due to temperature fluctuation of the crystal melt during crystal growth is controlled. A single crystal is provided that is characterized by

  Furthermore, the present invention provides a single crystal growth method for growing a single crystal by a single crystal pulling method as a method for growing a single crystal as described above, wherein the growth rate at the time of single crystal growth is V (mm / min). And the temperature fluctuation period of the crystal melt is F (min), and the angle of the crystal growth interface with respect to the horizontal plane is θ, the growth rate and / or the temperature fluctuation period so that V × F / sin θ is in a certain range. The present invention provides a method for growing a single crystal characterized by controlling the growth of the single crystal.

Hereinafter, the single crystal growth method of the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto.
The single crystal growth apparatus used in the single crystal growth method of the present invention is not particularly limited. For example, a single crystal growth apparatus as shown in FIG. 10 can be used. Hereinafter, a single crystal growth apparatus for performing the single crystal growth method of the present invention will be described with reference to FIG.

  10 includes a quartz crucible 5 filled with a crystal melt 4, a graphite crucible 6 that protects the quartz crucible 5, a heater 7 and a heat insulating material 8 arranged so as to surround the crucibles 5 and 6. Is installed in the main chamber 1, and a pulling chamber 2 for accommodating and taking out the grown single crystal 3 is connected to the upper portion of the main chamber 1.

  When the single crystal 3 is grown using such a single crystal growing apparatus, the seed crystal is immersed in the crystal melt 4 in the quartz crucible 5 by the Czochralski method (CZ method), and then rotated through the seed drawing. The rod-shaped single crystal 3 is grown by gently pulling up. On the other hand, the crucibles 5 and 6 can be moved up and down in the direction of the crystal growth axis, and the crucible is raised so as to compensate for the liquid level drop of the melt that has been crystallized and decreased during the crystal growth. Is kept constant. In addition, an inert gas such as argon gas is introduced into the main chamber 1 from a gas inlet 10 provided in the upper part of the pulling chamber 2, and the space between the single crystal 3 being pulled and the gas rectifying cylinder 11 is interposed. It passes between the lower part of the heat shield member 12 and the melt surface, and is discharged from the gas outlet 9. Further, using a radiation thermometer (not shown), the temperature of the crystal melt 4 in the quartz crucible 5 is measured from the radiation on the surface of the crystal melt through a glass window, and the temperature fluctuation period of the crystal melt is measured. .

  According to the present invention, when a single crystal is grown in this way, the growth rate at the time of growing the single crystal is V (mm / min), the temperature fluctuation period of the crystal melt is F (min), and the crystal growth It is important to grow a single crystal by controlling the growth rate and / or temperature fluctuation period so that V × F / sin θ is in a certain range when the angle of the interface with respect to the horizontal plane is θ.

  Usually, when a single crystal is grown by the single crystal pulling method as described above, the shape of the crystal growth interface is an upwardly convex shape as shown in FIG. Small fluctuations are taken into the single crystal to generate nonuniform stripes as shown in FIG. At this time, the interval d between the non-uniform stripes is represented by the product d = V × F of the growth rate V of the single crystal and the temperature fluctuation period F of the crystal melt.

  When a single crystal wafer is cut out from a single crystal having nonuniform stripes as shown in FIG. 7, stripes as shown in FIG. 8 are formed on the produced single crystal wafer. At this time, if the interval between the non-uniform fringes on the wafer surface is L (FIG. 9), the non-uniform fringe interval L is expressed as L = d / sin θ = V × F / sin θ using the angle θ with respect to the horizontal plane of the crystal growth interface. It is expressed. Incidentally, the shape of the crystal growth interface has a curvature as shown in FIG. 6, and when measured strictly, the value of the non-uniform fringe interval L varies in the radial direction of the wafer even within the same wafer surface. However, since the error is very small with respect to the value of L, even if the shape of the crystal growth interface has a curvature, the interval between the non-uniform fringes on the entire wafer surface is obtained with L = V × F / sin θ as a representative value. be able to.

  According to the studies by the present inventors, as described above, when the non-uniform fringe spacing L is close to the size of the measurement region when measuring the nanotopology characteristics, the nanotopology characteristics of the single crystal wafer are measured. It became clear that it deteriorates. Therefore, when growing a single crystal, the interval L between the non-uniform stripes on the wafer surface, that is, the value of V × F / sin θ is different from the size of the measurement region when measuring the nanotopology. By controlling the crystal growth rate V and / or the temperature fluctuation period F of the crystal melt, it is possible to prevent the deterioration of the nanotopological characteristics.

  As described above, the current nanotopology is measured mainly in a 2 mm × 2 mm square region. Therefore, in order to improve the nanotopological characteristics in this 2 mm × 2 mm square region, in the grown single crystal, the non-uniform fringe spacing L in the plane perpendicular to the crystal growth axis direction, that is, V × It is important that F / sin θ is not about 2 mm. In particular, it is preferable to grow the single crystal by controlling the growth rate V and / or the temperature fluctuation period F so that V × F / sin θ is 1.5 mm or less or 2.3 mm or more. It has been experimentally confirmed that a nanotopology level of 14 nm or less can be obtained when the is fabricated (FIG. 1).

  The above range of V × F / sin θ is to prevent degradation of nanotopology characteristics when nanotopology is measured in a 2 mm × 2 mm square region currently being used. The range of F / sin θ is not limited to this. In other words, if the nanotopology measurement region will change in the future due to official standards or technological advances, the present invention appropriately changes the V × F / sinθ range according to the nanotopology measurement region. Needless to say, it is possible to prevent degradation of nanotopological properties.

  At this time, the growth rate V of the single crystal can be controlled by controlling the pulling rate when pulling the single crystal. On the other hand, the temperature fluctuation period F of the crystal melt is controlled by, for example, at least one of the following items: magnetic field strength applied to the crystal melt, crucible rotation speed, single crystal rotation speed, introduced gas flow rate, and crystal melt amount. This can be done easily by controlling

  In particular, the temperature fluctuation period can be easily and accurately controlled by controlling the magnetic field strength applied to the crystal melt. Actually, using the single crystal growth apparatus shown in FIG. 10 (equipped with a crucible having a diameter of 800 mm), after charging 320 kg of silicon raw material and melting them, the silicon was brought into a state just before the silicon single crystal was grown. The surface temperature of the melt was measured using a radiation thermometer. At this time, the intensity at the center of the horizontal magnetic field was changed from 0 G to 4000 G, and the temperature fluctuation period of the melt surface was measured. As a result, as shown in FIG. 5, F = 0.26min at 0G, 0.39min at 1000G, 0.44min at 2000G, 0.50min at 3000G, 0.55min at 4000G, and along with the change in magnetic field strength. The temperature fluctuation cycle also changed. From this result, it was confirmed that the temperature fluctuation period of the crystal melt can be controlled with high accuracy by controlling the magnetic field strength applied to the crystal melt. Therefore, by controlling the magnetic field strength, the non-uniform fringe spacing L in the wafer plane can be controlled with high accuracy. As a result, the nanotopology can be greatly improved.

  As described above, by using the method for growing a single crystal according to the present invention, a single crystal in which the spacing of nonuniform stripes taken into the single crystal due to temperature fluctuation of the crystal melt during crystal growth is controlled is manufactured. can do. A single crystal in which the spacing between non-uniform stripes resulting from crystal growth is controlled can be a single crystal capable of cutting out a single crystal wafer having excellent nanotopology characteristics. That is, according to the present invention, it is possible to improve the nanotopological characteristics of a wafer by controlling the single crystal growth conditions rather than controlling the wafer surface processing conditions as in the prior art.

  Furthermore, according to the present invention, the single crystal to be grown is silicon, and even if silicon is doped with boron, phosphorus or the like and exhibits a low resistivity of 0.1 Ω · cm or less, it is incorporated into the single crystal. By controlling the spacing of the non-uniform stripes, it is possible to reliably prevent the deterioration of the nanotopological characteristics that has been particularly serious in the conventional single crystal having a low resistivity as described above. Therefore, it is possible to grow a silicon single crystal having a low resistivity, which is excellent in gettering ability and obtains a wafer having excellent nanotopology characteristics. At this time, the lower limit of the resistivity is not particularly limited. For example, the resistivity of the single crystal when a dopant such as boron or phosphorus is doped to the solid solution limit is the lower limit.

  In addition, according to the present invention, the diameter of the single crystal is 200 mm or more, and the nanotopology characteristics can be improved by increasing the growth rate to some extent. Thus, improving the nanotopology characteristics by increasing the growth rate can improve not only the quality but also the productivity.

In addition, after a single crystal is grown by the above-described method for growing a single crystal according to the present invention, the single crystal is cut out and subjected to processes such as lapping, chamfering, and polishing, which are conventionally performed, to manufacture a single crystal wafer. be able to.
Such a single crystal wafer can be a high-quality wafer excellent in nanotopology characteristics. In particular, when the nanotopology level in a 2 mm × 2 mm square region is measured over the entire surface of the wafer, a single crystal wafer in which a satisfactory average level of 14 nm or less is achieved.

  Furthermore, an epitaxial wafer can be manufactured by forming an epitaxial layer on the surface of this single crystal wafer. With such an epitaxial wafer, the nanotopology characteristics of the single crystal wafer serving as the substrate are excellent, and therefore the nanotopology characteristics of the epitaxial wafer are also excellent. In particular, when the nanotopology level in the 2 mm × 2 mm square region of the epitaxial wafer is measured over the entire surface of the wafer, a satisfactory level with an average of maximum values of 14 nm or less is achieved.

  In addition, epitaxial wafers with excellent nanotopology characteristics have excellent film thickness uniformity of the epitaxial layer, and internal stress (strain) is generated due to irregularities between the surface of the single crystal wafer and the epitaxial layer. Therefore, slip lines are not generated in the epitaxial layer. Therefore, it has a high gettering capability by using a low resistivity single crystal wafer having a high thermal mechanical strength as a substrate, particularly 0.1Ω · cm or less, during device manufacture. Therefore, a high yield in the LSI device can be expected.

  In the present invention, the temperature fluctuation of the crystal melt is described focusing on the temperature fluctuation period. However, based on the fundamental discovery of the present invention, the nanotopological characteristics of a single crystal wafer can be improved by reducing the temperature fluctuation range of the crystal melt.

EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.
In the following examples and comparative examples, nanotopology is measured in a 2 mm × 2 mm square region. Further, in order to examine in advance the crystal growth interface shape when growing a silicon single crystal of the same diameter with the single crystal growth apparatus used here, that is, the angle θ with respect to the horizontal plane of the crystal growth interface, the following X-ray topograph is used. Observations were made. First, a single crystal was grown while changing the growth rate and the magnetic field strength, and this single crystal was sliced in the direction of the crystal growth axis to prepare a vertically divided sample, which was then heated at 800 ° C. for 4 hours + 1000 ° C. for 16 hours. A precipitation heat treatment was performed. Thereafter, the vertically divided samples were observed by X-ray topography. The observation results are shown in FIG. 2 (only the radius portion). From the observation result by the X-ray topograph, the angle θ with respect to the horizontal plane of the crystal growth interface was obtained, and it was found that there was almost no change at θ = 10.

(Example 1)
First, using the single crystal growth apparatus (equipped with a quartz crucible having a diameter of 800 mm) shown in FIG. A silicon single crystal having a straight body length of about 120 cm was grown. At that time, the resistivity of the single crystal was adjusted to 0.006 to 0.009 Ω · cm by doping with boron. At this time, since the temperature fluctuation period at a magnetic field strength of 4000 G is 0.55 min from the relationship between the magnetic field intensity and the temperature fluctuation period shown in FIG. 5, the growth rate is controlled to 0.44 mm / min. The value of V × F / sin θ in 1 was set to V × F / sin θ = 0.44 × 0.55 / sin 10 = 1.39 (mm).

  A silicon wafer was cut out from the thus grown silicon single crystal, and nanotopology was measured in a 2 mm × 2 mm square region. In general, the larger the amount of silicon solution, the stronger the thermal convection and the greater the temperature fluctuation. Therefore, the earlier the single crystal is grown, the more likely the uneven stripes resulting from the temperature fluctuation of the solution are affected. Therefore, in this example, 50 silicon wafers cut from a range of 10 to 15 cm from the single crystal shoulder were prepared, and their nanotopology was measured. As a result, the average of the maximum value of the nanotopology level in a 2 mm × 2 mm square region in 50 silicon wafers was a good value of 13.3 nm, and it was found that the nanotopology characteristics were excellent.

(Example 2)
Using the same single crystal growth apparatus as in Example 1, a silicon single crystal having a diameter of 300 mm and a straight body length of about 120 cm was grown while applying a horizontal magnetic field having a central magnetic field strength of 3000 G. At that time, the resistivity of the single crystal was set to 0.006 to 0.009 Ω · cm as in Example 1. At this time, since the temperature fluctuation period at a magnetic field strength of 3000 G is 0.50 min, the growth rate is controlled to 0.92 mm / min, and the value of V × F / sin θ in Example 2 is set to V × F. / Sin θ = 0.92 × 0.50 / sin 10 = 2.65 (mm).

  Fifty silicon wafers cut from a range of 10 to 15 cm from the shoulder of the silicon single crystal grown in this way were produced, and their nanotopology was measured. As a result, the average of the maximum values of the nanotopology level was a very good value of 11.4 nm, and the nanotopology characteristics were very excellent. FIG. 3 shows a map obtained by measuring the nanotopology of the silicon wafer produced. As shown in FIG. 3, in the silicon wafer of Example 2, nonuniform stripes due to crystals are not strongly observed on the wafer surface, and it can be seen that the unevenness of the wafer surface is small.

  Furthermore, when an epitaxial layer was formed on the surface of this silicon wafer to produce an epitaxial wafer and the nanotopology was measured, it showed a nanotopology level almost equivalent to the above, and the nanotopology characteristics were very good. all right.

(Example 3)
Using the same single crystal growth apparatus as described above, a silicon single crystal having a diameter of 300 mm and a straight body length of about 120 cm was grown without applying a magnetic field. At that time, the resistivity of the single crystal was set to 0.006 to 0.009 Ω · cm. At this time, since the temperature fluctuation period at a magnetic field strength of 0 G is 0.26 min, the growth rate is controlled to 0.82 mm / min. In Example 3, V × F / sin θ = 0.82 × 0.26. /Sin10=1.23 (mm).

  Fifty silicon wafers cut from a range of 10 to 15 cm from the shoulder of the silicon single crystal grown in this way were produced, and their nanotopology was measured. As a result, the average of the maximum values of the nanotopology level was a good value of 12.3 nm, and the nanotopology characteristics were excellent.

(Comparative Example 1)
Using the same single crystal growth apparatus as in the above example, a silicon single crystal having a diameter of 300 mm and a straight body length of about 120 cm was grown while applying a horizontal magnetic field with a central magnetic field strength of 4000 G. At that time, the resistivity of the single crystal was set to 0.006 to 0.009 Ω · cm as in the example. At this time, the growth rate was controlled to 0.55 mm / min so that V × F / sin θ = 0.55 × 0.55 / sin 10 = 1.74 (mm). This value is close to 2 mm, which is the current nanotopology measurement region.

  Fifty silicon wafers cut from a range of 10 to 15 cm from the shoulder of the silicon single crystal grown in this way were produced, and their nanotopology was measured. As a result, the average of the maximum values at the nanotopology level was as large as 14.7 nm, and the nanotopology characteristics were deteriorated. At this time, the result of measuring the nanotopology of the fabricated silicon wafer is shown in a map form as shown in FIG. 4. Uneven fringes due to crystal growth are strongly observed on the wafer surface, and the unevenness of the wafer surface is clearly confirmed. It was done.

(Comparative Example 2)
Using the same single crystal growth apparatus as described above, a silicon single crystal having a diameter of 300 mm and a straight body length of about 120 cm was grown while applying a horizontal magnetic field having a central magnetic field strength of 4000 G. At that time, the resistivity of the single crystal was set to 0.006 to 0.009 Ω · cm. At this time, the growth rate was controlled to 0.63 mm / min so that V × F / sin θ = 0.63 × 0.55 / sin 10 = 1.99 (mm). This value is almost the same as the current nanotopology measurement region.

  Fifty silicon wafers cut from a range of 10 to 15 cm from the shoulder of the silicon single crystal grown in this way were produced, and their nanotopology was measured. As a result, the average of the maximum values of the nanotopology level was a very large value of 15.3 nm, and the nanotopology characteristics were greatly deteriorated.

  The results of Examples 1 to 3 and Comparative Examples 1 and 2 are plotted in a graph with V × F / sin θ on the horizontal axis and the measured nanotopology level on the vertical axis. From FIG. 1, the nanotopology level is most deteriorated when the value of V × F / sin θ is 2 mm, and the nanotopology characteristics of the wafer are better as the value of V × F / sin θ is smaller or larger than 2 mm. I understand that Furthermore, in the range where V × F / sin θ is 1.5 mm or less or 2.3 mm or more, the average of the maximum value of the nanotopology is 14 nm or less.

  Also, as in Examples 2 and 3, the ability to improve the nanotopology by increasing the growth rate is a very promising technique from the viewpoint of improving productivity. When a large-diameter single crystal having a diameter of 200 mm or more is grown, it is difficult to grow a crystal at a high speed. Therefore, the crystal is generally grown in a speed range as in Comparative Examples 1 and 2 where the crystal growth speed is somewhat slow. Therefore, if the growth rate is increased and the nanotopology characteristics are improved as in Examples 2 and 3, not only the quality but also the productivity can be improved.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

  For example, in the above description, a case where a single crystal having a diameter of 300 mm is grown has been described as an example. However, the present invention is not limited to this, and a single crystal having a large diameter of 200 mm or 400 mm or more is grown. Even in this case, the present invention can be similarly applied.

It is a graph showing the relationship between V * F / sin (theta) and nanotopology level. It is a figure showing the result (only a radius part) which observed the vertically divided sample of the single crystal by X-ray topograph in order to investigate the crystal growth interface shape. It is the figure which showed the result of having measured the nano topology of the wafer in Example 2 in the shape of a map. It is the figure which showed the result of having measured the nano topology of the wafer in the comparative example 1 in the shape of a map. It is a graph showing the relationship between magnetic field strength and the temperature fluctuation period of a crystal solution. It is the figure which represented typically the crystal growth interface at the time of growing a single crystal. It is sectional drawing of the single crystal which represented typically a mode that the temperature fluctuation of the crystal solution was taken in in the single crystal as a nonuniform stripe. It is sectional drawing which represented typically the wafer cut out from the single crystal of FIG. It is the figure which represented typically the space | interval L of the nonuniform stripe in the wafer surface. It is a schematic diagram of the single crystal growth apparatus used in the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Main chamber, 2 ... Pulling chamber, 3 ... Single crystal, 4 ... Crystal melt, 5 ... Quartz crucible, 6 ... Graphite crucible, 7 ... Heating heater, 8 ... Heat insulation material, 9 ... Gas outflow port, 10 ... Gas Inlet 11, gas rectifier cylinder 12, heat shield member.

Claims (6)

  A silicon single crystal obtained by a single crystal pulling method, and the interval of non-uniform stripes taken into the single crystal due to temperature fluctuations of the crystal melt during crystal growth is perpendicular to the crystal growth axis direction. A silicon single crystal characterized by being controlled to 1.5 mm or less or 2.3 mm or more and having a resistivity of 0.1 Ω · cm or less.   The silicon single crystal according to claim 1, wherein the silicon single crystal has a diameter of 200 mm or more.   A single crystal wafer cut from the silicon single crystal according to claim 1.   4. The single crystal wafer according to claim 3, wherein the average of the maximum values of the nanotopology level in a 2 mm × 2 mm square region is 14 nm or less over the entire surface of the single crystal wafer.   An epitaxial wafer characterized in that an epitaxial layer is formed on the surface of the single crystal wafer according to claim 3 or 4.   6. The epitaxial wafer according to claim 5, wherein the average of the maximum values of nanotopology levels in a 2 mm × 2 mm square region is 14 nm or less over the entire wafer surface of the epitaxial wafer.

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