JP5780491B2 - Manufacturing method of silicon epitaxial wafer - Google Patents

Description

  The present invention relates to a method for manufacturing a silicon epitaxial wafer.

  In the case of applications such as power devices, a silicon epitaxial wafer is a low-concentration structure configured to have either P-type or N-type conductivity by adding impurities at a high concentration as a silicon substrate on which an epitaxial film is formed. A resistive substrate is used.

  When the conductivity type is P-type, boron (B) or the like is added as an impurity. When the conductivity type is N-type, phosphorus (P), antimony (Sb), arsenic (As), or the like is added as a silicon substrate. To be added.

  However, when the silicon substrate is heated to a high temperature (1000 to 1200 ° C.) to grow an epitaxial film on the silicon substrate to which such impurities are added, the above-mentioned impurities jump out of the silicon substrate and grow in the grown epitaxial film. There is a problem that a phenomenon (auto-doping) is taken in.

  The occurrence of this auto-doping causes a deterioration in the uniformity of the in-wafer surface of the resistivity and the like, and therefore needs to be suppressed as much as possible.

  As a method for improving the occurrence of auto-doping, adjusting the temperature distribution in the wafer surface is used. Specifically, the temperature at the outer periphery of the wafer is heated to be lower than the temperature at the center of the wafer. Things have been done.

  However, in order to improve the uniformity of the resistivity within the wafer surface, when the wafer is heated, a slip occurs in the wafer surface temperature distribution in which the temperature on the outer periphery of the wafer is lower than the temperature at the center of the wafer. There is a problem.

  That is, in order to improve the uniformity of resistivity within the wafer surface, a temperature distribution in the wafer surface where the temperature at the outer periphery of the wafer is lower than the temperature at the center of the wafer is desirable. It is desirable that the temperature at the outer periphery and the temperature at the center of the wafer have the same temperature distribution (see FIG. 1). As described above, the optimum conditions of the two qualities that prevent the uniformity of the resistivity within the wafer surface and the prevention of slipping are contradictory, making it difficult to achieve both.

  For example, Patent Document 1 relates to a method for growing a silicon epitaxial layer. As a method for eliminating auto-doping and slip at the same time, a slip-free temperature distribution is used, and the dopant concentration in the raw material gas on the wafer peripheral side and the central side is changed. How to do is described. However, in this method, the dopant concentration in the raw material gas has to be adjusted based on the mass flow rate of the dopant, and there is a problem that control is difficult.

  Further, for example, Patent Document 2 relates to a method for growing a silicon epitaxial layer. As a method for eliminating auto-doping and slip at the same time, heating is performed only with an upper lamp until the temperature of the substrate is raised, and then a lower RF coil is added. A method of heating is described. However, since this method is not a method based on the in-plane temperature distribution of the wafer, there is a possibility that variations occur and the yield deteriorates.

Japanese Patent Laid-Open No. 6-232060 JP-A-64-49217

  The present invention has been made in view of the above-mentioned problems of the prior art, and adjusts the resistivity distribution of the epitaxial film while improving the occurrence of slip by optimizing the temperature in the wafer surface during epitaxial growth. An object of the present invention is to provide a method for manufacturing a silicon epitaxial wafer.

  In order to achieve the above object, the present inventors have intensively studied, and as a result, the occurrence of slip is improved by assigning the optimum temperature distribution for slip and the optimum temperature distribution for resistivity distribution to separate processes in epitaxial growth. However, the inventors considered that the resistivity distribution of the epitaxial film could be adjusted, and reached the present invention.

The method for producing a silicon epitaxial wafer according to the present invention is a method for producing a silicon epitaxial wafer including at least a temperature raising step, a pre-bake step, and an epitaxial film forming step. Regarding the distribution, the temperature raising step and the pre-bake step are performed with a first wafer surface temperature distribution, the epitaxial film forming step is performed with a second wafer surface temperature distribution, and the second wafer surface temperature distribution is temperature of the wafer outer peripheral portion than the first wafer plane temperature distribution is a divorced epitaxial wafer manufacturing method of a low temperature distribution, and the definition of the wafer surface temperature distribution and as the following formula (1) When the first wafer in-plane temperature distribution is -0.5% to 0.5%, Eha plane temperature distribution is characterized by from 0.5% to 3.0%.
Wafer surface temperature distribution (%) = {temperature at the center of the wafer (° C.) − Temperature at a point 5 mm inside from the wafer periphery (° C.)} / Temperature at the center of the wafer (° C.) × 100 (%)... (1)

  The first wafer in-plane temperature distribution is preferably an optimum temperature distribution for preventing slip, and the second wafer in-plane temperature distribution is preferably an optimum temperature distribution for preventing auto-doping.

  Here, the wafer outer peripheral portion is preferably a portion inside 5 mm from the wafer outer periphery.

  According to the present invention, in each process of epitaxial growth, by optimizing the temperature distribution in the wafer surface, manufacturing of a silicon epitaxial wafer capable of adjusting the resistivity distribution of the epitaxial film while improving the occurrence of slipping is achieved. There is a remarkable effect that a method can be provided.

It is a graph which shows the relationship between the slip by the temperature distribution in a wafer surface, and the resistivity distribution of an epitaxial film. It is the schematic of a single wafer type vapor phase growth apparatus. It is a graph which shows the temperature profile of an epitaxial growth process. 3 is a graph showing the amount of slip generation in Example 1 and Comparative Example 1.

FIG. 1 shows the relationship between the slip due to the temperature distribution in the wafer surface and the resistivity distribution of the epitaxial film. In FIG. 1, the wafer surface temperature distribution is calculated from the following equation (1).
Wafer surface temperature distribution (%) = {temperature at the center of the wafer (° C.) − Temperature at a point 5 mm inside from the wafer periphery (° C.)} / Temperature at the center of the wafer (° C.) × 100 (%) (1)
When the definition of the temperature distribution in the wafer surface is as described above, the temperature distribution in the first wafer surface in the temperature raising step and the pre-bake step is -0.5% to 0.5%, The second wafer surface temperature distribution is preferably 0.5% to 3.0%.

  The slip is mainly generated from the contact point between the wafer supporting the wafer being heat-treated and the wafer, and is considered to occur particularly during the temperature rise. Therefore, by satisfying both qualities, the temperature rise process and pre-bake process before the epitaxial film formation process are set to “optimal temperature distribution for slip” and the epitaxial film formation process is set to “temperature distribution optimal for resistivity distribution”. I found that I can do it.

  Hereinafter, the present invention will be described with reference to examples. However, this invention is not limited to the aspect shown in the Example.

  FIG. 2 is a schematic view showing a single-wafer type vapor phase growth apparatus that can be used in the production method of the present invention. A chamber (reaction vessel) 12 of the vapor phase growth apparatus 10 shown in FIG. 2 is formed of a chamber base 11 and transparent quartz members 13 and 14 sandwiching the chamber base 11 from above and below.

  In the chamber 12, a susceptor 17 that supports the silicon single crystal substrate W with an upper wafer mounting surface (facing part) 19 is disposed. The susceptor 17 is provided with, for example, three or more through holes 16, and wafer lift pins 15 for placing and separating the silicon single crystal substrate W by being inserted into the through holes 16 and moving up and down are arranged. Yes.

  The susceptor 17 is connected to a wafer rotating mechanism 18. During the epitaxial growth, the susceptor 17 is rotated to rotate the placed silicon single crystal substrate W, and the silicon epitaxial layer is formed on the silicon single crystal substrate W. Grow uniformly. In the chamber 12, a vapor phase growth gas including a source gas and a carrier gas (for example, hydrogen) is introduced into the chamber 12, and a source gas and a gas are formed on the surface of the silicon single crystal substrate W placed on the susceptor 17. A gas introduction pipe 20 for supplying a carrier gas is connected. A gas discharge pipe 21 for discharging gas from the chamber 12 is connected to the opposite side of the chamber 12 to the side where the gas introduction pipe 20 is connected.

Example 1
A silicon substrate having a resistivity of 8.0 to 12.0 Ω · cm and a diameter of 200 mm containing boron as an impurity was prepared. An epitaxial film having an epi resistivity of 10.0 Ω · cm and an epi film thickness of 5 μm is grown on the silicon substrate using a growth temperature of 1150 ° C., a dopant gas of BH ₃ , and a film forming gas of trichlorosilane (TCS). An epitaxial wafer as a sample was manufactured by performing epitaxial growth (CVD method). At this time, the temperature distribution to the pre-bake process is “optimum temperature distribution for slip” (wafer surface temperature distribution = 0.3%), and the film formation process (wafer temperature = 1150 ° C.) is “optimal temperature distribution for resistivity distribution. (Wafer surface temperature distribution = 0.9%) (see FIG. 3). The amount of slip generated in the epitaxial wafer manufactured at this time was measured. FIG. 4 shows the result at that time.

  From FIG. 4, slipping occurs when the temperature distribution is changed to the optimum temperature distribution during the temperature rise, but the temperature distribution from the temperature rise to the pre-baking process is “optimal temperature distribution for slip”, and the film forming process is “resistivity”. It was confirmed that the slip was drastically improved by making the temperature distribution optimal for the distribution.

(Comparative Example 1)
A silicon substrate having a resistivity of 8.0 to 12.0 Ω · cm and a diameter of 200 mm containing boron as an impurity was prepared. An epitaxial film having an epi resistivity of 10.0 Ω · cm and an epi film thickness of 5 μm is grown on the silicon substrate using a growth temperature of 1150 ° C., a dopant gas of BH ₃ , and a film forming gas of trichlorosilane (TCS). An epitaxial wafer as a sample was manufactured by performing epitaxial growth (CVD method). At this time, the pre-bake process and the film-forming process are performed from the middle of the temperature rise to the middle of the temperature rise (wafer temperature = 1080 ° C.) with “temperature distribution optimum for slip” (wafer in-plane temperature distribution = 0.3%). Was “optimal temperature distribution for resistivity distribution” (temperature distribution in wafer surface = 0.9%) (see FIG. 3). The amount of slip generated in the epitaxial wafer manufactured at this time was measured. FIG. 4 shows the result at that time.

  Based on the above results, resistance is improved while improving slip by setting the temperature distribution during epitaxial growth to the pre-bake process as “optimal temperature distribution for slip” and the film formation step as “optimal temperature distribution for resistivity distribution”. It was shown that the rate distribution can be adjusted.

  The above-described embodiment is an exemplification, and the embodiment having substantially the same configuration as the technical idea described in the claims of the present invention and having the same function and effect is any type. Are also included in the technical scope of the present invention.

10: Vapor growth apparatus, 11: Chamber base, 12: Chamber, 13, 14: Transparent quartz member, 15: Wafer lift pin, 16: Through hole, 17: Susceptor, 18: Wafer rotation mechanism, 19: Wafer mounting surface , 20: gas introduction pipe, 21: gas discharge pipe, W: silicon single crystal substrate.

Claims (2)

In a method for producing a silicon epitaxial wafer including at least a temperature raising step, a pre-bake step, and an epitaxial film formation step,
Regarding the temperature distribution in the wafer surface indicated by the temperature difference between the central portion and the outer periphery of the wafer, the temperature raising step and the pre-baking step are performed with the first wafer surface temperature distribution, and the epitaxial film forming step is performed with the second wafer surface. With internal temperature distribution,
The second is in the wafer plane temperature distribution method for manufacturing a divorced epitaxial wafer temperature is low the temperature distribution of the wafer outer peripheral portion than said first wafer surface temperature distribution,
When the definition of the temperature distribution in the wafer surface is as shown in the following formula (1), the temperature distribution in the first wafer surface is −0.5% to 0.5%, and the second wafer surface The method for producing a silicon epitaxial wafer, wherein the internal temperature distribution is 0.5% to 3.0% .
Wafer surface temperature distribution (%) = {temperature at the center of the wafer (° C.) − Temperature at a point 5 mm inside from the wafer periphery (° C.)} / Temperature at the center of the wafer (° C.) × 100 (%)... (1)   The first wafer surface temperature distribution is an optimum temperature distribution for preventing slip, and the second wafer surface temperature distribution is an optimum temperature distribution for preventing autodoping. The method for producing a silicon epitaxial wafer according to claim 1.

Images