JP2017174902A5 - - Google Patents
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- Publication number
- JP2017174902A5 JP2017174902A5 JP2016057341A JP2016057341A JP2017174902A5 JP 2017174902 A5 JP2017174902 A5 JP 2017174902A5 JP 2016057341 A JP2016057341 A JP 2016057341A JP 2016057341 A JP2016057341 A JP 2016057341A JP 2017174902 A5 JP2017174902 A5 JP 2017174902A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- etching
- substrate
- semiconductor device
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 238000005530 etching Methods 0.000 claims 15
- 239000000758 substrate Substances 0.000 claims 11
- 238000004519 manufacturing process Methods 0.000 claims 10
- 239000004065 semiconductor Substances 0.000 claims 10
- 238000000034 method Methods 0.000 claims 5
- 238000011534 incubation Methods 0.000 claims 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 230000007723 transport mechanism Effects 0.000 claims 1
- 239000011800 void material Substances 0.000 claims 1
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016057341A JP6583081B2 (ja) | 2016-03-22 | 2016-03-22 | 半導体装置の製造方法 |
| KR1020170033034A KR102103625B1 (ko) | 2016-03-22 | 2017-03-16 | 반도체 장치의 제조 방법 및 반도체 장치의 제조 시스템 |
| TW106108647A TWI662607B (zh) | 2016-03-22 | 2017-03-16 | 半導體裝置之製造方法及半導體裝置之製造系統 |
| US15/465,144 US10297443B2 (en) | 2016-03-22 | 2017-03-21 | Semiconductor device manufacturing method and semiconductor device manufacturing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016057341A JP6583081B2 (ja) | 2016-03-22 | 2016-03-22 | 半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017174902A JP2017174902A (ja) | 2017-09-28 |
| JP2017174902A5 true JP2017174902A5 (cg-RX-API-DMAC7.html) | 2018-12-13 |
| JP6583081B2 JP6583081B2 (ja) | 2019-10-02 |
Family
ID=59896679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016057341A Active JP6583081B2 (ja) | 2016-03-22 | 2016-03-22 | 半導体装置の製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US10297443B2 (cg-RX-API-DMAC7.html) |
| JP (1) | JP6583081B2 (cg-RX-API-DMAC7.html) |
| KR (1) | KR102103625B1 (cg-RX-API-DMAC7.html) |
| TW (1) | TWI662607B (cg-RX-API-DMAC7.html) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10840205B2 (en) | 2017-09-24 | 2020-11-17 | Invensas Bonding Technologies, Inc. | Chemical mechanical polishing for hybrid bonding |
| US11056348B2 (en) | 2018-04-05 | 2021-07-06 | Invensas Bonding Technologies, Inc. | Bonding surfaces for microelectronics |
| JP7040257B2 (ja) * | 2018-04-25 | 2022-03-23 | 東京エレクトロン株式会社 | 成膜装置、及び成膜方法 |
| JP7004608B2 (ja) * | 2018-05-11 | 2022-01-21 | 東京エレクトロン株式会社 | 半導体膜の形成方法及び成膜装置 |
| US10741442B2 (en) | 2018-05-31 | 2020-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layer formation for conductive feature |
| US11011494B2 (en) | 2018-08-31 | 2021-05-18 | Invensas Bonding Technologies, Inc. | Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics |
| US10872788B2 (en) * | 2018-11-26 | 2020-12-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wet etch apparatus and method for using the same |
| CN110459464B (zh) * | 2019-08-14 | 2021-09-14 | 中国科学院微电子研究所 | 一种厚膜氮化硅的区域挖槽制备方法 |
| US11264357B1 (en) | 2020-10-20 | 2022-03-01 | Invensas Corporation | Mixed exposure for large die |
| KR20240128982A (ko) | 2022-01-06 | 2024-08-27 | 도쿄엘렉트론가부시키가이샤 | 판정 방법 및 기판 처리 장치 |
| CN116072606B (zh) * | 2023-02-08 | 2025-12-23 | 长鑫存储技术有限公司 | 一种半导体结构的制备方法及半导体结构 |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5654049A (en) * | 1979-10-09 | 1981-05-13 | Mitsubishi Electric Corp | Semiconductor device |
| JP2812599B2 (ja) * | 1992-02-06 | 1998-10-22 | シャープ株式会社 | 半導体装置の製造方法 |
| JPH07297182A (ja) * | 1994-04-27 | 1995-11-10 | Sony Corp | ＳｉＮ系絶縁膜の形成方法 |
| JP3660391B2 (ja) * | 1994-05-27 | 2005-06-15 | 株式会社東芝 | 半導体装置の製造方法 |
| US20010028922A1 (en) * | 1995-06-07 | 2001-10-11 | Sandhu Gurtej S. | High throughput ILD fill process for high aspect ratio gap fill |
| JP3402972B2 (ja) | 1996-11-14 | 2003-05-06 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
| US7115516B2 (en) * | 2001-10-09 | 2006-10-03 | Applied Materials, Inc. | Method of depositing a material layer |
| JP2003243537A (ja) * | 2002-02-18 | 2003-08-29 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| JP3759525B2 (ja) * | 2003-10-27 | 2006-03-29 | 松下電器産業株式会社 | 半導体装置の製造方法 |
| WO2005062390A1 (en) * | 2003-12-22 | 2005-07-07 | Showa Denko K.K. | Group iii nitride semiconductor device and light-emitting device using the same |
| US7482247B1 (en) * | 2004-12-30 | 2009-01-27 | Novellus Systems, Inc. | Conformal nanolaminate dielectric deposition and etch bag gap fill process |
| KR100711928B1 (ko) * | 2005-12-29 | 2007-04-27 | 동부일렉트로닉스 주식회사 | 반도체 장치의 금속 배선 및 그 형성 방법 |
| JP5550843B2 (ja) * | 2009-03-19 | 2014-07-16 | ラピスセミコンダクタ株式会社 | 半導体装置の製造方法 |
| US8742476B1 (en) * | 2012-11-27 | 2014-06-03 | Monolithic 3D Inc. | Semiconductor device and structure |
| JP5490753B2 (ja) * | 2010-07-29 | 2014-05-14 | 東京エレクトロン株式会社 | トレンチの埋め込み方法および成膜システム |
| JP5544343B2 (ja) * | 2010-10-29 | 2014-07-09 | 東京エレクトロン株式会社 | 成膜装置 |
| JP5599350B2 (ja) * | 2011-03-29 | 2014-10-01 | 東京エレクトロン株式会社 | 成膜装置及び成膜方法 |
| JP5829926B2 (ja) * | 2011-07-06 | 2015-12-09 | 東京エレクトロン株式会社 | タングステン膜の成膜方法 |
| JP5162016B1 (ja) * | 2011-09-15 | 2013-03-13 | 株式会社東芝 | 半導体素子、ウェーハ、半導体素子の製造方法及びウェーハの製造方法 |
| US9000557B2 (en) * | 2012-03-17 | 2015-04-07 | Zvi Or-Bach | Semiconductor device and structure |
| JP6468955B2 (ja) * | 2015-06-23 | 2019-02-13 | 東京エレクトロン株式会社 | シリコン含有膜の成膜方法及び成膜装置 |
-
2016
- 2016-03-22 JP JP2016057341A patent/JP6583081B2/ja active Active
-
2017
- 2017-03-16 TW TW106108647A patent/TWI662607B/zh active
- 2017-03-16 KR KR1020170033034A patent/KR102103625B1/ko active Active
- 2017-03-21 US US15/465,144 patent/US10297443B2/en active Active