JP2017139308A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2017139308A JP2017139308A JP2016018589A JP2016018589A JP2017139308A JP 2017139308 A JP2017139308 A JP 2017139308A JP 2016018589 A JP2016018589 A JP 2016018589A JP 2016018589 A JP2016018589 A JP 2016018589A JP 2017139308 A JP2017139308 A JP 2017139308A
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- Prior art keywords
- insulating film
- film
- gate electrode
- silicon nitride
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 297
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- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 2
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Abstract
【解決手段】低耐圧のMISFETQ2のゲート電極G2と、制御ゲート電極CGおよびメモリゲート電極MGを含むパターンとのそれぞれの側壁に、窒化シリコン膜NT3を介してサイドウォール状の酸化シリコン膜OX4を形成した後、ゲート電極G2の横の酸化シリコン膜OX3を除去し、続いて半導体基板SB上に酸化シリコン膜OX5を形成し、エッチバックを行う。これにより、ゲート電極G2の横に、窒化シリコン膜NT3および酸化シリコン膜OX5からなるサイドウォールSW1を形成し、上記パターンの横に、窒化シリコン膜NT3、酸化シリコン膜OX4およびOX5からなるサイドウォールSW2を形成する。
【選択図】図29
Description
本実施の形態の半導体装置は、不揮発性メモリ(不揮発性記憶素子、フラッシュメモリ、不揮発性半導体記憶装置)を備えた半導体装置である。本実施の形態および以下の実施の形態では、不揮発性メモリは、nチャネル型MISFETを基本としたメモリセルをもとに説明を行う。
以下では、本実施の形態の半導体装置の製造方法を、図1〜図28を用いて説明する。図1〜図28は、本実施の形態の半導体装置の製造工程中の断面図である。図1〜図4、図6〜図19では、図の左側から右側に向かって、順にロジック回路領域LP、ロジック回路領域LN、I/O領域HVおよびメモリセル領域HMの断面図を示している。これらの領域は、図において破線で区切られており、各領域は互いに離間している。ロジック回路領域LP、LN、I/O領域HVおよびメモリセル領域HMは、いずれも同じ半導体基板の主面に存在しており、当該主面に沿う方向において互いに並んでいる。図5は、図4の一部を拡大して示す断面図である。
次に、不揮発性メモリの動作例について、図30を参照して説明する。
以下に、図62〜図68を用いて比較例の半導体装置の問題点を説明し、図29などを用いて本実施の形態の半導体装置およびその製造方法の効果について説明する。図62〜図68は、比較例の半導体装置の製造工程中の断面図であり、図20〜図28と同様にロジック回路領域LNおよびメモリセルMCを示す断面図である。
以下に、本実施の形態の変形例1の半導体装置の製造工程について、図31〜図43を用いて説明する。図31〜図43は、本変形例の半導体装置の製造工程中の断面図である。図31〜図37は、図1と同様にロジック回路領域LP、LN、I/O領域HVおよびメモリセル領域HMを示す断面図である。図38〜図43は、図20と同様にロジック回路領域LNおよびメモリセル領域HMを示す断面図である。
以下に、本実施の形態の変形例2の半導体装置の製造工程について、図46〜図51を用いて説明する。図46〜図51は、本変形例の半導体装置の製造工程中の断面図である。図46〜図50は、図1と同様にロジック回路領域LP、LN、I/O領域HVおよびメモリセル領域HMを示す断面図である。図51は、図20と同様にロジック回路領域LNおよびメモリセル領域HMを示す断面図である。
以下に、本実施の形態2の半導体装置の製造方法について、図53〜図55を用いて説明する。ここでは、図34〜図37を用いて上述したオフセットスペーサを形成する第2の方法を用いる場合において、サイドウォールの一部である外側の部分を窒化シリコン膜により形成することについて説明する。図53〜図55では、図を分かりやすくするため、オフセットスペーサOS2を1つの膜として示す。本実施の形態と、前記実施の形態1の変形例1との主な違いは、酸化シリコン膜OX5(図23参照)の代わりに窒化シリコン膜を形成している点にある。
以下に、本実施の形態の変形例1の半導体装置の製造工程について、図58を用いて説明する。図58は、本変形例の半導体装置の製造工程中の断面図である。図58は、図20と同様にロジック回路領域LNおよびメモリセル領域HMを示す断面図である。
以下に、本実施の形態の変形例2の半導体装置の製造工程について、図60を用いて説明する。図60は、本変形例の半導体装置の製造工程中の断面図である。図60は、図20と同様にロジック回路領域LNおよびメモリセル領域HMを示す断面図である。
DF1〜DF4 拡散層
EX1〜EX4 エクステンション領域
G1〜G3 ゲート電極
GF1〜GF4 ゲート絶縁膜
HM メモリセル領域
LN、LP ロジック回路領域
MC メモリセル
MG メモリゲート電極
NT1〜NT8、NTA 窒化シリコン膜
ON ONO膜
OX1〜OX6、OXA 酸化シリコン膜
OS1〜OS4 オフセットスペーサ
Q2、Q3 MISFET
SB 半導体基板
SW1〜SW4、SWA、SWB サイドウォール
Claims (20)
- (a)半導体基板を用意する工程、
(b)第1領域の前記半導体基板上に、第1絶縁膜を介して第1ゲート電極を複数形成し、第2領域の前記半導体基板上に、第2絶縁膜を介して第2ゲート電極を形成する工程、
(c)複数の前記第1ゲート電極と、前記第2ゲート電極とを覆う第3絶縁膜および第4絶縁膜を順に前記半導体基板上に形成する工程、
(d)エッチバックにより前記第4絶縁膜の一部を除去することで前記第3絶縁膜の上面を前記第4絶縁膜から露出させ、複数の前記第1ゲート電極と、前記第2ゲート電極とのそれぞれの側壁を覆う前記第4絶縁膜を残す工程、
(e)前記(d)工程の後、複数の前記第1ゲート電極のそれぞれの前記側壁を覆う前記第4絶縁膜を除去する工程、
(f)前記(e)工程の後、複数の前記第1ゲート電極と、前記第2ゲート電極と、前記第2領域の前記第4絶縁膜とを覆う第5絶縁膜を前記半導体基板上に形成する工程、
(g)エッチバックにより前記第5絶縁膜および前記第3絶縁膜のそれぞれの一部を除去することで、前記第3絶縁膜から前記半導体基板を露出させ、これにより、前記第1領域の前記第3絶縁膜および前記第5絶縁膜を含む第1サイドウォールと、前記第2領域の前記第3絶縁膜、前記第4絶縁膜および前記第5絶縁膜を含む第2サイドウォールとを形成する工程、
(h)前記第1領域の前記半導体基板の主面に、前記第1サイドウォールをマスクとして用いてイオン注入を行うことで第1ソース・ドレイン領域を形成し、これにより前記第1ソース・ドレイン領域および前記第1ゲート電極を含む第1トランジスタを形成する工程、
(i)前記第2領域の前記半導体基板の前記主面に、前記第2サイドウォールをマスクとして用いてイオン注入を行うことで第2ソース・ドレイン領域を形成し、これにより前記第2ソース・ドレイン領域および前記第2ゲート電極を含む第2トランジスタを形成する工程、
を有し、
前記第1トランジスタは、前記第2トランジスタよりも低い電圧で駆動する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
隣り合う前記第1ゲート電極同士の相互間の距離は、前記第3絶縁膜および前記第4絶縁膜の合計の膜厚の2倍よりも大きい、半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記半導体基板の前記主面に沿う方向における前記第2サイドウォールの幅の大きさは、隣り合う前記第1ゲート電極同士の相互間の距離の半分以上である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(b)工程では、前記第1絶縁膜、前記第2絶縁膜、複数の前記第1ゲート電極および前記第2ゲート電極を形成し、前記第2領域の前記半導体基板上に、電荷蓄積膜を含む第3絶縁膜を介して第3ゲート電極を形成し、
前記第2ゲート電極と前記第3ゲート電極とは、前記第3絶縁膜を介して隣接し、
前記(c)工程では、前記第3ゲート電極を覆う前記第3絶縁膜および前記第4絶縁膜を形成し、
前記(d)工程では、前記第4絶縁膜の一部を除去することで、複数の前記第1ゲート電極のそれぞれの前記側壁と、前記第2ゲート電極の一方の前記側壁とのそれぞれを覆う前記第4絶縁膜を残し、前記第2ゲート電極の他方の前記側壁を、前記第3ゲート電極を介して覆う前記第4絶縁膜を残し、
前記(f)工程では、前記第3ゲート電極を覆う前記第5絶縁膜を形成し、
前記(i)工程では、前記第2トランジスタと、前記第2ソース・ドレイン領域および前記第3ゲート電極を含む第3トランジスタとを形成し、
前記第2トランジスタおよび前記第3トランジスタは、メモリセルを構成する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第3絶縁膜は、窒化シリコン膜であり、前記第4絶縁膜および前記第5絶縁膜は、酸化シリコン膜である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第3絶縁膜および前記第5絶縁膜は、窒化シリコン膜であり、前記第4絶縁膜は、酸化シリコン膜である、半導体装置の製造方法。 - 請求項4記載の半導体装置の製造方法において、
(b1)前記(b)工程の後、複数の前記第1ゲート電極と、前記第2ゲート電極とを覆う第1酸化シリコン膜および第1窒化シリコン膜を前記半導体基板上に順に形成する工程、
(b2)前記(c)工程の前に、エッチバックにより前記第1窒化シリコン膜の一部を除去することで、前記第1酸化シリコン膜を露出させ、これにより、複数の前記第1ゲート電極と、前記第2ゲート電極とのそれぞれの前記側壁を覆う前記第1酸化シリコン膜および前記第1窒化シリコン膜を含む第1オフセットスペーサを形成する工程、
をさらに有する、半導体装置の製造方法。 - 請求項4記載の半導体装置の製造方法において、
(b3)前記(b)工程の後、複数の前記第1ゲート電極および前記第2ゲート電極のそれぞれの前記側壁を覆うサイドウォール状の第2酸化シリコン膜を形成する工程、
(b4)前記複数の前記第1ゲート電極のそれぞれの前記側壁を覆う前記第2酸化シリコン膜を除去する工程、
(b5)前記(b4)工程の後、複数の前記第1ゲート電極、前記第2ゲート電極および前記第2酸化シリコン膜を覆う第2窒化シリコン膜および第3窒化シリコン膜を前記半導体基板上に順に形成する工程、
(b6)前記(c)工程の前に、エッチバックにより前記第3窒化シリコン膜および前記第2窒化シリコン膜のそれぞれの一部を除去することで、前記第2窒化シリコン膜から前記半導体基板を露出させ、これにより、複数の前記第1ゲート電極のそれぞれの前記側壁を覆う前記第2窒化シリコン膜および前記第3窒化シリコン膜を含む第2オフセットスペーサと、前記第2ゲート電極の前記側壁を覆う前記第2酸化シリコン膜、前記第2窒化シリコン膜および前記第3窒化シリコン膜を含む第3オフセットスペーサとを形成する工程、
をさらに有する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第1絶縁膜は、窒化シリコンより高い誘電率を有し、または、前記第1ゲート電極は、金属を含む、半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記第3絶縁膜および前記第5絶縁膜は、窒化シリコン膜であり、前記第4絶縁膜は、酸化シリコン膜である、半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
(b7)前記(b)工程の後、複数の前記第1ゲート電極と、前記第2ゲート電極とを覆う第4窒化シリコン膜および第5窒化シリコン膜を前記半導体基板上に順に形成する工程、
(b8)前記(c)工程の前に、エッチバックにより前記第5窒化シリコン膜および前記第4窒化シリコン膜のそれぞれの一部を除去することで、前記半導体基板を前記4窒化シリコン膜から露出させ、これにより、複数の前記第1ゲート電極と、前記第2ゲート電極とのそれぞれの前記側壁を覆う前記第4窒化シリコン膜および前記第5窒化シリコン膜を含む第4オフセットスペーサを形成する工程、
をさらに有する、半導体装置の製造方法。 - (a)半導体基板を用意する工程、
(b)第1領域の前記半導体基板上に、第1絶縁膜を介してダミーゲート電極を複数形成し、第2領域の前記半導体基板上に、第2絶縁膜を介して第1ゲート電極を形成する工程、
(c)複数の前記ダミーゲート電極と、前記第1ゲート電極とを覆う第3絶縁膜および第4絶縁膜を順に前記半導体基板上に形成する工程、
(d)エッチバックにより前記第4絶縁膜の一部を除去することで前記第3絶縁膜の上面を前記第4絶縁膜から露出させ、複数の前記ダミーゲート電極と、前記第1ゲート電極とのそれぞれの側壁を覆う前記第4絶縁膜を残す工程、
(e)前記(d)工程の後、複数の前記ダミーゲート電極のそれぞれの前記側壁を覆う前記第4絶縁膜を除去する工程、
(f)前記(e)工程の後、複数の前記ダミーゲート電極と、前記第1ゲート電極と、前記第2領域の前記第4絶縁膜とを覆う第5絶縁膜を前記半導体基板上に形成する工程、
(g)エッチバックにより前記第5絶縁膜および前記第3絶縁膜のそれぞれの一部を除去することで、前記第3絶縁膜から前記半導体基板を露出させ、これにより、前記第1領域の前記第3絶縁膜および前記第5絶縁膜を含む第1サイドウォールと、前記第2領域の前記第3絶縁膜、前記第4絶縁膜および前記第5絶縁膜を含む第2サイドウォールとを形成する工程、
(h)前記第1領域の前記半導体基板の主面に、前記第1サイドウォールをマスクとして用いてイオン注入を行うことで第1ソース・ドレイン領域を形成する工程、
(i)前記第2領域の前記半導体基板の前記主面に、前記第2サイドウォールをマスクとして用いてイオン注入を行うことで第2ソース・ドレイン領域を形成し、これにより前記第2ソース・ドレイン領域および前記第1ゲート電極を含む第1トランジスタを形成する工程、
(j)前記(i)工程の後、複数の前記ダミーゲート電極および前記第1ゲート電極を覆う層間絶縁膜を形成した後、前記層間絶縁膜の上面を研磨することで、前記ダミーゲート電極を露出させる工程、
(k)前記(j)工程の後、前記ダミーゲート電極を除去することで溝を形成する工程、
(l)前記溝内に金属を含む第2ゲート電極を形成することで、前記第1ソース・ドレイン領域および前記第2ゲート電極を含む第2トランジスタを形成する工程、
を有し、
前記第2トランジスタは、前記第1トランジスタよりも低い電圧で駆動する、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
隣り合う前記ダミーゲート電極同士の相互間の距離は、前記第3絶縁膜および前記第4絶縁膜の合計の膜厚の2倍よりも大きい、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記半導体基板の前記主面に沿う方向における前記第2サイドウォールの幅の大きさは、隣り合う前記ダミーゲート電極同士の相互間の距離の半分以上である、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記(b)工程では、前記第1絶縁膜、前記第2絶縁膜、複数の前記ダミーゲート電極および前記第1ゲート電極を形成し、前記第2領域の前記半導体基板上に、電荷蓄積膜を含む前記第3絶縁膜を介して第3ゲート電極を形成し、
前記第1ゲート電極と前記第3ゲート電極とは、前記第3絶縁膜を介して隣接し、
前記(c)工程では、前記第3ゲート電極を覆う前記第3絶縁膜および前記第4絶縁膜を形成し、
前記(d)工程では、前記第4絶縁膜の一部を除去することで、複数の前記ダミーゲート電極のそれぞれの前記側壁と、前記第1ゲート電極の一方の前記側壁とのそれぞれを覆う前記第4絶縁膜を残し、前記第1ゲート電極の他方の前記側壁を、前記第3ゲート電極を介して覆う前記第4絶縁膜を残し、
前記(f)工程では、前記第3ゲート電極を覆う前記第5絶縁膜を形成し、
前記(i)工程では、前記第1トランジスタと、前記第2ソース・ドレイン領域および前記第3ゲート電極を含む第3トランジスタとを形成し、
前記第1トランジスタおよび前記第3トランジスタは、メモリセルを構成する、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記第3絶縁膜は、窒化シリコン膜であり、前記第4絶縁膜および前記第5絶縁膜は、酸化シリコン膜である、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記第3絶縁膜および前記第5絶縁膜は、窒化シリコン膜であり、前記第4絶縁膜は、酸化シリコン膜である、半導体装置の製造方法。 - 請求項15記載の半導体装置の製造方法において、
(b1)前記(b)工程の後、複数の前記ダミーゲート電極と、前記第1ゲート電極とを覆う第1酸化シリコン膜および第1窒化シリコン膜を前記半導体基板上に順に形成する工程、
(b2)前記(c)工程の前に、エッチバックにより前記第1窒化シリコン膜の一部を除去することで、前記第1酸化シリコン膜を露出させ、これにより、複数の前記ダミーゲート電極と、前記第1ゲート電極とのそれぞれの前記側壁を覆う前記第1酸化シリコン膜および前記第1窒化シリコン膜を含む第1オフセットスペーサを形成する工程、
をさらに有する、半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法において、
(b3)前記(b)工程の後、複数の前記ダミーゲート電極と、前記第1ゲート電極とを覆う第2窒化シリコン膜および第3窒化シリコン膜を前記半導体基板上に順に形成する工程、
(b4)前記(c)工程の前に、エッチバックにより前記第3窒化シリコン膜および前記第2窒化シリコン膜のそれぞれの一部を除去することで、前記半導体基板を前記2窒化シリコン膜から露出させ、これにより、複数の前記ダミーゲート電極と、前記第1ゲート電極とのそれぞれの前記側壁を覆う前記第2窒化シリコン膜および前記第3窒化シリコン膜を含む第2オフセットスペーサを形成する工程、
をさらに有する、半導体装置の製造方法。 - 半導体基板と、
第1領域の前記半導体基板上に第1絶縁膜を介して形成された第1ゲート電極と、
第2領域の前記半導体基板上に第2絶縁膜を介して形成された第2ゲート電極と、
前記第2領域の前記半導体基板上に、電荷蓄積膜を含む第3絶縁膜を介して形成され、前記第2ゲート電極の一方の側壁に前記第3絶縁膜を介して隣接する第3ゲート電極と、
前記第1ゲート電極の側壁を覆う第1窒化シリコン膜を含む第1オフセットスペーサと、
前記第2ゲート電極、前記第3絶縁膜および前記第3ゲート電極を含むパターンの側壁を順に覆う酸化シリコン膜および第2窒化シリコン膜を含む第2オフセットスペーサと、
前記第1ゲート電極の側壁を、前記第1オフセットスペーサを介して覆う第3窒化シリコン膜を含む第1サイドウォールと、
前記パターンの側壁を、前記第2オフセットスペーサを介して覆う第4窒化シリコン膜を含む第2サイドウォールと、
前記第1領域の前記半導体基板の主面に形成された第1ソース・ドレイン領域と、
前記第2領域の前記半導体基板の主面に形成された第2ソース・ドレイン領域と、
を有し、
前記第1ゲート電極および前記第1ソース・ドレイン領域は、トランジスタを構成し、
前記第2ゲート電極、前記第3ゲート電極、前記第3絶縁膜および前記第2ソース・ドレイン領域は、メモリセルを構成し、
前記半導体基板の主面に沿う方向において、前記第1サイドウォールの幅は、前記第2サイドウォールの幅よりも小さく、
前記電荷蓄積膜の側壁は、前記酸化シリコン膜に接し、
前記第1絶縁膜は、窒化シリコンより高い誘電率を有し、または、前記第1ゲート電極は、金属を含む、半導体装置。
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JP5013050B2 (ja) * | 2006-06-14 | 2012-08-29 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
KR20120102932A (ko) * | 2011-03-09 | 2012-09-19 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 제조방법 |
JP6045873B2 (ja) | 2012-10-05 | 2016-12-14 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2014204041A (ja) * | 2013-04-08 | 2014-10-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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US9536890B2 (en) * | 2015-04-01 | 2017-01-03 | Powerchip Technology Corporation | Semiconductor transistor and flash memory, and manufacturing method thereof |
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2016
- 2016-02-03 JP JP2016018589A patent/JP6683488B2/ja active Active
- 2016-11-08 TW TW105136178A patent/TW201801253A/zh unknown
- 2016-11-24 CN CN201611045583.5A patent/CN107039454B/zh active Active
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2017
- 2017-01-23 US US15/412,465 patent/US9837427B2/en active Active
- 2017-02-01 KR KR1020170014528A patent/KR20170092465A/ko unknown
- 2017-10-30 US US15/797,637 patent/US20180047746A1/en not_active Abandoned
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US20080296637A1 (en) * | 2007-06-01 | 2008-12-04 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP2012248722A (ja) * | 2011-05-30 | 2012-12-13 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP2013098192A (ja) * | 2011-10-28 | 2013-05-20 | Renesas Electronics Corp | 半導体装置の製造方法および半導体装置 |
JP2014165299A (ja) * | 2013-02-25 | 2014-09-08 | Renesas Electronics Corp | 半導体装置の製造方法および半導体装置 |
JP2015162621A (ja) * | 2014-02-28 | 2015-09-07 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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TW201801253A (zh) | 2018-01-01 |
CN107039454A (zh) | 2017-08-11 |
JP6683488B2 (ja) | 2020-04-22 |
KR20170092465A (ko) | 2017-08-11 |
US9837427B2 (en) | 2017-12-05 |
US20170221917A1 (en) | 2017-08-03 |
US20180047746A1 (en) | 2018-02-15 |
CN107039454B (zh) | 2021-12-10 |
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