JP2017050526A5 - - Google Patents

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JP2017050526A5
JP2017050526A5 JP2016097400A JP2016097400A JP2017050526A5 JP 2017050526 A5 JP2017050526 A5 JP 2017050526A5 JP 2016097400 A JP2016097400 A JP 2016097400A JP 2016097400 A JP2016097400 A JP 2016097400A JP 2017050526 A5 JP2017050526 A5 JP 2017050526A5
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layer
channel
channel layer
memory device
stack
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JP2016097400A
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JP2017050526A (ja
JP6669581B2 (ja
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JP2016097400A 2015-08-31 2016-05-13 多層チャネル及び電荷トラップ層を有するメモリデバイス Active JP6669581B2 (ja)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201562212315P 2015-08-31 2015-08-31
US62/212,315 2015-08-31
US201662279068P 2016-01-15 2016-01-15
US62/279,068 2016-01-15
US15/078,156 US10020317B2 (en) 2015-08-31 2016-03-23 Memory device with multi-layer channel and charge trapping layer
US15/078,156 2016-03-23

Publications (3)

Publication Number Publication Date
JP2017050526A JP2017050526A (ja) 2017-03-09
JP2017050526A5 true JP2017050526A5 (https=) 2019-01-31
JP6669581B2 JP6669581B2 (ja) 2020-03-18

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JP2016097400A Active JP6669581B2 (ja) 2015-08-31 2016-05-13 多層チャネル及び電荷トラップ層を有するメモリデバイス

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US (1) US10020317B2 (https=)
JP (1) JP6669581B2 (https=)
KR (1) KR102250029B1 (https=)
WO (1) WO2017039784A1 (https=)

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