JP6669581B2 - 多層チャネル及び電荷トラップ層を有するメモリデバイス - Google Patents

多層チャネル及び電荷トラップ層を有するメモリデバイス Download PDF

Info

Publication number
JP6669581B2
JP6669581B2 JP2016097400A JP2016097400A JP6669581B2 JP 6669581 B2 JP6669581 B2 JP 6669581B2 JP 2016097400 A JP2016097400 A JP 2016097400A JP 2016097400 A JP2016097400 A JP 2016097400A JP 6669581 B2 JP6669581 B2 JP 6669581B2
Authority
JP
Japan
Prior art keywords
layer
channel layer
channel
stack
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016097400A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017050526A (ja
JP2017050526A5 (https=
Inventor
チャン レンホワ
チャン レンホワ
ラムクマール クリシュナスワミ
ラムクマール クリシュナスワミ
林志 杉野
林志 杉野
シュエ レー
シュエ レー
Original Assignee
ロンギチュード フラッシュ メモリー ソリューションズ リミテッド
ロンギチュード フラッシュ メモリー ソリューションズ リミテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ロンギチュード フラッシュ メモリー ソリューションズ リミテッド, ロンギチュード フラッシュ メモリー ソリューションズ リミテッド filed Critical ロンギチュード フラッシュ メモリー ソリューションズ リミテッド
Publication of JP2017050526A publication Critical patent/JP2017050526A/ja
Publication of JP2017050526A5 publication Critical patent/JP2017050526A5/ja
Application granted granted Critical
Publication of JP6669581B2 publication Critical patent/JP6669581B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292—Non-planar channels of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
JP2016097400A 2015-08-31 2016-05-13 多層チャネル及び電荷トラップ層を有するメモリデバイス Active JP6669581B2 (ja)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201562212315P 2015-08-31 2015-08-31
US62/212,315 2015-08-31
US201662279068P 2016-01-15 2016-01-15
US62/279,068 2016-01-15
US15/078,156 US10020317B2 (en) 2015-08-31 2016-03-23 Memory device with multi-layer channel and charge trapping layer
US15/078,156 2016-03-23

Publications (3)

Publication Number Publication Date
JP2017050526A JP2017050526A (ja) 2017-03-09
JP2017050526A5 JP2017050526A5 (https=) 2019-01-31
JP6669581B2 true JP6669581B2 (ja) 2020-03-18

Family

ID=58187821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016097400A Active JP6669581B2 (ja) 2015-08-31 2016-05-13 多層チャネル及び電荷トラップ層を有するメモリデバイス

Country Status (4)

Country Link
US (1) US10020317B2 (https=)
JP (1) JP6669581B2 (https=)
KR (1) KR102250029B1 (https=)
WO (1) WO2017039784A1 (https=)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9430735B1 (en) 2012-02-23 2016-08-30 Micron Technology, Inc. Neural network in a memory device
US10134752B2 (en) 2016-06-22 2018-11-20 Samsung Electronics Co., Ltd. Memory device
US10269824B2 (en) * 2017-04-01 2019-04-23 Intel Corporation Non-volatile memory structures having multi-layer conductive channels
EP3580782A4 (en) 2017-08-21 2020-12-02 Yangtze Memory Technologies Co., Ltd. STABLE THREE-DIMENSIONAL MEMORY DEVICES AND THEIR TRAINING PROCESSES
CN107527919A (zh) * 2017-08-31 2017-12-29 长江存储科技有限责任公司 一种3d nand存储器件及其制造方法
CN107658317B (zh) * 2017-09-15 2019-01-01 长江存储科技有限责任公司 一种半导体装置及其制备方法
US10283452B2 (en) 2017-09-15 2019-05-07 Yangtze Memory Technology Co., Ltd. Three-dimensional memory devices having a plurality of NAND strings
CN109698162A (zh) * 2017-10-20 2019-04-30 萨摩亚商费洛储存科技股份有限公司 三维存储元件及其制造方法
US10283513B1 (en) * 2017-11-06 2019-05-07 Sandisk Technologies Llc Three-dimensional memory device with annular blocking dielectrics and method of making thereof
US10957392B2 (en) * 2018-01-17 2021-03-23 Macronix International Co., Ltd. 2D and 3D sum-of-products array for neuromorphic computing system
US11138497B2 (en) 2018-07-17 2021-10-05 Macronix International Co., Ltd In-memory computing devices for neural networks
US10629608B2 (en) * 2018-09-26 2020-04-21 Macronix International Co., Ltd. 3D vertical channel tri-gate NAND memory with tilted hemi-cylindrical structure
CN111341787B (zh) * 2018-10-08 2021-08-27 长江存储科技有限责任公司 利用自然氧化层形成具有沟道结构的三维存储器件的方法
US11636325B2 (en) 2018-10-24 2023-04-25 Macronix International Co., Ltd. In-memory data pooling for machine learning
KR102670089B1 (ko) * 2018-10-26 2024-05-28 삼성전자주식회사 3차원 반도체 메모리 장치
CN109473431A (zh) * 2018-11-13 2019-03-15 中国科学院微电子研究所 一种三维铁电存储器及其制作方法
US11562229B2 (en) 2018-11-30 2023-01-24 Macronix International Co., Ltd. Convolution accelerator using in-memory computation
US11934480B2 (en) 2018-12-18 2024-03-19 Macronix International Co., Ltd. NAND block architecture for in-memory multiply-and-accumulate operations
KR102681258B1 (ko) * 2018-12-27 2024-07-03 에스케이하이닉스 주식회사 복수의 채널층을 구비하는 비휘발성 메모리 장치
US11119674B2 (en) 2019-02-19 2021-09-14 Macronix International Co., Ltd. Memory devices and methods for operating the same
JP2020141008A (ja) * 2019-02-27 2020-09-03 キオクシア株式会社 半導体記憶装置及びその製造方法
US11132176B2 (en) 2019-03-20 2021-09-28 Macronix International Co., Ltd. Non-volatile computing method in flash memory
CN110299362A (zh) * 2019-07-16 2019-10-01 中国科学院微电子研究所 一种3d nand存储器及其制备方法
KR102757200B1 (ko) 2020-04-17 2025-01-20 에스케이하이닉스 주식회사 반도체 메모리 장치
US11562909B2 (en) * 2020-05-22 2023-01-24 Applied Materials, Inc. Directional selective junction clean with field polymer protections
JP2022039622A (ja) * 2020-08-28 2022-03-10 キオクシア株式会社 半導体記憶装置、および半導体記憶装置の製造方法
KR102862952B1 (ko) * 2021-01-07 2025-09-22 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 제조 방법
KR102666996B1 (ko) * 2021-03-26 2024-05-17 한양대학교 산학협력단 다층막 구조의 채널층을 포함하는 3차원 플래시 메모리 및 그 제조 방법
US20240057327A1 (en) * 2021-01-11 2024-02-15 Iucf-Hyu (Industry University Cooperation Foundation Hanyang University) Three-dimensional flash memory including channel layer having multilayer structure, and method for manufacturing same
US12462873B2 (en) * 2021-06-03 2025-11-04 Sunrise Memory Corporation Thin film storage transistor with silicon oxide nitride charge trapping layer
US11877446B2 (en) * 2021-06-11 2024-01-16 Sandisk Technologies Llc Three-dimensional memory device with electrically conductive layers containing vertical tubular liners and methods for forming the same
US12137565B2 (en) 2021-06-11 2024-11-05 Sandisk Technologies Llc Three-dimensional memory device with vertical word line barrier and methods for forming the same
US12299597B2 (en) 2021-08-27 2025-05-13 Macronix International Co., Ltd. Reconfigurable AI system
KR102919913B1 (ko) * 2021-09-08 2026-01-30 삼성전자주식회사 3차원 반도체 메모리 장치, 이의 제조 방법 및 이를 포함하는 전자 시스템
US20230320090A1 (en) * 2022-04-01 2023-10-05 Micron Technology, Inc. Nand pillar memory device and method
US12408342B2 (en) * 2022-06-10 2025-09-02 Macronix International Co., Ltd. Memory device with multi-layered charge storage stack
US12232324B2 (en) * 2022-09-27 2025-02-18 Infineon Technologies LLC Method of forming oxide-nitride-oxide stack of non-volatile memory and integration to CMOS process flow
US12321603B2 (en) 2023-02-22 2025-06-03 Macronix International Co., Ltd. High bandwidth non-volatile memory for AI inference system
US12536404B2 (en) 2023-02-22 2026-01-27 Macronix International Co., Ltd. Data optimization for high bandwidth (HBW) NVM AI inference system
US12585931B2 (en) * 2023-05-04 2026-03-24 Macronix International Co., Ltd. 3D hybrid bonding 3D memory devices with NPU/CPU for AI inference application
US12417170B2 (en) 2023-05-10 2025-09-16 Macronix International Co., Ltd. Computing system and method of operation thereof

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001338988A (ja) 2000-05-25 2001-12-07 Hitachi Ltd 半導体装置及びその製造方法
US6313487B1 (en) 2000-06-15 2001-11-06 Board Of Regents, The University Of Texas System Vertical channel floating gate transistor having silicon germanium channel layer
US6544854B1 (en) 2000-11-28 2003-04-08 Lsi Logic Corporation Silicon germanium CMOS channel
US6709935B1 (en) 2001-03-26 2004-03-23 Advanced Micro Devices, Inc. Method of locally forming a silicon/geranium channel layer
US7274068B2 (en) 2004-05-06 2007-09-25 Micron Technology, Inc. Ballistic direct injection NROM cell on strained silicon structures
US8592891B1 (en) * 2007-05-25 2013-11-26 Cypress Semiconductor Corp. Methods for fabricating semiconductor memory with process induced strain
JP2011023705A (ja) * 2009-06-18 2011-02-03 Toshiba Corp 不揮発性半導体記憶装置
US8592873B2 (en) * 2010-06-24 2013-11-26 Samsung Electronics Co., Ltd. Semiconductor memory devices and methods of forming the same
US8928061B2 (en) * 2010-06-30 2015-01-06 SanDisk Technologies, Inc. Three dimensional NAND device with silicide containing floating gates
KR20130070158A (ko) * 2011-12-19 2013-06-27 에스케이하이닉스 주식회사 3차원 비휘발성 메모리 소자, 메모리 시스템 및 그 제조 방법
US8828851B2 (en) * 2012-02-01 2014-09-09 Stmicroeletronics, Inc. Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering
JP2013201270A (ja) 2012-03-23 2013-10-03 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
JP6328607B2 (ja) * 2012-03-29 2018-05-23 サイプレス セミコンダクター コーポレーション ロジックｃｍｏｓフローへのｏｎｏ統合の方法
KR20130117130A (ko) * 2012-04-17 2013-10-25 삼성전자주식회사 비휘발성 메모리 소자의 게이트 구조물
CN104769724B (zh) * 2012-07-01 2018-09-18 赛普拉斯半导体公司 具有多个电荷存储层的存储器晶体管
KR102003526B1 (ko) * 2012-07-31 2019-07-25 삼성전자주식회사 반도체 메모리 소자 및 그 제조방법
US8946023B2 (en) * 2013-03-12 2015-02-03 Sandisk Technologies Inc. Method of making a vertical NAND device using sequential etching of multilayer stacks
KR20150020845A (ko) * 2013-08-19 2015-02-27 에스케이하이닉스 주식회사 수직 채널을 갖는 반도체 장치, 그를 포함하는 저항 변화 메모리 장치 및 그 제조방법
US9460931B2 (en) * 2013-09-17 2016-10-04 Sandisk Technologies Llc High aspect ratio memory hole channel contact formation
KR102101841B1 (ko) * 2013-10-28 2020-04-17 삼성전자 주식회사 수직형 비휘발성 메모리 소자
US9425257B2 (en) 2013-11-20 2016-08-23 Taiwan Semiconductor Manufacturing Company Limited Non-planar SiGe channel PFET
KR20150070819A (ko) * 2013-12-17 2015-06-25 에스케이하이닉스 주식회사 반도체 메모리 소자 및 그 제조방법

Also Published As

Publication number Publication date
KR102250029B1 (ko) 2021-05-10
US10020317B2 (en) 2018-07-10
JP2017050526A (ja) 2017-03-09
WO2017039784A1 (en) 2017-03-09
KR20170026101A (ko) 2017-03-08
US20170263623A1 (en) 2017-09-14

Similar Documents

Publication Publication Date Title
JP6669581B2 (ja) 多層チャネル及び電荷トラップ層を有するメモリデバイス
US20180323208A1 (en) Vertical division of three-dimensional memory device
US9230980B2 (en) Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device
US9099496B2 (en) Method of forming an active area with floating gate negative offset profile in FG NAND memory
US8617947B2 (en) Method of manufacturing semiconductor device
US9780108B2 (en) Ultrathin semiconductor channel three-dimensional memory devices
US9876025B2 (en) Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices
US8884357B2 (en) Vertical NAND and method of making thereof using sequential stack etching and landing pad
US20190123060A1 (en) Transistor, Semiconductor Device, Memory Device and Fabrication the Same
US9741803B2 (en) Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
CN110010613A (zh) 三维半导体存储器件及其制造方法
US20150318300A1 (en) Method of making damascene select gate in memory device
CN204130535U (zh) 一种非易失性三维半导体存储器
CN109473442B (zh) 半导体器件沟道层的制备方法及半导体器件沟道层
US7705390B2 (en) Dual bit flash memory devices and methods for fabricating the same
US20190319104A1 (en) Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
US9224748B2 (en) Method of forming spaced-apart charge trapping stacks
TW201419419A (zh) 用於製造非揮發性電荷捕獲記憶體元件之基氧化方法
WO2011024213A1 (ja) 不揮発性半導体記憶装置
US20150179818A1 (en) Method of manufacturing nonvolatile semiconductor storage device and nonvolatile semiconductor storage device
US20170069762A1 (en) Memory device and method for fabricating the same

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20181210

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20181210

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20181210

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20190312

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190320

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190409

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20190628

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20190709

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190821

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20191029

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200110

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200128

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200227

R150 Certificate of patent or registration of utility model

Ref document number: 6669581

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250