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  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
  • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
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  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
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  • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
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  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
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Definitions

• the present disclosure relates generally to non-volatile (NV) memory devices, and more particularly to three-dimensional (3-D) or vertical NV memory cell strings and methods of manufacturing thereof including forming multiple layer channel and/or charge trapping layer.
• NV non-volatile
• Flash memory both the NAND and NOR types, includes strings of NV memory elements or cells, such as floating-gate metal-oxide-semiconductor field-effect (FGMOS) transistors and silicon-oxide-nitride-oxide- silicon (SONOS) transistors.
• FGMOS floating-gate metal-oxide-semiconductor field-effect
• SONOS silicon-oxide-nitride-oxide- silicon
• any small imperfection in the fabrication process may cause logic/memory states of the NV memory elements to become difficult to differentiate, which may result in a false reading of logic states.
• control electrodes are getting so small and closely spaced that their effects, such as in biasing gates, may spread over more than one memory cells or strings, which may lead to unreliable reading and writing of data.
• NV memory cell strings are oriented vertically and NV memory cells are stacked on a semiconductor substrate. Accordingly, memory bit density is much enhanced compared to the two-dimensional (2-D) geometry having a similar footprint on the substrate.
• channels are disposed inside openings formed in a dielectric/gate stack on a substrate.
• channels are mainly composed of polycrystalline silicon (Poly-Si), allowing electric current (charge carriers) to flow along the channels.
• Poly-Si channels may include silicon crystals of small grain sizes, contributing to more severe potential defects such as grain boundaries. Defects such as grain boundaries may cause charge carriers to scatter. As a result, the current flowing along channels may be reduced significantly.
• 3-D memory cell strings, such as 3-D NAND the reduction in reading current may affect the margin for read operations adversely.
• the number of layers in the dielectric/gate stack will be restricted, which in turn limit the number of memory cells (FGMOS, SONOS, etc.) in one NV memory string.
• FIG. 1 is a flowchart illustrating an embodiment of a method for fabricating a vertical NV memory device including strings of NV memory cells
• FIGS. 2A and 2B are representative diagrams illustrating isometric views of a portion of a vertical NV memory device during fabrication according to the method of FIG. 1;
• FIG. 2C is a representative cross-sectional view of a portion of a vertical NV memory array
• FIGS. 2D to 2U are representative diagrams illustrating cross-sectional views of a portion of a vertical NV memory device during fabrication according to the method of FIG. 1;
• FIGS. 2V to 2Z are representative diagrams illustrating cross-sectional views and a schematic diagram of a portion of a finished vertical NV memory device including multiple vertical strings of NV memory cells and common source line fabricated according to the method of FIGS, l and 2A-2U.
• NV memory includes memory devices that retain their states even when operation power is removed. While their states may eventually dissipate, they are retained for a relatively long period of time.
• particular embodiments may be practiced without one or more of these specific details, or in combination with other known methods, materials, and apparatuses. In the following description, numerous specific details are set forth, such as specific materials, dimensions, concentrations, and processes parameters etc. to provide a thorough understanding of the present subject matter.
• the terms “over”, “overlying”, “under”, “between”, and “on” as used herein refer to a relative position of one layer with respect to other layers.
• one layer deposited or disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
• one layer deposited or disposed between layers may be directly in contact with the layers or may have one or more intervening layers.
• a first layer “on” a second layer is in contact with that second layer.
• the relative position of one layer with respect to other layers is provided assuming operations deposit, modify and remove films relative to a starting wafer without consideration of the absolute orientation of the wafer.
• a memory device including an opening or openings disposed in a stack including first stack layers and second stack layers over a wafer, a multi-layer dielectric disposed over at least an inner sidewall of the openings, a first channel layer disposed over the multi-layer dielectric, and a second channel layer disposed over the first channel layer, in which at least one of the first or second channel layers includes germanium (Ge).
• the openings may be substantially perpendicular to a top surface of the wafer and may include a cross-sectional shape selected from a group of circle, oval, square, diamond, and rectangle.
• the first and second stack layers may be disposed over one another in an alternating manner to form the stack, the first stack layers include silicon dioxide (Si0 2 ) or other dielectric, and each of the second stack layers includes a gate layer, wherein the gate layer may include one of a doped polycrystalline silicon (Poly-Si) layer or a tungsten/titanium nitride (W/TiN) composite layer or other metal gate layers.
• the first and second stack layers may be disposed over one another in an alternating manner to form the stack
• the first stack layers include silicon dioxide (Si0 2 ) or other dielectric
• each of the second stack layers includes a gate layer, wherein the gate layer may include one of a doped polycrystalline silicon (Poly-Si) layer or a tungsten/titanium nitride (W/TiN) composite layer or other metal gate layers.
• At least one of the first or second channel layers may include a silicon-germanium (Si-Ge) composite layer, and the Si-Ge composite layer may include Ge concentration by number of atoms in an approximate range of 5% to 95%.
• the first and second channel layers may include a poly-crystalline structure.
• At least one additional channel layer may be disposed over the second channel layer, wherein the at least one additional channel layer includes Ge.
• the multi-layer dielectric may include a blocking dielectric layer disposed over at least the inner sidewall of the openings, a charge-trapping layer over the blocking dielectric layer, and a tunnel dielectric layer over the charge-trapping layer, wherein the charge-trapping layer may include a multi-layer structure.
• the multilayer structure of the charge-trapping layer may include an outer nitride layer, a middle dielectric layer, and an inner nitride layer, wherein at least one of the outer or inner nitride layers may include silicon oxynitride.
• one of the outer and inner nitride layers may be oxygen- rich and the other may be silicon-rich, and wherein the middle dielectric layer may be oxygen- rich and mostly charge-trap free.
• At least one of the first or second channel layers is positively doped and may include a dopant selected from a group of boron, gallium, or indium, and doped at an approximate concentration range of lei 5 cm “3 to lei 8 cm “3 .
• a thickness ratio between the first and the second channel layers may be in an approximate range of 1:5 to 1 :0.2.
• the NVM transistor may include memory transistors or devices related to Silicon- Oxide-Nitride-Oxide-Silicon (SONOS) or floating gate technology.
• SONOS Silicon- Oxide-Nitride-Oxide-Silicon
• FIG. 1 is a flowchart illustrating an embodiment of a method or process flow for fabricating a 3-D or vertical NV memory device.
• FIGS. 2A-2U are block and schematic diagrams illustrating cross- sectional and isometric views of a portion of a vertical NV memory device during fabrication of the memory cells according to the method of FIG. 1.
• FIGS. 2T-2Z are representative diagrams illustrating a cross-sectional view of a portion of one embodiment of the finished memory device or array.
• the vertical NV memory device may include a single or multiple vertical memory cell strings, such as NAND flash memory strings.
• the fabrication process 1000 begins with forming a stack 105 of alternating layers of multiple inter-cell dielectric layers or first stack layers 104 and gate layers or second stack layers 106 over a substrate or wafer 102, in step 1002 of fabrication process 1000.
• each inter-cell dielectric layer 104 is stacked between two gate layers 106 and vice versa, either throughout the entire stack 105 or at least in parts of stack 105.
• Wafer 102 may be a bulk wafer composed of any single crystal material suitable for semiconductor device fabrication, or may include a top epitaxial layer of a suitable material formed on a wafer.
• suitable materials for wafer 102 include, but are not limited to, silicon, germanium, silicon-germanium or a Group III-V compound semiconductor material.
• stack 105 is formed adopting a stair geometry or a pyramid configuration having a plurality of steps.
• each step includes an inter-cell dielectric layer 104 and a gate layer 106 to form a pair 103.
• the surface area of inter-cell dielectric layer 104 and gate layer 106 pair 103 may get smaller as they are disposed higher in stack 105.
• the stair geometry of stack 105 may facilitate more effective word-line connections to gate layers 106.
• stack 105 may adopt other configurations and all inter-cell dielectric layer 104 and gate layer 106 pairs 103 may have approximately the same surface area.
• inter-cell dielectric layer 104 of the bottom pair 103 may be disposed directly overlying and in contact with wafer 102, or there may be intervening layers between them (not shown).
• the intervening layers may be dielectric layers, gate layers, semiconductor layers used to manufacture intervening devices between the string of NV memory cells and wafer 102.
• the bottom intervening layers and top additional layers may be utilized to form semiconductor devices other than NV memory cells, such as field-effect transistors (FET) or connecting elements according to system requirements.
• FET field-effect transistors
• inter-cell dielectric layers 104 may be formed by any suitable deposition methods known in the art, such as sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), etc.
• the inter-cell dielectric layers 104 may include silicon dioxide (Si0 2 ) or other dielectric material having a thickness of from about 20 nanometers (nm) to about 50 nm or other appropriate thicknesses. In some embodiments, inter-cell dielectric layers 104 may have variable thicknesses throughout stack 105.
• inter-cell dielectric layers 104 may be grown by a thermal oxidation process, in-situ steam generation process or plasma or radical oxidation technique.
• gate layers 106 may eventually become or electrically coupled to control gates of NV transistors in vertical NV memory device 200 (not shown in this figure).
• gate layers 106 may be coupled to word-lines. As best shown in FIG. 2A, gate layers 106 may be formed over a top surface of each inter-cell dielectric layer 104.
• gate layers 106 may be formed by a deposition process like those discussed above, and include a single doped polysilicon layer, either positively or negatively doped (p+ doped or n+ doped) with appropriate dopants and concentration known in the art.
• the gate layers 106 may have a thickness of from about 30 nm to about 60 nm or other thicknesses. In some embodiments, gate layers 106 may have variable thicknesses throughout stack 105.
• gate layers 106 when metal control gates are desired, gate layers 106 may be formed by a deposition process and composed of a single layer of silicon nitride (S1 3 N 4 ) having a thickness of from about 30 nm to about 60 nm or other thicknesses. Gate layers 106 that are composed of silicon nitride, may then be replaced by or converted to metal gate layers 123 in step 1022, which will be discussed in later sections.
• vertical openings 108 which are substantially perpendicular to the plane of wafer 102, may be formed in locations where vertical channels of NV memory cell strings 100 of vertical NV memory device 200 may be subsequently formed. In one embodiment, there may be multiple NV memory cell strings 100 in one vertical NV memory device 200. It is the understanding that the vertical axis of openings 108 may be disposed at a right angle (90°) or an approximate right angle to the top surface of wafer 102. In one embodiment, openings 108 may be formed by etching stack 105 using suitable etching processes, such as plasma etching, wet etching, etc. There may be a plurality of slits 151 to form common source line (CSL) 152 in stack 105 in block 1024. In one embodiment, slits 151 are deep trenches formed throughout stack 105.
• CSL common source line
• an NV memory array 500 may include multiple vertical NV memory devices 200 disposed on wafer 102.
• a layer of dielectric such as Si0 2 , is formed and subsequently planarized to form interlayer dielectric layer (ILD) 202, in step 1004.
• ILD interlayer dielectric layer
• FIG. 2D features a side cross-sectional view along line Y-Y' of FIG. 2B and FIG. 2E features a top cross- sectional view along X-X' of FIG. 2D.
• openings 108 may be etched to reach or beyond a top surface of wafer 102, in step 1006.
• Optical emission intensity and/or spectroscopic reflectometry technique may be used to detect the end point of and subsequently terminate the openings 108 formation process.
• Openings 108 may have an approximately uniform diameter 110 of from about 60 nm to about 130 nm or other dimensions throughout the entirety of stack 105.
• openings 108 may have a variable cross-sectional diameter, such as a tapered shape (not shown).
• each opening 108 may be distributed to maintain a minimum spacing, which is the distance from the perimeter of one opening 108 to another. In one embodiment, the minimum spacing may be maintained at about 20 nm to about 130 nm or other dimensions. In another embodiment, openings 108 may be distributed such that NV memory cells in area 92 to be formed may share the same set of control gates and connections to the same set of word-lines and/or CSL 152. [0031] Referring to FIG. 1, FIGS.
• vertical NV memory device 200 featuring a single opening 108 (one NV memory cell string 100 when completed), having four alternating inter-cell dielectric layers 104 and gate layers 106, is illustrated. It will be the understanding that this is an exemplary embodiment, for illustration and not limitation purposes, to illustrate the subject matter as vertical NV memory device 200 may have other quantities and combinations of openings 108, alternating inter-cell dielectric layers 104 and gate layers 106 pair 103. Moreover, a vertical NV memory device 200 may include additional semiconductor devices formed at its two ends (in top additional layers and bottom intervening layers as discussed above).
• a vertical NV memory device 200 that has multiple openings 108 may contain multiple NV memory cell strings 100, each may be fabricated in similar processes, either concurrently or sequentially.
• a vertical NV memory device 200 may be formed in openings 108 by forming a string of NV memory cells 94 in areas 92 connected in series.
• Each NV memory cell 94 may be formed in the area 92 which includes two inter-cell dielectric layers 104 and one gate layer 106.
• NV memory cells 94 of the same NV memory cell strings 100 may be coupled in series, which resembles a NAND flash memory cell string embodiment. As best illustrated in FIG.
• opening 108 may have a circular cross-section with a diameter 110 of from about 60 nm to about 130 nm or other dimensions.
• opening 108' may have a cross-section of other shapes, such as a square, a rectangle, a diamond, an oval, etc.
• openings 108' of other shapes may also maintain a minimum spacing at about 20 nm to about 130 nm from one another.
• SEG selective epitaxial growth
• SEG structure 154 may be disposed in contact with wafer 102 and fills up the bottom of opening 108 corresponding to multiple alternating layers and/or intervening layers in stack 105.
• SEG structure 154 may be composed of silicon, fabricated using SEG techniques in which growth may occur on exposed silicon areas of wafer 102. Regions on which silicon growth is not desired may be masked by a dielectric film, typically silicon dioxide or silicon nitride. Silicon grown in the SEG structure may be undoped. Alternatively, silicon may be doped. In some embodiments, silicon in SEG structure 154 may be positively doped, negatively doped, and the doping may be in-situ doping.
• SEG structure 154 may be carried out either during the SEG formation step 1008 or after.
• SEG structure 154 for each NV memory cell string 100 may be connected to CSL 152 (not shown in this figure) with a coupling structure either formed on or within wafer 102.
• FIG. 2H is a side cross-sectional view of one embodiment of a portion of vertical NV memory device 200 and FIG. 21 is a top cross-sectional view along X-X' of FIG. 2H.
• blocking dielectric layer 112 is formed in opening 108 in step 1010.
• blocking dielectric layer 112 may include a single layer or multiple layers, and may include layers of Si0 2 or other dielectric materials coating the inside wall of opening 108 and the top surface of SEG structure 154.
• the blocking dielectric layer 112 may be formed by suitable conformal deposition process, such as CVD and ALD, and have a relatively uniform thickness of about 30 A to about 70A or other thicknesses.
• the blocking dielectric layer 112 may be deposited by a CVD process using a process gas including gas mixtures of silane or dichlorosilane (DCS) and an oxygen-containing gas, such as 0 2 or N 2 0, in ratios and at flow rates tailored to provide a silicon dioxide (Si0 2 ) blocking dielectric layer 112.
• a process gas including gas mixtures of silane or dichlorosilane (DCS) and an oxygen-containing gas, such as 0 2 or N 2 0, in ratios and at flow rates tailored to provide a silicon dioxide (Si0 2 ) blocking dielectric layer 112.
• blocking dielectric layer 112 may include other high-k dielectric materials, such as hafnium oxide, alternatively or additionally to silicon dioxide.
• blocking dielectric layer 112 may be formed by thermal oxidation or in-situ steam generation or plasma, radical, or other oxidation processes.
• FIG. 2J is a side cross-sectional view of one embodiment of a portion of vertical NV memory device 200 and FIG. 2K is a top cross-sectional view along X-X' of FIG. 2J.
• charge-trapping layer 114 is formed in opening 108, in step 1012.
• charge -trapping layer 114 is a single layer and may include a layer of silicon nitride and/or silicon oxynitride formed on or overlying or in contact with the blocking dielectric layer 112.
• the charge-trapping layer 114 may be formed by suitable conformal deposition process, such as CVD and ALD.
• charge-trapping layer 114 may have a relatively uniform thickness of from about 50 A to about 100A or other thicknesses. As best shown in FIG. 2J, charge-trapping layer 114 is a continuous layer, or coating the entire length of opening 108. In one embodiment, charge-trapping layer 114 may cover portions where NV memory cells 94 are formed in opening 108. NV memory cells 94 formed in different layers in stack 105 do not interfere with one another because charge carriers trapped in the charge-trapping layer 114 may not move from layer to layer vertically along opening 108. The electric fields associated with gate layers 106 closely confine charge carriers in the charge -trapping layer 114 to the gate layer 106 they are trapped in. [0035] In another embodiment, as illustrated in the exploded view in FIG.
• an alternative embodiment of charge trapping layer 114' may include multiple layers including at least a first charge-trapping layer or outer charge-trapping layer 114a that is formed on or overlying or in contact with the blocking dielectric layer 112, and a second charge-trapping layer or inner charge-trapping layer 114e that is formed on or overlying or in contact with the first charge- trapping layer 114a.
• the first charge-trapping layer 114a may be oxygen-lean relative to the second charge-trapping layer 114c and may comprise a majority of a charge traps distributed in multi-layer charge-trapping layer 114'.
• the first charge-trapping layer 114a may include a silicon nitride and silicon oxynitride layer having a stoichiometric composition of oxygen, nitrogen and/or silicon that is different from that of the second charge-trapping layer 114c.
• the first charge-trapping layer 114a may include a silicon oxynitride layer which may be formed or deposited by a CVD process using a process gas including DCS/NH 3 and N 2 0/NH 3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean top nitride layer.
• mono-silane SiH 4 (MS), di-silane Si 2 3 ⁇ 4 (DS), tetra-chloro- silane SiCl 4 (TCS), and hexa-chloro-di-silane S1 2 CI 6 (HCD) may be used as a source of silicon in the CVD process.
• the second charge-trapping layer 114c of a multi-layer charge-trapping layer 114' may include a silicon nitride (Si 3 N 4 ), silicon-rich silicon nitride or a silicon oxynitride (SiO x N y ) layer.
• the second charge-trapping layer 114c may include a silicon oxynitride layer formed by a CVD process using dichlorosilane (DCS)/ammonia (NH 3 ) and nitrous oxide (N 2 0)/NH 3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer.
• DCS dichlorosilane
• NH 3 ammonia
• N 2 0 nitrous oxide
• composition of oxygen, nitrogen and/or silicon of first and second charge-trapping layers 114a & 114c may be identical or approximate to one another.
• the middle oxide layer 114b may include Si0 2 and/or oxygen-rich dielectric that is charge traps free.
• the middle oxide layer 114b may substantially reduce the probability of electron charge that accumulates at the boundaries of the first charge-trapping layer 114a during programming from tunneling into the second charge-trapping layer 114c, resulting in lower leakage current than for conventional memory devices.
• the middle oxide layer 114b is formed by oxidizing to a chosen depth using thermal or radical oxidation or deposition processes, such as CVD and ALD.
• oxygen-rich and “silicon-rich” are relative to a stoichiometric silicon nitride, or “nitride,” commonly employed in the art having a composition of (S1 3 N 4 ) and with a refractive index (RI) of approximately 2.0 at 633 nm.
• nitride commonly employed in the art having a composition of (S1 3 N 4 ) and with a refractive index (RI) of approximately 2.0 at 633 nm.
• RI refractive index
• films described herein as "silicon-rich” correspond to a shift from stoichiometric silicon nitride toward a higher weight percentage of silicon with less oxygen than an "oxygen-rich” film.
• a silicon-rich silicon oxynitride film is therefore more like silicon and the RI is increased toward the 3.5 RI of pure silicon.
• FIG. 2L is a side cross-sectional view of one embodiment of a portion of vertical NV memory device 200 and FIG. 2M is a top cross-sectional view along X-X' of FIG. 2L.
• tunnel dielectric layer 116 is formed in opening 108, in step 1014.
• tunnel dielectric layer 116 may be formed on or overlying or in contact with the charge-trapping layer 114 within opening 108.
• a layer of dielectric material may be deposited by CVD or ALD process.
• the layer of dielectric material may include, but not limited to silicon dioxide, silicon oxynitride, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxynitride, hafnium zirconium oxide and lanthanum oxide.
• tunnel dielectric layer 116 has a relatively uniform thickness of from about 20 A to about 50 A or other thicknesses suitable to allow charge carriers to tunnel into the charge -trapping layer 114 under an applied control gate bias while maintaining a suitable barrier to leakage when the applied gate is unbiased.
• tunnel dielectric layer 116 is silicon dioxide, silicon oxynitride, or a combination thereof and can be grown by a thermal oxidation process, using plasma or radical oxidation of a portion of second charge-trapping layer 114c.
• tunnel dielectric layer 116 may be a bi-layer dielectric region including a first layer of a material such as, but not limited to, silicon dioxide or silicon oxynitride and a second layer of a material which may include, but is not limited to silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxynitride, hafnium zirconium oxide and lanthanum oxide.
• blocking dielectric layer 112, charge trapping layer 114 and tunnel dielectric layer 116 may be referred to collectively as charge trapping dielectric or multilayer dielectric 107.
• FIG. 20 is a side cross-sectional view of one embodiment of a portion of vertical NV memory device 200 and FIG. 2P is a top cross-sectional view along X-X' of FIG. 20.
• first channel layer or outer channel layer 118a may be formed on, overlying or in contact with the tunnel dielectric layer 116 within opening 108.
• the first channel layer 118a may include any suitable semiconductor materials, such as silicon, germanium, silicon germanium, or other compound semiconductor materials, such as III-V, II- VI, or conductive or semi-conductive oxides, etc.
• the semiconductor material may be amorphous, polycrystalline, or single crystal.
• the first channel layer 118a may be formed by any suitable deposition process, such as low pressure chemical vapor deposition (LPCVD), CVD and ALD.
• LPCVD low pressure chemical vapor deposition
• CVD chemical vapor deposition
• ALD atomic layer deposition
• the semiconductor channel material may be a recrystallized
• polycrystalline semiconductor material formed by recrystallizing an initially deposited amorphous semiconductor material.
• NV memory cell strings 100 it is imperative to maintain an adequately high reading current or on-current flowing through NV memory cell strings 100 to avoid errors during read operations.
• the potential problem of a weak reading current is made worse when stack 105 includes more inter-cell dielectric layer 104 and gate layer 106 pairs 103 (stair steps) to incorporate more NV memory cells 94 in the NV memory cell strings 100.
• stack 105 includes more inter-cell dielectric layer 104 and gate layer 106 pairs 103 (stair steps) to incorporate more NV memory cells 94 in the NV memory cell strings 100.
• first channel layer 118a is formed in opening 108, in step 1016.
• first channel layer 118a of vertical NV memory device 200 is vertical and substantially perpendicular to a top surface of substrate 102, which has an opposite orientation of the channels in 2-D geometry.
• First channel layer 118a is disposed using a CVD process, such as LPCVD and plasma-enhanced chemical vapor deposition (PECVD).
• the first channel layer 118a may include a silicon-germanium (Si-Ge) composite layer.
• the concentration of Ge in the Si-Ge composite layer may range from 1% to 99% by no. of Ge atoms. In one embodiment, the concentration is kept at around 5% Ge to 95% Ge.
• first channel layer 118a may include only Poly-Si or Poly-Ge.
• the first channel layer 118a may have a relative uniform thickness of from about 50 A to about 150 A or other thicknesses.
• Si-Ge composite layer may have higher electron and/or hole mobility. Consequently, reading or on-current through first channel layer 118a may be maintained at a higher level.
• semiconductor source may be selected from the group of GeH 2 Cl 2 , Ge 2 H 6 , GeH 4 , SiH 2 Cl 2 , Si 3 H8, Si 2 H6, S1H 4 , and a combination thereof.
• Gas LTO520 may be used to enhance seed formation during the deposition process in small openings, such as opening 108.
• Si-Ge layer has a lower melting point than Si/Poly-Si and thus yields relatively larger grains than Si/Poly-Si.
• the Si-Ge layer of first channel layer 118a may have less defects such as grain boundaries which may adversely affect reading current as previously discussed.
• the Si-Ge layer also allows possible Band-gap engineering in first channel layer 118a since Si-Ge layer may have different band-structure depending on the Ge concentration.
• first channel layer 118a may contain un-doped or electrically neutral semiconductor channel material as discussed above.
• the semiconductor channel material may be lightly doped with positive-typed dopants, such as boron.
• first channel layer 118a is formed by in-situ boron-doped CVD technique. During the deposition process, approximately 0.01% to 1% of boron source, such as BC1 3 or B23 ⁇ 4 in S1H 4 is introduced, and the process is carried out in a temperature at approximately 530°C.
• the concentration of dopant in first channel layer 118a may be from about lel5 cm “3 to about lel8 cm “3 or other appropriate concentrations.
• dopants such as gallium or indium may be used alternatively or additionally.
• Deposition processes such as conformal implant technique, plasma-immersion ion implantation, that are capable of high aspect ratio may also be used.
• FIG. 2Q is a side cross-sectional view of one embodiment of a portion of vertical NV memory device 200.
• the process of multi-layer punch or etch is performed, in step 1018.
• the multi-layer punch may be performed to remove a portion of the semiconductor-oxide-nitride-oxide (SONO) layers and/or other layers.
• first channel layer 118a is physically and electrically isolated from SEG structure 154 by at least the blocking dielectric layer 112, charge trapping layer 114 and tunnel dielectric layer 116.
• An etching process is performed to remove layers previously deposited at the bottom of opening 108.
• plasma etch process is performed until the bottom of opening 108 at least reaches or gouges into SEG structure 154.
• Etchant may include fluorine-based chemicals, such as CF 4 , C 4 F 6 , CH 2 F 2 , NF 3 , and O2 and Ar.
• multi-layer punch is performed to remove a portion of multi-layer dielectric 107 and first channel layer 118a disposed at the bottom of opening 108 until SEG structure 154 is exposed.
• first channel layer 118a may be physically and/or electrically isolated from SEG structure 154.
• FIG. 2R is a side cross-sectional view of one embodiment of a portion of vertical NV memory device 200.
• second channel layer or inner channel layer 118b is formed in opening 108, in step 1018.
• second channel layer 118b is deposited and over first channel layer 118a and the bottom of opening 108 created by the previously discussed multi-layer punch or etch process.
• Second channel layer 118b is disposed using similar CVD process as those used in forming the first channel layer 118a in step 1016.
• second channel layer 118b may include a silicon- germanium (Si-Ge) composite layer.
• the concentration of Ge in the Si-Ge composite layer may range from 1% to 99%. In one embodiment, the concentration is kept at around 5% Ge to 95% Ge concentration (no. of Ge atoms based).
• second channel layer 118b may include only Poly-Si or Poly-Ge. In one embodiment, the second channel layer 118b may have a relative uniform thickness of from about 50 A to about 150 A or other thicknesses.
• Second channel layer 118b may also be either undoped or slightly and positively doped by similar processes and concentration in forming the first channel layer 118a.
• first and second channel layers 118a and 118b form the channel 118 for the NV memory cell strings 100.
• channel 118 may be a single layer.
• second channel 118b is electrically and may be physically coupled to SEG structure 154 and first channel layer 118a, reconnecting the two elements. SEG structure 154 may then be electrically coupled to common source line 152 (not shown in this figure).
• Second channel 118b may, in some embodiments, physically connecting SEG structure 154 to first channel layer 118a.
• first and second channel layers 118a and 118b may have different Ge concentration in each of its Si-Ge composite layer.
• Ge concentration is higher in the first channel layer 118a and the silicon/Poly-Si concentration in the second channel layer 118b is higher.
• the higher Ge concentration may increase the on- current in the first channel layer 118a, while the higher Si/Poly-Si concentration in the second channel layer 118b may provide better lattice matching with SEG structure 154, and effective back interface with dielectric filler 120 (not shown in this figure) formed subsequently.
• the formation of dielectric filler 120 will be discussed in later sections.
• Thickness ratio between the first and second channel layers 118a and 118b may range from about 1:5 to about 1:0.2. In one embodiment, the thickness ratio between the first and second channel layers 118a and 118b is configured to be about 1: 1.
• FIG. 2S is a top cross-sectional view along X-X' of FIG. 2R.
• first and second channel layers 118a and 118b are adjacent to and/or in contact with one another.
• Inner (top) surface of first channel layer 118a is treated with etchants during the multi-layer punch or etch step 1018 before receiving the second channel layer 118b.
• one or more additional channel layer may be deposited over second channel layer 118b according to system requirements.
• the additional channel layer(s) over the second channel layer 118b may be deposited in a similar process steps as the first and second channel layers 118a & 118b.
• the Ge concentration, thickness of the additional channel layer(s) may be similar or different from the first and second channel layers 118a & 118b.
• the inner most channel layer may have a relatively lower Ge concentration to reduce formation of Ge oxide during formation of dielectric filler 120 (not shown in this figure).
• the additional channel layer(s) may be formed in one step or multiple steps.
• FIG. 2T is a side cross-sectional view of one embodiment of a portion of vertical NV memory device 200 and FIG. 2U is a top cross-sectional view along X-X' of FIG. 2T.
• dielectric filler 120 is formed in opening 108 to fill out empty space in opening 108 after second channel layer 118b is formed, in step 1020.
• dielectric filler 120 includes dielectric materials, such as silicon dioxide, silicon nitride, and silicon oxynitride.
• Dielectric filler 120 may be formed by deposition methods, such as CVD or ALD, or oxidation methods, such as plasma or radical oxidation technique or thermal RTO.
• FIG. 2V is a side cross-sectional view of one embodiment of a portion of NV memory cell string 100 of vertical NV memory device 200 and FIG. 2X is a top cross-sectional view along X-X' of FIG. 2V.
• metal gate layer 123 is formed to replace gate layers 106 disposed between inter-cell dielectric layers 104 in stack 105, in step 1022.
• gate layers 106 which include silicon nitride, are removed firstly using a wet etch process.
• Vertical NV memory device 200 is dipped in wet etch chemical, such as phosphoric acid (H 3 PO 4 ) in a temperature range of from about 150°C to about 170°C, for about 50 minutes (mins) to about 120 mins.
• photoresist layers or hard marks may be formed to protect other layers from etchants.
• the process may start by forming gate coating layer 124 of titanium nitride (TiN) using a suitable deposition process, such as metalorganic CVD (MOCVD) or ALD.
• MOCVD metalorganic CVD
• ALD atomic layer deposition
• the deposited layer becomes gate coating layer 124 that coats or lines the space defined by two neighboring inter-cell dielectric layers 104 and blocking dielectric layer 112.
• the coating of the space may be complete or partial.
• TiN coating as the gate coating layer 124 improves surface properties.
• the combination of TiN and W to form metal gate layer 123 is one of the combinations of the present embodiment.
• Other combinations using different conductive materials to form metal gate layers 123 may include but are not limited to metal nitrides, metal carbides, metal silicides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, tungsten, palladium, platinum, cobalt, and nickel, which are known in the art and may be adopted.
• polysilicon gate layers is formed by deposition process, such as CVD and ALD.
• deposition process such as CVD and ALD.
• polysilicon doped with appropriate dopants at an operational concentration that are known in the art may be deposited.
• a layer of high-K dielectric 125 is deposited to coat or line the space defined by two neighboring inter-cell dielectric layers 104 and blocking dielectric layer 112, either completely or partially.
• the layer of high-K dielectric 125 may include AI2O3 and be deposited by ALD.
• NV memory cell strings 100 is primarily completed.
• the embodiment shown in FIG. 2V features five NV memory cells 94. It will be understood by one having ordinary skill in the art that other quantities of NV memory cells 94 in one NV memory cell strings 100 may be fabricated using the process steps disclosed herein by having more stair steps 103 in stack 105.
• the completed NV memory cell string 100 includes a string of NV memory cells 94 connected in series (by channel layer 118), in which metal gate layers 123 or polysilicon layers correspond to control gates and portions of channel layer 118 adjacent to inter-cell dielectric layers 104 to source/drain regions of individual NV memory cells 94.
• channel layer 118 including first and second channel layers 118a and 118b, represents a shared channel for all NV memory cells 94 within one opening 108 of the NV memory cell strings 100.
• vertical NV memory cell strings 100 in the same vertical NV memory device 200 may be fabricated concurrently or sequentially.
• Each NV memory cell 94 on the same layer of stack 105 shares a same metal gate layer 123 which includes gate coating layer 124 and gate filler layer 122.
• metal gate layer 123 either functions as a common word-line or is coupled to a common word-line for NV memory cells 94 of the same vertical layer in vertical NV memory device 200.
• Vertical NV memory cell strings 100 may have one top end coupled to a bit-line and one bottom end coupled to a common source-line 152 via channel layer 118 and SEG structure 154.
• one or more vertical NV memory cell strings 100 may share one bit-line. In another embodiment, one or more vertical NV memory cell strings 100 may share one common source- line 152.
• channel layer 118 may be connected to bit-line via channel plug (not shown) at the top of channel layer 118. It is understood that channel plugs and/or other connecting elements to bit-lines are fabricated in methods practiced by ordinary skill in the art, and will be not be discussed in details herein.
• FIG. 2Z is a side cross-sectional view along Z-Z' of FIG. 2B of one embodiment of a portion of vertical NV memory device 200 showing common source line structure 152.
• each deep CSL trench 151 there may be multiple vertical deep CSL slits or trenches 151 created in a particular pattern in stack 105, by etching method such as plasma etching and wet etching .
• etching method such as plasma etching and wet etching .
• a CSL structure 152 is formed within each deep CSL trench 151.
• a layer of dielectric 156 such as silicon oxide, is deposited by CVD or ALD in CSL trench 151.
• source-line 158 that may include electrical conducting material, such as W, may be deposited.
• source-line 158 may extend and gouge into wafer 102 and further connected to SEG structure 154 of one or multiple vertical NV memory cell strings 100.
• the circuit diagram illustrated in FIG. 2Z shows that four vertical NV memory cell strings 100, each has its own bit-line BLl-4, are each coupled electrically to CSL 152. It will be understood that different numbers of vertical NV memory cell strings 100 may share one or multiple CSL 152 and/or bit-lines, according to system requirements. [0052] Thus, embodiments of vertical/3-D NV memory devices/strings/apparatus and methods of fabricating the same have been described.

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