JP2016541123A5 - - Google Patents

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JP2016541123A5
JP2016541123A5 JP2016539325A JP2016539325A JP2016541123A5 JP 2016541123 A5 JP2016541123 A5 JP 2016541123A5 JP 2016539325 A JP2016539325 A JP 2016539325A JP 2016539325 A JP2016539325 A JP 2016539325A JP 2016541123 A5 JP2016541123 A5 JP 2016541123A5
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mtj
forming
imd layer
common
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JP2016539325A
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JP6740129B2 (ja
JP2016541123A (ja
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Priority claimed from US14/109,200 external-priority patent/US9406875B2/en
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JP2016539325A 2013-12-17 2014-12-12 技術スケーリングのためのｍｒａｍ統合技法 Expired - Fee Related JP6740129B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/109,200 2013-12-17
US14/109,200 US9406875B2 (en) 2013-12-17 2013-12-17 MRAM integration techniques for technology scaling
PCT/US2014/070035 WO2015094974A1 (en) 2013-12-17 2014-12-12 Mram integration techniques for technology scaling

Publications (3)

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JP2016541123A JP2016541123A (ja) 2016-12-28
JP2016541123A5 true JP2016541123A5 (enExample) 2018-01-11
JP6740129B2 JP6740129B2 (ja) 2020-08-12

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JP2016539325A Expired - Fee Related JP6740129B2 (ja) 2013-12-17 2014-12-12 技術スケーリングのためのｍｒａｍ統合技法

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US (2) US9406875B2 (enExample)
EP (1) EP3084766B1 (enExample)
JP (1) JP6740129B2 (enExample)
CN (1) CN105830161B (enExample)
WO (1) WO2015094974A1 (enExample)

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