JP2016540378A5 - - Google Patents

Download PDF

Info

Publication number
JP2016540378A5
JP2016540378A5 JP2016530238A JP2016530238A JP2016540378A5 JP 2016540378 A5 JP2016540378 A5 JP 2016540378A5 JP 2016530238 A JP2016530238 A JP 2016530238A JP 2016530238 A JP2016530238 A JP 2016530238A JP 2016540378 A5 JP2016540378 A5 JP 2016540378A5
Authority
JP
Japan
Prior art keywords
gate length
devices
patterning
gates
cpp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2016530238A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016540378A (ja
JP6316959B2 (ja
Filing date
Publication date
Priority claimed from US14/283,168 external-priority patent/US9691868B2/en
Application filed filed Critical
Publication of JP2016540378A publication Critical patent/JP2016540378A/ja
Publication of JP2016540378A5 publication Critical patent/JP2016540378A5/ja
Application granted granted Critical
Publication of JP6316959B2 publication Critical patent/JP6316959B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2016530238A 2013-11-22 2014-10-24 ゲートパターニングのためのリソグラフィマージプロセス Expired - Fee Related JP6316959B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361908007P 2013-11-22 2013-11-22
US61/908,007 2013-11-22
US14/283,168 US9691868B2 (en) 2013-11-22 2014-05-20 Merging lithography processes for gate patterning
US14/283,168 2014-05-20
PCT/US2014/062276 WO2015076978A1 (en) 2013-11-22 2014-10-24 Merging lithography processes for gate patterning

Publications (3)

Publication Number Publication Date
JP2016540378A JP2016540378A (ja) 2016-12-22
JP2016540378A5 true JP2016540378A5 (enExample) 2017-09-21
JP6316959B2 JP6316959B2 (ja) 2018-04-25

Family

ID=51847018

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016530238A Expired - Fee Related JP6316959B2 (ja) 2013-11-22 2014-10-24 ゲートパターニングのためのリソグラフィマージプロセス

Country Status (6)

Country Link
US (1) US9691868B2 (enExample)
EP (1) EP3072152A1 (enExample)
JP (1) JP6316959B2 (enExample)
KR (1) KR20160088358A (enExample)
CN (1) CN105745747B (enExample)
WO (1) WO2015076978A1 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9691868B2 (en) * 2013-11-22 2017-06-27 Qualcomm Incorporated Merging lithography processes for gate patterning
US9691898B2 (en) * 2013-12-19 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Germanium profile for channel strain
US9287398B2 (en) 2014-02-14 2016-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor strain-inducing scheme
US9406511B2 (en) * 2014-07-10 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned double patterning
US20160111421A1 (en) * 2014-10-21 2016-04-21 Mark S. Rodder Multiple cpp for increased source/drain area for fets including in a critical speed path
TWI695283B (zh) * 2015-08-05 2020-06-01 聯華電子股份有限公司 半導體佈局結構及其設計方法
US9397006B1 (en) 2015-12-04 2016-07-19 International Business Machines Corporation Co-integration of different fin pitches for logic and analog devices
US9793270B1 (en) * 2016-04-21 2017-10-17 International Business Machines Corporation Forming gates with varying length using sidewall image transfer
CN109216185B (zh) * 2017-07-03 2021-02-26 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制备方法
DE102017127276A1 (de) * 2017-08-30 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Standardzellen und abwandlungen davon innerhalb einer standardzellenbibliothek
US10361127B1 (en) 2017-12-28 2019-07-23 International Business Machines Corporation Vertical transport FET with two or more gate lengths
US11164772B2 (en) 2018-10-30 2021-11-02 International Business Machines Corporation Spacer-defined process for lithography-etch double patterning for interconnects
KR102628894B1 (ko) * 2018-12-05 2024-01-24 삼성전자주식회사 단위 배선 구조를 갖는 집적 회로, 그 제조 방법 및 설계 방법
KR20220087229A (ko) 2020-12-17 2022-06-24 삼성전자주식회사 반도체 소자
US12453071B2 (en) * 2022-04-26 2025-10-21 Qualcomm Incorporated Gate spacer structures for three-dimensional semiconductor devices
US20240171137A1 (en) * 2022-11-22 2024-05-23 Macom Technology Solutions Holdings, Inc. Multi-zone radio frequency transistor amplifiers

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100354440B1 (ko) 2000-12-04 2002-09-28 삼성전자 주식회사 반도체 장치의 패턴 형성 방법
US6998332B2 (en) * 2004-01-08 2006-02-14 International Business Machines Corporation Method of independent P and N gate length control of FET device made by sidewall image transfer technique
US7446352B2 (en) * 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
CN101673735B (zh) * 2008-09-12 2011-11-16 台湾积体电路制造股份有限公司 默认多晶硅间距设计规则下的混合多晶硅间距单元设计结构及系统
US7932566B2 (en) 2008-12-31 2011-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and system of mixing poly pitch cell design under default poly pitch design rules
JP2011061003A (ja) 2009-09-10 2011-03-24 Elpida Memory Inc 配線パターン形成方法および半導体装置の製造方法、半導体装置、データ処理システム
US8390331B2 (en) * 2009-12-29 2013-03-05 Nxp B.V. Flexible CMOS library architecture for leakage power and variability reduction
US8314034B2 (en) 2010-12-23 2012-11-20 Intel Corporation Feature size reduction
US8610176B2 (en) * 2011-01-11 2013-12-17 Qualcomm Incorporated Standard cell architecture using double poly patterning for multi VT devices
JP5289479B2 (ja) * 2011-02-14 2013-09-11 株式会社東芝 半導体装置の製造方法
US8673165B2 (en) * 2011-10-06 2014-03-18 International Business Machines Corporation Sidewall image transfer process with multiple critical dimensions
EP2602663A1 (en) 2011-12-09 2013-06-12 Nederlandse Organisatie voor toegepast -natuurwetenschappelijk onderzoek TNO System and method for overlay control
US9558947B2 (en) 2011-12-29 2017-01-31 Intel Corporation Pattern decomposition lithography techniques
US8782571B2 (en) 2012-03-08 2014-07-15 Globalfoundries Inc. Multiple patterning process for forming trenches or holes using stitched assist features
US9691868B2 (en) * 2013-11-22 2017-06-27 Qualcomm Incorporated Merging lithography processes for gate patterning

Similar Documents

Publication Publication Date Title
JP2016540378A5 (enExample)
CN102667743B (zh) 存取具有非均匀页大小的多通道存储器系统
JP2017516313A5 (enExample)
US9691868B2 (en) Merging lithography processes for gate patterning
TWD160877S (zh) 電子機器用控制器外殼
JP2017506430A5 (enExample)
CN105447221B (zh) 设计半导体装置的布局的方法
WO2017067813A3 (en) A method of manufacturing a pellicle for a lithographic apparatus, a pellicle for a lithographic apparatus, a lithographic apparatus, a device manufacturing method, an apparatus for processing a pellicle, and a method for processing a pellicle
JP2017512383A5 (enExample)
WO2010042521A3 (en) Memory apparatus, systems and methods
WO2010019373A3 (en) Memory devices and methods of storing data on a memory device
WO2012166483A3 (en) Apparatuses including stair-step structures and methods of forming the same
JP2009518695A5 (enExample)
CN102959530A (zh) 多通道多端口存储器
JP2016538721A5 (enExample)
WO2011056529A3 (en) Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning
JP2018523919A5 (enExample)
TW201108017A (en) ROM layout systems and methods
JP2016503242A5 (enExample)
JP2007215028A5 (enExample)
TWD160873S (zh) 電子機器用控制器之部分
JP2017108357A5 (enExample)
MX2021000424A (es) Sistemas y metodos para centrar un objeto circular.
JP2016532974A5 (enExample)
JP2017515305A5 (enExample)