JP2016529708A - 異なる材料から基板上にフィンを形成する方法 - Google Patents

異なる材料から基板上にフィンを形成する方法 Download PDF

Info

Publication number
JP2016529708A
JP2016529708A JP2016531780A JP2016531780A JP2016529708A JP 2016529708 A JP2016529708 A JP 2016529708A JP 2016531780 A JP2016531780 A JP 2016531780A JP 2016531780 A JP2016531780 A JP 2016531780A JP 2016529708 A JP2016529708 A JP 2016529708A
Authority
JP
Japan
Prior art keywords
layer
substrate
opening
forming
oxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016531780A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016529708A5 (enExample
Inventor
スタンリー・スンチュル・ソン
ジョンゼ・ワン
チョ・フェイ・イェプ
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2016529708A publication Critical patent/JP2016529708A/ja
Publication of JP2016529708A5 publication Critical patent/JP2016529708A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292—Non-planar channels of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/011—Manufacture or treatment comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2016531780A 2013-08-01 2014-07-25 異なる材料から基板上にフィンを形成する方法 Pending JP2016529708A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/956,398 US9396931B2 (en) 2013-08-01 2013-08-01 Method of forming fins from different materials on a substrate
US13/956,398 2013-08-01
PCT/US2014/048270 WO2015017283A1 (en) 2013-08-01 2014-07-25 Method of forming fins from different materials on a substrate

Publications (2)

Publication Number Publication Date
JP2016529708A true JP2016529708A (ja) 2016-09-23
JP2016529708A5 JP2016529708A5 (enExample) 2017-08-17

Family

ID=51352812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016531780A Pending JP2016529708A (ja) 2013-08-01 2014-07-25 異なる材料から基板上にフィンを形成する方法

Country Status (6)

Country Link
US (2) US9396931B2 (enExample)
EP (1) EP3028301A1 (enExample)
JP (1) JP2016529708A (enExample)
KR (1) KR20160038031A (enExample)
CN (1) CN105453251B (enExample)
WO (1) WO2015017283A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9129863B2 (en) 2014-02-11 2015-09-08 International Business Machines Corporation Method to form dual channel group III-V and Si/Ge FINFET CMOS
US9123585B1 (en) * 2014-02-11 2015-09-01 International Business Machines Corporation Method to form group III-V and Si/Ge FINFET on insulator
US9564518B2 (en) * 2014-09-24 2017-02-07 Qualcomm Incorporated Method and apparatus for source-drain junction formation in a FinFET with in-situ doping
US20160358827A1 (en) * 2014-10-21 2016-12-08 United Microelectronics Corp. Method of forming fin-shaped structure
US9524987B2 (en) 2014-10-21 2016-12-20 United Microelectronics Corp. Fin-shaped structure and method thereof
US9633908B2 (en) 2015-06-16 2017-04-25 International Business Machines Corporation Method for forming a semiconductor structure containing high mobility semiconductor channel materials
EP3314665A4 (en) * 2015-06-26 2019-02-20 INTEL Corporation CAVITATE-BASED INTEGRATION OF HETEROEPITACTIC N-TYPE TRANSISTORS WITH P-TYPE TRANSISTORS
US9679899B2 (en) * 2015-08-24 2017-06-13 Stmicroelectronics, Inc. Co-integration of tensile silicon and compressive silicon germanium
WO2017197589A1 (zh) 2016-05-17 2017-11-23 华为技术有限公司 一种用户面资源管理方法、用户面网元及控制面网元

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05129424A (ja) * 1992-04-01 1993-05-25 Ricoh Co Ltd 半導体装置とその製造方法
JP2005260240A (ja) * 2004-03-12 2005-09-22 Internatl Business Mach Corp <Ibm> ハイブリッド結晶方位基板上の集積回路構造及び形成方法（高性能ｃｍｏｓｓｏｉデバイス）
JP2006012995A (ja) * 2004-06-23 2006-01-12 Toshiba Corp 半導体装置及びその製造方法
JP2008505488A (ja) * 2004-06-30 2008-02-21 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 特徴の異なる結晶性半導体領域を有する基板の形成技術
JP2008108999A (ja) * 2006-10-27 2008-05-08 Sony Corp 半導体装置および半導体装置の製造方法
JP2008532330A (ja) * 2005-03-07 2008-08-14 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 集積回路およびその製造方法
JP2008227026A (ja) * 2007-03-12 2008-09-25 Toshiba Corp 半導体装置の製造方法
US7803670B2 (en) * 2006-07-20 2010-09-28 Freescale Semiconductor, Inc. Twisted dual-substrate orientation (DSO) substrates
JP2011035064A (ja) * 2009-07-30 2011-02-17 Renesas Electronics Corp 半導体装置、半導体基板、及び半導体基板の処理方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6864581B1 (en) * 2002-08-15 2005-03-08 National Semiconductor Corporation Etched metal trace with reduced RF impendance resulting from the skin effect
US6762448B1 (en) 2003-04-03 2004-07-13 Advanced Micro Devices, Inc. FinFET device with multiple fin structures
US6921982B2 (en) * 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
US6998684B2 (en) * 2004-03-31 2006-02-14 International Business Machines Corporation High mobility plane CMOS SOI
DE102004057764B4 (de) 2004-11-30 2013-05-16 Advanced Micro Devices, Inc. Verfahren zur Herstellung eines Substrats mit kristallinen Halbleitergebieten mit unterschiedlichen Eigenschaften, die über einem kristallinen Vollsubstrat angeordnet sind und damit hergestelltes Halbleiterbauelement
US7422956B2 (en) 2004-12-08 2008-09-09 Advanced Micro Devices, Inc. Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers
US8241970B2 (en) 2008-08-25 2012-08-14 International Business Machines Corporation CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins
US8258602B2 (en) 2009-01-28 2012-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Bipolar junction transistors having a fin
EP2315239A1 (en) 2009-10-23 2011-04-27 Imec A method of forming monocrystalline germanium or silicon germanium
US8513723B2 (en) 2010-01-19 2013-08-20 International Business Machines Corporation Method and structure for forming high performance MOS capacitor along with fully depleted semiconductor on insulator devices on the same chip
US8618556B2 (en) 2011-06-30 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design and method of fabricating same
KR20130054010A (ko) 2011-11-16 2013-05-24 삼성전자주식회사 Ｉｉｉ-ｖ족 물질을 이용한 반도체 소자 및 그 제조방법

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05129424A (ja) * 1992-04-01 1993-05-25 Ricoh Co Ltd 半導体装置とその製造方法
JP2005260240A (ja) * 2004-03-12 2005-09-22 Internatl Business Mach Corp <Ibm> ハイブリッド結晶方位基板上の集積回路構造及び形成方法（高性能ｃｍｏｓｓｏｉデバイス）
JP2006012995A (ja) * 2004-06-23 2006-01-12 Toshiba Corp 半導体装置及びその製造方法
JP2008505488A (ja) * 2004-06-30 2008-02-21 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 特徴の異なる結晶性半導体領域を有する基板の形成技術
JP2008532330A (ja) * 2005-03-07 2008-08-14 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 集積回路およびその製造方法
US7803670B2 (en) * 2006-07-20 2010-09-28 Freescale Semiconductor, Inc. Twisted dual-substrate orientation (DSO) substrates
JP2008108999A (ja) * 2006-10-27 2008-05-08 Sony Corp 半導体装置および半導体装置の製造方法
JP2008227026A (ja) * 2007-03-12 2008-09-25 Toshiba Corp 半導体装置の製造方法
JP2011035064A (ja) * 2009-07-30 2011-02-17 Renesas Electronics Corp 半導体装置、半導体基板、及び半導体基板の処理方法

Also Published As

Publication number Publication date
WO2015017283A1 (en) 2015-02-05
CN105453251A (zh) 2016-03-30
US9396931B2 (en) 2016-07-19
EP3028301A1 (en) 2016-06-08
US20150035019A1 (en) 2015-02-05
KR20160038031A (ko) 2016-04-06
CN105453251B (zh) 2019-05-28
US20160322391A1 (en) 2016-11-03

Similar Documents

Publication Publication Date Title
JP2016529708A (ja) 異なる材料から基板上にフィンを形成する方法
KR101350846B1 (ko) 스트레인 물질을 가지는 반도체 디바이스
US9425296B2 (en) Vertical tunnel field effect transistor
US8987008B2 (en) Integrated circuit layout and method with double patterning
US9293341B2 (en) Mechanisms for forming patterns using multiple lithography processes
TW201332109A (zh) 閘極對齊接觸點及其製造方法
KR20160132011A (ko) 내부에 정의된 갭을 갖는 반도체 디바이스
US20180308754A1 (en) Grid self-aligned metal via processing schemes for back end of line (beol) interconnects and structures resulting therefrom
CN107980170A (zh) 用于器件制造的通过对氧化物层的原子层去除的过渡金属干法蚀刻
US20150380257A1 (en) Method of forming finfet having fins of different height
US10181403B2 (en) Layout effect mitigation in FinFET
US10153166B2 (en) Mechanisms for forming patterns using lithography processes
US20190304890A1 (en) Alignment via-trace structures
US20200266266A1 (en) Semiconductor device with high charge carrier mobility materials on porous silicon
CN114981955B (zh) 具有高电荷迁移率沟道材料的全环绕栅极晶体管
CN104011850B (zh) 碳纳米管半导体器件和确定性纳米制造方法
CN106601680B (zh) 一种半导体器件及其制备方法、电子装置
US9431528B2 (en) Lithographic stack excluding SiARC and method of using same
CN107665824B (zh) 一种FinFET器件及制备方法、电子装置
KR20170041191A (ko) 촉매 산화물 형성에 의해 마이크로 전자 디바이스 격리를 생성하는 장치 및 방법
US11515402B2 (en) Microelectronic transistor source/drain formation using angled etching
CN107706113A (zh) 一种FinFET器件及制备方法、电子装置
CN105474369A (zh) 用于剥离掩模层的牺牲材料

Legal Events

Date Code Title Description
A529 Written submission of copy of amendment under article 34 pct

Free format text: JAPANESE INTERMEDIATE CODE: A529

Effective date: 20160121

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170704

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170704

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20180521

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20180910