KR20160038031A - 기판 상의 상이한 재료들로부터 핀들을 형성하는 방법 - Google Patents

기판 상의 상이한 재료들로부터 핀들을 형성하는 방법 Download PDF

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Publication number
KR20160038031A
KR20160038031A KR1020167005361A KR20167005361A KR20160038031A KR 20160038031 A KR20160038031 A KR 20160038031A KR 1020167005361 A KR1020167005361 A KR 1020167005361A KR 20167005361 A KR20167005361 A KR 20167005361A KR 20160038031 A KR20160038031 A KR 20160038031A
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South Korea
Prior art keywords
layer
substrate
forming
oxide layer
opening
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KR1020167005361A
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English (en)
Korean (ko)
Inventor
스탠리 승철 송
총제 왕
초 페이 옙
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퀄컴 인코포레이티드
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    • H01L21/823431—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/8258—
    • H01L21/845—
    • H01L27/1207—
    • H01L27/1211—
    • H01L29/1033—
    • H01L29/785—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292—Non-planar channels of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/011—Manufacture or treatment comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13067—FinFET, source/drain region shapes fins on the silicon surface

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020167005361A 2013-08-01 2014-07-25 기판 상의 상이한 재료들로부터 핀들을 형성하는 방법 Withdrawn KR20160038031A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/956,398 US9396931B2 (en) 2013-08-01 2013-08-01 Method of forming fins from different materials on a substrate
US13/956,398 2013-08-01
PCT/US2014/048270 WO2015017283A1 (en) 2013-08-01 2014-07-25 Method of forming fins from different materials on a substrate

Publications (1)

Publication Number Publication Date
KR20160038031A true KR20160038031A (ko) 2016-04-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020167005361A Withdrawn KR20160038031A (ko) 2013-08-01 2014-07-25 기판 상의 상이한 재료들로부터 핀들을 형성하는 방법

Country Status (6)

Country Link
US (2) US9396931B2 (enExample)
EP (1) EP3028301A1 (enExample)
JP (1) JP2016529708A (enExample)
KR (1) KR20160038031A (enExample)
CN (1) CN105453251B (enExample)
WO (1) WO2015017283A1 (enExample)

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US9129863B2 (en) 2014-02-11 2015-09-08 International Business Machines Corporation Method to form dual channel group III-V and Si/Ge FINFET CMOS
US9123585B1 (en) * 2014-02-11 2015-09-01 International Business Machines Corporation Method to form group III-V and Si/Ge FINFET on insulator
US9564518B2 (en) * 2014-09-24 2017-02-07 Qualcomm Incorporated Method and apparatus for source-drain junction formation in a FinFET with in-situ doping
US20160358827A1 (en) * 2014-10-21 2016-12-08 United Microelectronics Corp. Method of forming fin-shaped structure
US9524987B2 (en) 2014-10-21 2016-12-20 United Microelectronics Corp. Fin-shaped structure and method thereof
US9633908B2 (en) 2015-06-16 2017-04-25 International Business Machines Corporation Method for forming a semiconductor structure containing high mobility semiconductor channel materials
EP3314665A4 (en) * 2015-06-26 2019-02-20 INTEL Corporation CAVITATE-BASED INTEGRATION OF HETEROEPITACTIC N-TYPE TRANSISTORS WITH P-TYPE TRANSISTORS
US9679899B2 (en) * 2015-08-24 2017-06-13 Stmicroelectronics, Inc. Co-integration of tensile silicon and compressive silicon germanium
WO2017197589A1 (zh) 2016-05-17 2017-11-23 华为技术有限公司 一种用户面资源管理方法、用户面网元及控制面网元

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US6864581B1 (en) * 2002-08-15 2005-03-08 National Semiconductor Corporation Etched metal trace with reduced RF impendance resulting from the skin effect
US6762448B1 (en) 2003-04-03 2004-07-13 Advanced Micro Devices, Inc. FinFET device with multiple fin structures
US6921982B2 (en) * 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
US6995456B2 (en) * 2004-03-12 2006-02-07 International Business Machines Corporation High-performance CMOS SOI devices on hybrid crystal-oriented substrates
US6998684B2 (en) * 2004-03-31 2006-02-14 International Business Machines Corporation High mobility plane CMOS SOI
JP2006012995A (ja) * 2004-06-23 2006-01-12 Toshiba Corp 半導体装置及びその製造方法
WO2006007188A1 (en) * 2004-06-30 2006-01-19 Advanced Micro Devices, Inc. Technique for forming a substrate having crystalline semiconductor regions of different characteristics
DE102004057764B4 (de) 2004-11-30 2013-05-16 Advanced Micro Devices, Inc. Verfahren zur Herstellung eines Substrats mit kristallinen Halbleitergebieten mit unterschiedlichen Eigenschaften, die über einem kristallinen Vollsubstrat angeordnet sind und damit hergestelltes Halbleiterbauelement
US7422956B2 (en) 2004-12-08 2008-09-09 Advanced Micro Devices, Inc. Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers
US6972478B1 (en) * 2005-03-07 2005-12-06 Advanced Micro Devices, Inc. Integrated circuit and method for its manufacture
US7803670B2 (en) 2006-07-20 2010-09-28 Freescale Semiconductor, Inc. Twisted dual-substrate orientation (DSO) substrates
JP2008108999A (ja) * 2006-10-27 2008-05-08 Sony Corp 半導体装置および半導体装置の製造方法
JP2008227026A (ja) * 2007-03-12 2008-09-25 Toshiba Corp 半導体装置の製造方法
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Also Published As

Publication number Publication date
WO2015017283A1 (en) 2015-02-05
CN105453251A (zh) 2016-03-30
US9396931B2 (en) 2016-07-19
EP3028301A1 (en) 2016-06-08
US20150035019A1 (en) 2015-02-05
CN105453251B (zh) 2019-05-28
US20160322391A1 (en) 2016-11-03
JP2016529708A (ja) 2016-09-23

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PA0105 International application

Patent event date: 20160226

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid