JP2016522936A5 - - Google Patents

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Publication number
JP2016522936A5
JP2016522936A5 JP2016513011A JP2016513011A JP2016522936A5 JP 2016522936 A5 JP2016522936 A5 JP 2016522936A5 JP 2016513011 A JP2016513011 A JP 2016513011A JP 2016513011 A JP2016513011 A JP 2016513011A JP 2016522936 A5 JP2016522936 A5 JP 2016522936A5
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JP
Japan
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data
data entry
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JP2016513011A
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Japanese (ja)
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JP6138352B2 (ja
JP2016522936A (ja
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Priority claimed from US14/017,760 external-priority patent/US9442675B2/en
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JP2016513011A 2013-05-08 2014-05-06 データアクセスの前のメモリ内の不完全データエントリから冗長データエントリへのデータのリダイレクトならびに関連するシステムおよび方法 Expired - Fee Related JP6138352B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361820945P 2013-05-08 2013-05-08
US61/820,945 2013-05-08
US14/017,760 2013-09-04
US14/017,760 US9442675B2 (en) 2013-05-08 2013-09-04 Redirecting data from a defective data entry in memory to a redundant data entry prior to data access, and related systems and methods
PCT/US2014/036936 WO2014182678A1 (en) 2013-05-08 2014-05-06 Redirecting data from a defective data entry in memory to a redundant data entry prior to data access, and related systems and methods

Publications (3)

Publication Number Publication Date
JP2016522936A JP2016522936A (ja) 2016-08-04
JP2016522936A5 true JP2016522936A5 (enExample) 2017-01-05
JP6138352B2 JP6138352B2 (ja) 2017-05-31

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Family Applications (1)

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JP2016513011A Expired - Fee Related JP6138352B2 (ja) 2013-05-08 2014-05-06 データアクセスの前のメモリ内の不完全データエントリから冗長データエントリへのデータのリダイレクトならびに関連するシステムおよび方法

Country Status (5)

Country Link
US (1) US9442675B2 (enExample)
EP (1) EP2994914B1 (enExample)
JP (1) JP6138352B2 (enExample)
CN (1) CN105229746B (enExample)
WO (1) WO2014182678A1 (enExample)

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US10395748B2 (en) 2016-06-15 2019-08-27 Micron Technology, Inc. Shared error detection and correction memory
KR102468864B1 (ko) * 2016-07-05 2022-11-18 에스케이하이닉스 주식회사 반도체 장치, 메모리 시스템 및 그 리페어 방법
US10713136B2 (en) * 2017-09-22 2020-07-14 Qualcomm Incorporated Memory repair enablement
US11237970B2 (en) 2018-11-07 2022-02-01 Micron Technology, Inc. Reduce data traffic between cache and memory via data access of variable sizes
IT202000016441A1 (it) * 2020-07-07 2022-01-07 Sk Hynix Inc Comparatore di risorse di ridondanza per una architettura di bus, architettura di bus per un dispositivo di memoria che implementa un metodo migliorato di confronto e corrispondente metodo di confronto

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Publication number Priority date Publication date Assignee Title
JPS6177946A (ja) 1984-09-26 1986-04-21 Hitachi Ltd 半導体記憶装置
KR880008330A (ko) 1986-12-30 1988-08-30 강진구 스테이틱 램의 프리차아지 시스템
JPH02244479A (ja) 1989-03-16 1990-09-28 Fujitsu Ltd 半導体メモリ装置
US5841712A (en) 1996-09-30 1998-11-24 Advanced Micro Devices, Inc. Dual comparator circuit and method for selecting between normal and redundant decode logic in a semiconductor memory device
US6223248B1 (en) * 1997-04-29 2001-04-24 Texas Instruments Incorporated Circuits systems and methods for re-mapping memory row redundancy during two cycle cache access
US6192486B1 (en) 1998-08-13 2001-02-20 International Business Machines Corporation Memory defect steering circuit
US6324103B2 (en) 1998-11-11 2001-11-27 Hitachi, Ltd. Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device
JP2001076489A (ja) 1999-09-07 2001-03-23 Toshiba Microelectronics Corp メモリ回路
JP2001319479A (ja) 2000-05-12 2001-11-16 Nec Corp メモリ装置
EP1365419B1 (en) 2002-05-21 2008-12-31 STMicroelectronics S.r.l. Self-repair method for non volatile memory device with erasing/programming failure detection, and non volatile memory device therefor
EP1624463A1 (en) 2004-07-14 2006-02-08 STMicroelectronics S.r.l. A Programmable memory device with an improved redundancy structure
JP2007265589A (ja) 2006-03-30 2007-10-11 Fujitsu Ltd 不揮発性半導体メモリ
JP5101222B2 (ja) 2007-09-10 2012-12-19 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US7995409B2 (en) 2007-10-16 2011-08-09 S. Aqua Semiconductor, Llc Memory with independent access and precharge
US7788550B2 (en) * 2007-12-17 2010-08-31 Atmel Rousset S.A.S. Redundant bit patterns for column defects coding
US8977820B2 (en) 2007-12-21 2015-03-10 Arm Limited Handling of hard errors in a cache of a data processing apparatus
JP2009163854A (ja) * 2007-12-28 2009-07-23 Elpida Memory Inc 半導体記憶装置
US7940599B2 (en) 2009-03-16 2011-05-10 Freescale Semiconductor, Inc. Dual port memory device
JP2011123970A (ja) 2009-12-14 2011-06-23 Renesas Electronics Corp 半導体記憶装置
US8279687B2 (en) 2010-05-13 2012-10-02 International Business Machines Corporation Single supply sub VDD bit-line precharge SRAM and method for level shifting
US8228749B2 (en) 2010-06-04 2012-07-24 Texas Instruments Incorporated Margin testing of static random access memory cells
US8351287B1 (en) 2010-12-22 2013-01-08 Lattice Semiconductor Corporation Bitline floating circuit for memory power reduction
US8472271B2 (en) 2011-02-18 2013-06-25 International Business Machines Corporation Systems and methods for memory device precharging
US9455021B2 (en) 2011-07-22 2016-09-27 Texas Instruments Incorporated Array power supply-based screening of static random access memory cells for bias temperature instability
US8824230B2 (en) 2011-09-30 2014-09-02 Qualcomm Incorporated Method and apparatus of reducing leakage power in multiple port SRAM memory cell

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