CN105229746B - 在进行数据存取之前将数据从存储器中的有缺陷数据项重导向到冗余数据项，及相关系统及方法 - Google Patents

在进行数据存取之前将数据从存储器中的有缺陷数据项重导向到冗余数据项，及相关系统及方法 Download PDF

Info

Publication number
CN105229746B
CN105229746B CN201480029174.9A CN201480029174A CN105229746B CN 105229746 B CN105229746 B CN 105229746B CN 201480029174 A CN201480029174 A CN 201480029174A CN 105229746 B CN105229746 B CN 105229746B
Authority
CN
China
Prior art keywords
data item
data
address
defective
index
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201480029174.9A
Other languages
English (en)
Chinese (zh)
Other versions
CN105229746A (zh
Inventor
柴家明
葛绍平
史蒂芬·爱德华·莱尔斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105229746A publication Critical patent/CN105229746A/zh
Application granted granted Critical
Publication of CN105229746B publication Critical patent/CN105229746B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0689—Disk arrays, e.g. RAID, JBOD
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0662—Virtualisation aspects
    • G06F3/0665—Virtualisation aspects at area level, e.g. provisioning of virtual or logical volumes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
CN201480029174.9A 2013-05-08 2014-05-06 在进行数据存取之前将数据从存储器中的有缺陷数据项重导向到冗余数据项，及相关系统及方法 Expired - Fee Related CN105229746B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361820945P 2013-05-08 2013-05-08
US61/820,945 2013-05-08
US14/017,760 2013-09-04
US14/017,760 US9442675B2 (en) 2013-05-08 2013-09-04 Redirecting data from a defective data entry in memory to a redundant data entry prior to data access, and related systems and methods
PCT/US2014/036936 WO2014182678A1 (en) 2013-05-08 2014-05-06 Redirecting data from a defective data entry in memory to a redundant data entry prior to data access, and related systems and methods

Publications (2)

Publication Number Publication Date
CN105229746A CN105229746A (zh) 2016-01-06
CN105229746B true CN105229746B (zh) 2018-02-06

Family

ID=51865701

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480029174.9A Expired - Fee Related CN105229746B (zh) 2013-05-08 2014-05-06 在进行数据存取之前将数据从存储器中的有缺陷数据项重导向到冗余数据项，及相关系统及方法

Country Status (5)

Country Link
US (1) US9442675B2 (enExample)
EP (1) EP2994914B1 (enExample)
JP (1) JP6138352B2 (enExample)
CN (1) CN105229746B (enExample)
WO (1) WO2014182678A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10395748B2 (en) 2016-06-15 2019-08-27 Micron Technology, Inc. Shared error detection and correction memory
KR102468864B1 (ko) * 2016-07-05 2022-11-18 에스케이하이닉스 주식회사 반도체 장치, 메모리 시스템 및 그 리페어 방법
US10713136B2 (en) * 2017-09-22 2020-07-14 Qualcomm Incorporated Memory repair enablement
US11237970B2 (en) 2018-11-07 2022-02-01 Micron Technology, Inc. Reduce data traffic between cache and memory via data access of variable sizes
IT202000016441A1 (it) * 2020-07-07 2022-01-07 Sk Hynix Inc Comparatore di risorse di ridondanza per una architettura di bus, architettura di bus per un dispositivo di memoria che implementa un metodo migliorato di confronto e corrispondente metodo di confronto

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2165378A (en) * 1984-09-26 1986-04-09 Hitachi Ltd A semiconductor storage device
US6192486B1 (en) * 1998-08-13 2001-02-20 International Business Machines Corporation Memory defect steering circuit
CN101939792A (zh) * 2007-12-17 2011-01-05 爱特梅尔卢梭公司 用于列缺陷译码的冗余位模式

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR880008330A (ko) 1986-12-30 1988-08-30 강진구 스테이틱 램의 프리차아지 시스템
JPH02244479A (ja) 1989-03-16 1990-09-28 Fujitsu Ltd 半導体メモリ装置
US5841712A (en) 1996-09-30 1998-11-24 Advanced Micro Devices, Inc. Dual comparator circuit and method for selecting between normal and redundant decode logic in a semiconductor memory device
US6223248B1 (en) * 1997-04-29 2001-04-24 Texas Instruments Incorporated Circuits systems and methods for re-mapping memory row redundancy during two cycle cache access
US6324103B2 (en) 1998-11-11 2001-11-27 Hitachi, Ltd. Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device
JP2001076489A (ja) 1999-09-07 2001-03-23 Toshiba Microelectronics Corp メモリ回路
JP2001319479A (ja) 2000-05-12 2001-11-16 Nec Corp メモリ装置
EP1365419B1 (en) 2002-05-21 2008-12-31 STMicroelectronics S.r.l. Self-repair method for non volatile memory device with erasing/programming failure detection, and non volatile memory device therefor
EP1624463A1 (en) 2004-07-14 2006-02-08 STMicroelectronics S.r.l. A Programmable memory device with an improved redundancy structure
JP2007265589A (ja) 2006-03-30 2007-10-11 Fujitsu Ltd 不揮発性半導体メモリ
JP5101222B2 (ja) 2007-09-10 2012-12-19 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US7995409B2 (en) 2007-10-16 2011-08-09 S. Aqua Semiconductor, Llc Memory with independent access and precharge
US8977820B2 (en) 2007-12-21 2015-03-10 Arm Limited Handling of hard errors in a cache of a data processing apparatus
JP2009163854A (ja) * 2007-12-28 2009-07-23 Elpida Memory Inc 半導体記憶装置
US7940599B2 (en) 2009-03-16 2011-05-10 Freescale Semiconductor, Inc. Dual port memory device
JP2011123970A (ja) 2009-12-14 2011-06-23 Renesas Electronics Corp 半導体記憶装置
US8279687B2 (en) 2010-05-13 2012-10-02 International Business Machines Corporation Single supply sub VDD bit-line precharge SRAM and method for level shifting
US8228749B2 (en) 2010-06-04 2012-07-24 Texas Instruments Incorporated Margin testing of static random access memory cells
US8351287B1 (en) 2010-12-22 2013-01-08 Lattice Semiconductor Corporation Bitline floating circuit for memory power reduction
US8472271B2 (en) 2011-02-18 2013-06-25 International Business Machines Corporation Systems and methods for memory device precharging
US9455021B2 (en) 2011-07-22 2016-09-27 Texas Instruments Incorporated Array power supply-based screening of static random access memory cells for bias temperature instability
US8824230B2 (en) 2011-09-30 2014-09-02 Qualcomm Incorporated Method and apparatus of reducing leakage power in multiple port SRAM memory cell

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2165378A (en) * 1984-09-26 1986-04-09 Hitachi Ltd A semiconductor storage device
US6192486B1 (en) * 1998-08-13 2001-02-20 International Business Machines Corporation Memory defect steering circuit
CN101939792A (zh) * 2007-12-17 2011-01-05 爱特梅尔卢梭公司 用于列缺陷译码的冗余位模式

Also Published As

Publication number Publication date
JP6138352B2 (ja) 2017-05-31
CN105229746A (zh) 2016-01-06
JP2016522936A (ja) 2016-08-04
WO2014182678A1 (en) 2014-11-13
US9442675B2 (en) 2016-09-13
US20140337573A1 (en) 2014-11-13
EP2994914A1 (en) 2016-03-16
EP2994914B1 (en) 2019-10-16

Similar Documents

Publication Publication Date Title
KR102520152B1 (ko) 프로세서-기반 시스템들에서의 확장 dram(dynamic random access memory) 버스트 길이들의 제공
US9710324B2 (en) Dual in-line memory modules (DIMMs) supporting storage of a data indicator(s) in an error correcting code (ECC) storage unit dedicated to storing an ECC
CN109716436B (zh) 存储器系统中用以支持同时存储器读取和写入操作的单独读取和写入地址解码
US9876017B2 (en) Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells
CN105229746B (zh) 在进行数据存取之前将数据从存储器中的有缺陷数据项重导向到冗余数据项，及相关系统及方法
US9583171B2 (en) Write driver circuits for resistive random access memory (RAM) arrays
US20180074893A1 (en) Providing memory bandwidth compression in chipkill-correct memory architectures
US9806083B2 (en) Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance, and related methods
EP2976770B1 (en) Pre-charging bitlines in a static random access memory (sram) prior to data access for reducing leakage power, and related systems and methods
CN115729861A (zh) 用于向量的存储器内关联处理
US10541044B2 (en) Providing efficient handling of memory array failures in processor-based systems
US8976618B1 (en) Decoded 2N-bit bitcells in memory for storing decoded bits, and related systems and methods
JP6377084B2 (ja) キャッシュメモリアクセスを高速化するためのキャッシュメモリフィルの重要ワード優先順序付け、ならびに関連するプロセッサベースのシステムおよび方法
US20180088659A1 (en) Cache memory clock generation circuits for reducing power consumption and read errors in cache memory
US9653183B1 (en) Shared built-in self-analysis of memory systems employing a memory array tile architecture
TW201732599A (zh) 使用動態隨機存取記憶體（ｄｒａｍ）快取指示符快取以提供可擴展ｄｒａｍ快取管理
US9830965B2 (en) Multiple-hot (multi-hot) bit decoding in a memory system for activating multiple memory locations in a memory for a memory access operation
US20140293682A1 (en) Memory bitcell clusters employing localized generation of complementary bitlines to reduce memory area, and related systems and methods

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20180206

CF01 Termination of patent right due to non-payment of annual fee