JP2016528727A5 - - Google Patents

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Publication number
JP2016528727A5
JP2016528727A5 JP2016525483A JP2016525483A JP2016528727A5 JP 2016528727 A5 JP2016528727 A5 JP 2016528727A5 JP 2016525483 A JP2016525483 A JP 2016525483A JP 2016525483 A JP2016525483 A JP 2016525483A JP 2016528727 A5 JP2016528727 A5 JP 2016528727A5
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JP
Japan
Prior art keywords
ram
tier
3dic
disposed
data bank
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JP2016525483A
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English (en)
Japanese (ja)
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JP6407992B2 (ja
JP2016528727A (ja
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Priority claimed from US14/012,478 external-priority patent/US20150019802A1/en
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Publication of JP2016528727A5 publication Critical patent/JP2016528727A5/ja
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Publication of JP6407992B2 publication Critical patent/JP6407992B2/ja
Expired - Fee Related legal-status Critical Current
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JP2016525483A 2013-07-11 2014-07-10 ビットセルおよび論理区画を有するモノリシック３次元（３ｄ）ランダムアクセスメモリ（ｒａｍ）アレイアーキテクチャ Expired - Fee Related JP6407992B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361845044P 2013-07-11 2013-07-11
US61/845,044 2013-07-11
US14/012,478 US20150019802A1 (en) 2013-07-11 2013-08-28 Monolithic three dimensional (3d) random access memory (ram) array architecture with bitcell and logic partitioning
US14/012,478 2013-08-28
PCT/US2014/046152 WO2015006563A1 (en) 2013-07-11 2014-07-10 A monolithic three dimensional (3d) random access memory (ram) array architecture with bitcell and logic partitioning

Publications (3)

Publication Number Publication Date
JP2016528727A JP2016528727A (ja) 2016-09-15
JP2016528727A5 true JP2016528727A5 (enExample) 2017-07-27
JP6407992B2 JP6407992B2 (ja) 2018-10-17

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016525483A Expired - Fee Related JP6407992B2 (ja) 2013-07-11 2014-07-10 ビットセルおよび論理区画を有するモノリシック３次元（３ｄ）ランダムアクセスメモリ（ｒａｍ）アレイアーキテクチャ

Country Status (6)

Country Link
US (1) US20150019802A1 (enExample)
EP (1) EP3020045A1 (enExample)
JP (1) JP6407992B2 (enExample)
KR (1) KR20160029835A (enExample)
CN (1) CN105378843A (enExample)
WO (1) WO2015006563A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108292514B (zh) 2015-11-06 2022-04-29 卡弗科学有限公司 电熵存储器设备
US9929149B2 (en) 2016-06-21 2018-03-27 Arm Limited Using inter-tier vias in integrated circuits
CN115188591A (zh) 2016-12-02 2022-10-14 卡弗科学有限公司 存储设备和电容储能设备
GB2563473B (en) * 2017-06-15 2019-10-02 Accelercomm Ltd Polar coder with logical three-dimensional memory, communication unit, integrated circuit and method therefor
CN110603640B (zh) * 2017-07-17 2023-06-27 美光科技公司 存储器电路系统
JP7338975B2 (ja) 2018-02-12 2023-09-05 三星電子株式会社 半導体メモリ素子
FR3089678B1 (fr) 2018-12-11 2021-09-17 Commissariat Energie Atomique Memoire ram realisee sous la forme d’un circuit integre 3d
US11469214B2 (en) 2018-12-22 2022-10-11 Xcelsis Corporation Stacked architecture for three-dimensional NAND
US11139283B2 (en) 2018-12-22 2021-10-05 Xcelsis Corporation Abstracted NAND logic in stacks
EP4024222A1 (en) 2021-01-04 2022-07-06 Imec VZW An integrated circuit with 3d partitioning
CN115996200A (zh) * 2021-10-15 2023-04-21 西安紫光国芯半导体有限公司 3d-ic基带芯片、堆叠芯片及数据处理方法
US20240008239A1 (en) * 2022-07-01 2024-01-04 Intel Corporation Stacked sram with shared wordline connection
CN116741227B (zh) * 2023-08-09 2023-11-17 浙江力积存储科技有限公司 一种三维存储器架构及其操作方法和存储器

Family Cites Families (11)

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US5089993B1 (en) * 1989-09-29 1998-12-01 Texas Instruments Inc Memory module arranged for data and parity bits
JP3707888B2 (ja) * 1996-02-01 2005-10-19 株式会社日立製作所 半導体回路
US5673227A (en) * 1996-05-14 1997-09-30 Motorola, Inc. Integrated circuit memory with multiplexed redundant column data path
KR100699421B1 (ko) * 1999-02-23 2007-03-26 가부시키가이샤 히타치세이사쿠쇼 반도체집적회로장치
JP4421957B2 (ja) * 2004-06-29 2010-02-24 日本電気株式会社 ３次元半導体装置
EP2248130A1 (en) * 2008-02-19 2010-11-10 Rambus Inc. Multi-bank flash memory architecture with assignable resources
US7894230B2 (en) * 2009-02-24 2011-02-22 Mosaid Technologies Incorporated Stacked semiconductor devices including a master device
TW201207852A (en) * 2010-04-05 2012-02-16 Mosaid Technologies Inc Semiconductor memory device having a three-dimensional structure
US8273610B2 (en) * 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
JP2012083243A (ja) * 2010-10-13 2012-04-26 Elpida Memory Inc 半導体装置及びそのテスト方法
US9257152B2 (en) * 2012-11-09 2016-02-09 Globalfoundries Inc. Memory architectures having wiring structures that enable different access patterns in multiple dimensions

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