JP2016509324A5 - - Google Patents

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Publication number
JP2016509324A5
JP2016509324A5 JP2015561531A JP2015561531A JP2016509324A5 JP 2016509324 A5 JP2016509324 A5 JP 2016509324A5 JP 2015561531 A JP2015561531 A JP 2015561531A JP 2015561531 A JP2015561531 A JP 2015561531A JP 2016509324 A5 JP2016509324 A5 JP 2016509324A5
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JP
Japan
Prior art keywords
cache line
cache
data entries
memory
ordering
Prior art date
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Application number
JP2015561531A
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English (en)
Japanese (ja)
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JP6377084B2 (ja
JP2016509324A (ja
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Priority claimed from US13/925,874 external-priority patent/US20140258636A1/en
Application filed filed Critical
Publication of JP2016509324A publication Critical patent/JP2016509324A/ja
Publication of JP2016509324A5 publication Critical patent/JP2016509324A5/ja
Application granted granted Critical
Publication of JP6377084B2 publication Critical patent/JP6377084B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2015561531A 2013-03-07 2014-03-04 キャッシュメモリアクセスを高速化するためのキャッシュメモリフィルの重要ワード優先順序付け、ならびに関連するプロセッサベースのシステムおよび方法 Expired - Fee Related JP6377084B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361773951P 2013-03-07 2013-03-07
US61/773,951 2013-03-07
US13/925,874 2013-06-25
US13/925,874 US20140258636A1 (en) 2013-03-07 2013-06-25 Critical-word-first ordering of cache memory fills to accelerate cache memory accesses, and related processor-based systems and methods
PCT/US2014/020229 WO2014138029A1 (en) 2013-03-07 2014-03-04 Critical-word-first ordering of cache memory fills to accelerate cache memory accesses, and related processor-based systems and methods

Publications (3)

Publication Number Publication Date
JP2016509324A JP2016509324A (ja) 2016-03-24
JP2016509324A5 true JP2016509324A5 (enExample) 2017-03-16
JP6377084B2 JP6377084B2 (ja) 2018-08-22

Family

ID=51489354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015561531A Expired - Fee Related JP6377084B2 (ja) 2013-03-07 2014-03-04 キャッシュメモリアクセスを高速化するためのキャッシュメモリフィルの重要ワード優先順序付け、ならびに関連するプロセッサベースのシステムおよび方法

Country Status (7)

Country Link
US (1) US20140258636A1 (enExample)
EP (1) EP2965209A1 (enExample)
JP (1) JP6377084B2 (enExample)
KR (1) KR20150130354A (enExample)
CN (1) CN105027094A (enExample)
BR (1) BR112015021438A2 (enExample)
WO (1) WO2014138029A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102719242B1 (ko) * 2016-10-24 2024-10-22 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
US10599585B2 (en) * 2017-03-23 2020-03-24 Intel Corporation Least recently used-based hotness tracking mechanism enhancements for high performance caching
US10380034B2 (en) * 2017-07-14 2019-08-13 International Business Machines Corporation Cache return order optimization
KR200492757Y1 (ko) 2020-04-13 2020-12-04 주식회사 케이티 서비스 북부 Tv 셋탑박스 걸이구

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5781923A (en) * 1996-05-28 1998-07-14 Hewlett-Packard Company Adding a field to the cache tag in a computer system to indicate byte ordering
US6360297B1 (en) * 1999-11-09 2002-03-19 International Business Machines Corporation System bus read address operations with data ordering preference hint bits for vertical caches
US20040103251A1 (en) * 2002-11-26 2004-05-27 Mitchell Alsup Microprocessor including a first level cache and a second level cache having different cache line sizes
US7162583B2 (en) * 2003-12-29 2007-01-09 Intel Corporation Mechanism to store reordered data with compression
US7293141B1 (en) * 2005-02-01 2007-11-06 Advanced Micro Devices, Inc. Cache word of interest latency organization
WO2007137090A2 (en) * 2006-05-16 2007-11-29 Hercules Software, Llc Hardware support for computer speciation
US8271729B2 (en) * 2009-09-18 2012-09-18 International Business Machines Corporation Read and write aware cache storing cache lines in a read-often portion and a write-often portion

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