JP6377084B2 - キャッシュメモリアクセスを高速化するためのキャッシュメモリフィルの重要ワード優先順序付け、ならびに関連するプロセッサベースのシステムおよび方法 - Google Patents

キャッシュメモリアクセスを高速化するためのキャッシュメモリフィルの重要ワード優先順序付け、ならびに関連するプロセッサベースのシステムおよび方法 Download PDF

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JP6377084B2
JP6377084B2 JP2015561531A JP2015561531A JP6377084B2 JP 6377084 B2 JP6377084 B2 JP 6377084B2 JP 2015561531 A JP2015561531 A JP 2015561531A JP 2015561531 A JP2015561531 A JP 2015561531A JP 6377084 B2 JP6377084 B2 JP 6377084B2
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cache
cache line
memory
data entries
data
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JP2016509324A5 (enExample
JP2016509324A (ja
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シアンユ・ドン
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2015561531A 2013-03-07 2014-03-04 キャッシュメモリアクセスを高速化するためのキャッシュメモリフィルの重要ワード優先順序付け、ならびに関連するプロセッサベースのシステムおよび方法 Expired - Fee Related JP6377084B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361773951P 2013-03-07 2013-03-07
US61/773,951 2013-03-07
US13/925,874 2013-06-25
US13/925,874 US20140258636A1 (en) 2013-03-07 2013-06-25 Critical-word-first ordering of cache memory fills to accelerate cache memory accesses, and related processor-based systems and methods
PCT/US2014/020229 WO2014138029A1 (en) 2013-03-07 2014-03-04 Critical-word-first ordering of cache memory fills to accelerate cache memory accesses, and related processor-based systems and methods

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JP2016509324A JP2016509324A (ja) 2016-03-24
JP2016509324A5 JP2016509324A5 (enExample) 2017-03-16
JP6377084B2 true JP6377084B2 (ja) 2018-08-22

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JP2015561531A Expired - Fee Related JP6377084B2 (ja) 2013-03-07 2014-03-04 キャッシュメモリアクセスを高速化するためのキャッシュメモリフィルの重要ワード優先順序付け、ならびに関連するプロセッサベースのシステムおよび方法

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US (1) US20140258636A1 (enExample)
EP (1) EP2965209A1 (enExample)
JP (1) JP6377084B2 (enExample)
KR (1) KR20150130354A (enExample)
CN (1) CN105027094A (enExample)
BR (1) BR112015021438A2 (enExample)
WO (1) WO2014138029A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102719242B1 (ko) * 2016-10-24 2024-10-22 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
US10599585B2 (en) * 2017-03-23 2020-03-24 Intel Corporation Least recently used-based hotness tracking mechanism enhancements for high performance caching
US10380034B2 (en) * 2017-07-14 2019-08-13 International Business Machines Corporation Cache return order optimization
KR200492757Y1 (ko) 2020-04-13 2020-12-04 주식회사 케이티 서비스 북부 Tv 셋탑박스 걸이구

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5781923A (en) * 1996-05-28 1998-07-14 Hewlett-Packard Company Adding a field to the cache tag in a computer system to indicate byte ordering
US6360297B1 (en) * 1999-11-09 2002-03-19 International Business Machines Corporation System bus read address operations with data ordering preference hint bits for vertical caches
US20040103251A1 (en) * 2002-11-26 2004-05-27 Mitchell Alsup Microprocessor including a first level cache and a second level cache having different cache line sizes
US7162583B2 (en) * 2003-12-29 2007-01-09 Intel Corporation Mechanism to store reordered data with compression
US7293141B1 (en) * 2005-02-01 2007-11-06 Advanced Micro Devices, Inc. Cache word of interest latency organization
WO2007137090A2 (en) * 2006-05-16 2007-11-29 Hercules Software, Llc Hardware support for computer speciation
US8271729B2 (en) * 2009-09-18 2012-09-18 International Business Machines Corporation Read and write aware cache storing cache lines in a read-often portion and a write-often portion

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WO2014138029A1 (en) 2014-09-12
US20140258636A1 (en) 2014-09-11
BR112015021438A2 (pt) 2017-07-18
EP2965209A1 (en) 2016-01-13
KR20150130354A (ko) 2015-11-23
CN105027094A (zh) 2015-11-04
JP2016509324A (ja) 2016-03-24

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