KR20150130354A - 캐시 메모리 액세스들을 가속하기 위한 캐시 메모리 필들의 중요-단어-우선 순서화 및 관련된 프로세서-기반 시스템들 및 방법들 - Google Patents
캐시 메모리 액세스들을 가속하기 위한 캐시 메모리 필들의 중요-단어-우선 순서화 및 관련된 프로세서-기반 시스템들 및 방법들 Download PDFInfo
- Publication number
- KR20150130354A KR20150130354A KR1020157027402A KR20157027402A KR20150130354A KR 20150130354 A KR20150130354 A KR 20150130354A KR 1020157027402 A KR1020157027402 A KR 1020157027402A KR 20157027402 A KR20157027402 A KR 20157027402A KR 20150130354 A KR20150130354 A KR 20150130354A
- Authority
- KR
- South Korea
- Prior art keywords
- cache
- cache line
- data entries
- ordering
- word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361773951P | 2013-03-07 | 2013-03-07 | |
| US61/773,951 | 2013-03-07 | ||
| US13/925,874 | 2013-06-25 | ||
| US13/925,874 US20140258636A1 (en) | 2013-03-07 | 2013-06-25 | Critical-word-first ordering of cache memory fills to accelerate cache memory accesses, and related processor-based systems and methods |
| PCT/US2014/020229 WO2014138029A1 (en) | 2013-03-07 | 2014-03-04 | Critical-word-first ordering of cache memory fills to accelerate cache memory accesses, and related processor-based systems and methods |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20150130354A true KR20150130354A (ko) | 2015-11-23 |
Family
ID=51489354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020157027402A Withdrawn KR20150130354A (ko) | 2013-03-07 | 2014-03-04 | 캐시 메모리 액세스들을 가속하기 위한 캐시 메모리 필들의 중요-단어-우선 순서화 및 관련된 프로세서-기반 시스템들 및 방법들 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20140258636A1 (enExample) |
| EP (1) | EP2965209A1 (enExample) |
| JP (1) | JP6377084B2 (enExample) |
| KR (1) | KR20150130354A (enExample) |
| CN (1) | CN105027094A (enExample) |
| BR (1) | BR112015021438A2 (enExample) |
| WO (1) | WO2014138029A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200492757Y1 (ko) | 2020-04-13 | 2020-12-04 | 주식회사 케이티 서비스 북부 | Tv 셋탑박스 걸이구 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102719242B1 (ko) * | 2016-10-24 | 2024-10-22 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 메모리 시스템의 동작 방법 |
| US10599585B2 (en) * | 2017-03-23 | 2020-03-24 | Intel Corporation | Least recently used-based hotness tracking mechanism enhancements for high performance caching |
| US10380034B2 (en) * | 2017-07-14 | 2019-08-13 | International Business Machines Corporation | Cache return order optimization |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5781923A (en) * | 1996-05-28 | 1998-07-14 | Hewlett-Packard Company | Adding a field to the cache tag in a computer system to indicate byte ordering |
| US6360297B1 (en) * | 1999-11-09 | 2002-03-19 | International Business Machines Corporation | System bus read address operations with data ordering preference hint bits for vertical caches |
| US20040103251A1 (en) * | 2002-11-26 | 2004-05-27 | Mitchell Alsup | Microprocessor including a first level cache and a second level cache having different cache line sizes |
| US7162583B2 (en) * | 2003-12-29 | 2007-01-09 | Intel Corporation | Mechanism to store reordered data with compression |
| US7293141B1 (en) * | 2005-02-01 | 2007-11-06 | Advanced Micro Devices, Inc. | Cache word of interest latency organization |
| WO2007137090A2 (en) * | 2006-05-16 | 2007-11-29 | Hercules Software, Llc | Hardware support for computer speciation |
| US8271729B2 (en) * | 2009-09-18 | 2012-09-18 | International Business Machines Corporation | Read and write aware cache storing cache lines in a read-often portion and a write-often portion |
-
2013
- 2013-06-25 US US13/925,874 patent/US20140258636A1/en not_active Abandoned
-
2014
- 2014-03-04 EP EP14714840.7A patent/EP2965209A1/en not_active Withdrawn
- 2014-03-04 JP JP2015561531A patent/JP6377084B2/ja not_active Expired - Fee Related
- 2014-03-04 WO PCT/US2014/020229 patent/WO2014138029A1/en not_active Ceased
- 2014-03-04 BR BR112015021438A patent/BR112015021438A2/pt not_active Application Discontinuation
- 2014-03-04 CN CN201480011177.XA patent/CN105027094A/zh active Pending
- 2014-03-04 KR KR1020157027402A patent/KR20150130354A/ko not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200492757Y1 (ko) | 2020-04-13 | 2020-12-04 | 주식회사 케이티 서비스 북부 | Tv 셋탑박스 걸이구 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP2965209A1 (en) | 2016-01-13 |
| WO2014138029A1 (en) | 2014-09-12 |
| JP6377084B2 (ja) | 2018-08-22 |
| JP2016509324A (ja) | 2016-03-24 |
| BR112015021438A2 (pt) | 2017-07-18 |
| US20140258636A1 (en) | 2014-09-11 |
| CN105027094A (zh) | 2015-11-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102545726B1 (ko) | 프로세서-기반 시스템들에서 공간 QoS(Quality of Service) 태깅을 사용한 이종 메모리 시스템들의 유연한 관리의 제공 | |
| AU2022203960B2 (en) | Providing memory bandwidth compression using multiple last-level cache (llc) lines in a central processing unit (cpu)-based system | |
| KR102780546B1 (ko) | 프로세서―기반 시스템의 메모리 내의 압축된 메모리 라인들의 우선순위―기반 액세스 | |
| US10169246B2 (en) | Reducing metadata size in compressed memory systems of processor-based systems | |
| US10176090B2 (en) | Providing memory bandwidth compression using adaptive compression in central processing unit (CPU)-based systems | |
| US20180173623A1 (en) | Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compressed memory system to avoid stalling write operations | |
| JP6377084B2 (ja) | キャッシュメモリアクセスを高速化するためのキャッシュメモリフィルの重要ワード優先順序付け、ならびに関連するプロセッサベースのシステムおよび方法 | |
| US10176096B2 (en) | Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches | |
| US10152261B2 (en) | Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system | |
| BR112018069720B1 (pt) | Provisão de compactação de largura de banda de memória utilizando múltiplas linhas de cache de último nível (llc) em um sistema baseado em unidade central de processamento (cpu) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
Patent event date: 20151002 Patent event code: PA01051R01D Comment text: International Patent Application |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |