CN105027094A - 用以加速高速缓冲存储器存取的高速缓冲存储器填充的关键词优先排序以及相关基于处理器的系统及方法 - Google Patents
用以加速高速缓冲存储器存取的高速缓冲存储器填充的关键词优先排序以及相关基于处理器的系统及方法 Download PDFInfo
- Publication number
- CN105027094A CN105027094A CN201480011177.XA CN201480011177A CN105027094A CN 105027094 A CN105027094 A CN 105027094A CN 201480011177 A CN201480011177 A CN 201480011177A CN 105027094 A CN105027094 A CN 105027094A
- Authority
- CN
- China
- Prior art keywords
- cache
- cache line
- data items
- memory
- index
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361773951P | 2013-03-07 | 2013-03-07 | |
| US61/773,951 | 2013-03-07 | ||
| US13/925,874 US20140258636A1 (en) | 2013-03-07 | 2013-06-25 | Critical-word-first ordering of cache memory fills to accelerate cache memory accesses, and related processor-based systems and methods |
| US13/925,874 | 2013-06-25 | ||
| PCT/US2014/020229 WO2014138029A1 (en) | 2013-03-07 | 2014-03-04 | Critical-word-first ordering of cache memory fills to accelerate cache memory accesses, and related processor-based systems and methods |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105027094A true CN105027094A (zh) | 2015-11-04 |
Family
ID=51489354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201480011177.XA Pending CN105027094A (zh) | 2013-03-07 | 2014-03-04 | 用以加速高速缓冲存储器存取的高速缓冲存储器填充的关键词优先排序以及相关基于处理器的系统及方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20140258636A1 (enExample) |
| EP (1) | EP2965209A1 (enExample) |
| JP (1) | JP6377084B2 (enExample) |
| KR (1) | KR20150130354A (enExample) |
| CN (1) | CN105027094A (enExample) |
| BR (1) | BR112015021438A2 (enExample) |
| WO (1) | WO2014138029A1 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102719242B1 (ko) * | 2016-10-24 | 2024-10-22 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 메모리 시스템의 동작 방법 |
| US10599585B2 (en) * | 2017-03-23 | 2020-03-24 | Intel Corporation | Least recently used-based hotness tracking mechanism enhancements for high performance caching |
| US10380034B2 (en) * | 2017-07-14 | 2019-08-13 | International Business Machines Corporation | Cache return order optimization |
| KR200492757Y1 (ko) | 2020-04-13 | 2020-12-04 | 주식회사 케이티 서비스 북부 | Tv 셋탑박스 걸이구 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5781923A (en) * | 1996-05-28 | 1998-07-14 | Hewlett-Packard Company | Adding a field to the cache tag in a computer system to indicate byte ordering |
| US6360297B1 (en) * | 1999-11-09 | 2002-03-19 | International Business Machines Corporation | System bus read address operations with data ordering preference hint bits for vertical caches |
| CN1820257A (zh) * | 2002-11-26 | 2006-08-16 | 先进微装置公司 | 包括具有不同缓存线大小的第一级高速缓存及第二级高速缓存的微处理器 |
| US7162583B2 (en) * | 2003-12-29 | 2007-01-09 | Intel Corporation | Mechanism to store reordered data with compression |
| US20070294769A1 (en) * | 2006-05-16 | 2007-12-20 | Hercules Software, Llc | Hardware support for computer speciation |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7293141B1 (en) * | 2005-02-01 | 2007-11-06 | Advanced Micro Devices, Inc. | Cache word of interest latency organization |
| US8271729B2 (en) * | 2009-09-18 | 2012-09-18 | International Business Machines Corporation | Read and write aware cache storing cache lines in a read-often portion and a write-often portion |
-
2013
- 2013-06-25 US US13/925,874 patent/US20140258636A1/en not_active Abandoned
-
2014
- 2014-03-04 JP JP2015561531A patent/JP6377084B2/ja not_active Expired - Fee Related
- 2014-03-04 BR BR112015021438A patent/BR112015021438A2/pt not_active Application Discontinuation
- 2014-03-04 EP EP14714840.7A patent/EP2965209A1/en not_active Withdrawn
- 2014-03-04 CN CN201480011177.XA patent/CN105027094A/zh active Pending
- 2014-03-04 KR KR1020157027402A patent/KR20150130354A/ko not_active Withdrawn
- 2014-03-04 WO PCT/US2014/020229 patent/WO2014138029A1/en not_active Ceased
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5781923A (en) * | 1996-05-28 | 1998-07-14 | Hewlett-Packard Company | Adding a field to the cache tag in a computer system to indicate byte ordering |
| US6360297B1 (en) * | 1999-11-09 | 2002-03-19 | International Business Machines Corporation | System bus read address operations with data ordering preference hint bits for vertical caches |
| CN1820257A (zh) * | 2002-11-26 | 2006-08-16 | 先进微装置公司 | 包括具有不同缓存线大小的第一级高速缓存及第二级高速缓存的微处理器 |
| US7162583B2 (en) * | 2003-12-29 | 2007-01-09 | Intel Corporation | Mechanism to store reordered data with compression |
| US20070294769A1 (en) * | 2006-05-16 | 2007-12-20 | Hercules Software, Llc | Hardware support for computer speciation |
Non-Patent Citations (1)
| Title |
|---|
| EDMUND J.GIESKE: "Critical Words Cache Memory", 《UNIVERSITY OF CINCINNATI. THESIS》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| US20140258636A1 (en) | 2014-09-11 |
| WO2014138029A1 (en) | 2014-09-12 |
| BR112015021438A2 (pt) | 2017-07-18 |
| JP2016509324A (ja) | 2016-03-24 |
| EP2965209A1 (en) | 2016-01-13 |
| JP6377084B2 (ja) | 2018-08-22 |
| KR20150130354A (ko) | 2015-11-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102545726B1 (ko) | 프로세서-기반 시스템들에서 공간 QoS(Quality of Service) 태깅을 사용한 이종 메모리 시스템들의 유연한 관리의 제공 | |
| CN108885585B (zh) | 在基于中央处理单元(cpu)的系统中使用多个末级高速缓冲存储器(llc)线提供存储器带宽压缩 | |
| KR102780546B1 (ko) | 프로세서―기반 시스템의 메모리 내의 압축된 메모리 라인들의 우선순위―기반 액세스 | |
| KR101845371B1 (ko) | 오프-다이 캐시 메모리의 태그들의 세트들을 캐시하기 위한 방법, 장치, 및 시스템 | |
| US10169246B2 (en) | Reducing metadata size in compressed memory systems of processor-based systems | |
| KR102520152B1 (ko) | 프로세서-기반 시스템들에서의 확장 dram(dynamic random access memory) 버스트 길이들의 제공 | |
| US10176090B2 (en) | Providing memory bandwidth compression using adaptive compression in central processing unit (CPU)-based systems | |
| US20180173623A1 (en) | Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compressed memory system to avoid stalling write operations | |
| US10115444B1 (en) | Data bit inversion tracking in cache memory to reduce data bits written for write operations | |
| JP6377084B2 (ja) | キャッシュメモリアクセスを高速化するためのキャッシュメモリフィルの重要ワード優先順序付け、ならびに関連するプロセッサベースのシステムおよび方法 | |
| CN110235110A (zh) | 当停顿的写入操作发生时减少或避免来自压缩存储器系统中的未压缩高速缓冲存储器的经逐出高速缓冲存储数据的缓冲 | |
| US9442675B2 (en) | Redirecting data from a defective data entry in memory to a redundant data entry prior to data access, and related systems and methods | |
| US10176096B2 (en) | Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches | |
| US10152261B2 (en) | Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system | |
| US20170285939A1 (en) | Generating compressed data streams with lookback pre-fetch instructions for pre-fetching decompressed data from a lookback buffer | |
| BR112018069720B1 (pt) | Provisão de compactação de largura de banda de memória utilizando múltiplas linhas de cache de último nível (llc) em um sistema baseado em unidade central de processamento (cpu) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20151104 |
|
| WD01 | Invention patent application deemed withdrawn after publication |