JP2016139761A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2016139761A JP2016139761A JP2015015457A JP2015015457A JP2016139761A JP 2016139761 A JP2016139761 A JP 2016139761A JP 2015015457 A JP2015015457 A JP 2015015457A JP 2015015457 A JP2015015457 A JP 2015015457A JP 2016139761 A JP2016139761 A JP 2016139761A
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor device
- column
- surface side
- ratio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 93
- 239000012535 impurity Substances 0.000 claims description 91
- 230000000052 comparative effect Effects 0.000 description 35
- 238000005468 ion implantation Methods 0.000 description 28
- 238000000034 method Methods 0.000 description 28
- 230000015556 catabolic process Effects 0.000 description 19
- 238000009792 diffusion process Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
【解決手段】第1導電型カラムと第2導電型カラムで構成されたスーパージャンクション構造を有する半導体装置において、スーパージャンクション構造の第1面側から第2面側に向けてPN比が増加するスーパージャンクション構造の第1領域と、第1領域と接し、且つ、半導体装置のチャネル領域に隣接するスーパージャンクション構造の第2領域とを備え、第2領域におけるPN比が、第1領域の第2面側の端部におけるPN比よりも小さく、且つ、第2領域の厚さは、第1領域の厚さよりも薄い半導体装置を提供する。
【選択図】図1
Description
[先行技術文献]
[特許文献]
特許文献1 特開2006−66421号公報
特許文献2 国際公開第2011/093473号
特許文献3 特開2008−91450号公報
特許文献4 特開2004−72068号公報
特許文献5 特開2007−300034号公報
図1は、実施例1に係る半導体装置100の構造の断面の一例を示す。半導体装置100は、スーパージャンクション領域10、ドレイン領域20、チャネル領域30及びゲート・ソース領域40を備える。ドレイン領域20、チャネル領域30及びゲート・ソース領域40は、あくまで一例であり、本例の構造に限られない。
図3は、比較例1に係る半導体装置500の構成の一例を示す。本例の半導体装置500は、n型カラム51及びp型カラム52で構成されたスーパージャンクション領域50を備える。半導体装置500において、スーパージャンクション領域50以外の構造は、基本的に半導体装置100と同様である。本例のスーパージャンクション領域50は、低濃度領域53及び高濃度領域54を有する。
図5は、比較例2に係る半導体装置500の構成の一例を示す。本例の半導体装置500は、カラム傾斜領域55を有するスーパージャンクション領域50を備える。カラム傾斜領域55では、n型カラム51及びp型カラム52の側面の形状が傾斜する。
図7は、比較例3に係る半導体装置500の構成の一例を示す。本例の半導体装置500は、低濃度傾斜領域56及び高濃度傾斜領域57を有するスーパージャンクション領域50を備える。比較例3に係る半導体装置500は、比較例1及び比較例2に係る構成を組み合わせたものに相当する。
図11A〜図11Eは、多段エピタキシャル方式を用いた製造方法の一例を示す。図11Aは、実施例2に係る半導体装置100の構成の一例を示す。本例の半導体装置100は、多段エピタキシャル方式を用いて製造されたスーパージャンクション領域10を備える。
図12A〜図12Eは、トレンチ埋め込み方式を用いた製造方法の一例を示す。図12Aは、エピタキシャル成長後のスーパージャンクション領域10を示す。本例の半導体装置100は、トレンチ埋め込み方式を用いて製造されたスーパージャンクション領域10を備える。スーパージャンクション領域10は、1段でエピタキシャル成長される。
図13A〜図13Eは、トレンチ埋め込み方式を用いた製造方法の一例を示す。本例は実施例3と段差領域14の形成方法が異なる。
Claims (16)
- 第1導電型カラムと第2導電型カラムで構成されたスーパージャンクション構造を有する半導体装置において、
前記スーパージャンクション構造の第1面側から第2面側に向けてPN比が増加する前記スーパージャンクション構造の第1領域と、
前記第1領域と接し、且つ、前記半導体装置のチャネル領域に隣接する前記スーパージャンクション構造の第2領域と、
を備え、
前記第2領域におけるPN比が、前記第1領域の前記第2面側の端部におけるPN比よりも小さく、且つ、前記第2領域の厚さは、前記第1領域の厚さよりも薄い半導体装置。 - 前記第2領域の前記第1導電型及び前記第2導電型の不純物濃度は、前記第1領域の前記第1導電型及び前記第2導電型のそれぞれの不純物濃度よりも高い請求項1に記載の半導体装置。
- 前記スーパージャンクション構造において、前記第2導電型の不純物濃度の総量と前記第1導電型の不純物濃度の総量とが等しい請求項1又は2に記載の半導体装置。
- 前記第2領域において、前記第2導電型の不純物濃度が前記第1導電型の不純物濃度と等しい請求項1から3のいずれか一項に記載の半導体装置。
- 前記第1領域において、前記第1導電型の不純物濃度が一定であり、前記第2導電型の不純物濃度が前記第1面側から前記第2面側に向けて増加する請求項1から4のいずれか一項に記載の半導体装置。
- 前記第1領域のPN比が連続的に変化する請求項1から5のいずれか一項に記載の半導体装置。
- 前記第2領域のPN比が一定である請求項1から6のいずれか一項に記載の半導体装置。
- 前記第2領域のPN比が1である請求項7に記載の半導体装置。
- 前記第1領域の前記第2面側の端部におけるPN比は、1よりも大きく、且つ、1.5以下である請求項1から8のいずれか一項に記載の半導体装置。
- 前記第1領域の前記第2面側の端部におけるPN比は、1よりも大きく、且つ、1.3以下である請求項9に記載の半導体装置。
- 前記第2領域のPN比が、前記第1領域の前記第1面側の端部におけるPN比よりも大きい請求項1から10のいずれか一項に記載の半導体装置。
- 前記第2領域の前記第2導電型カラムの幅が、前記第1領域の前記第2面側の端部における前記第2導電型カラムの幅よりも小さい請求項1から11のいずれか一項に記載の半導体装置。
- 前記第2領域において、前記第2導電型カラムの幅が一定である請求項1から12のいずれか一項に記載の半導体装置。
- 前記第1領域において、前記第2導電型カラムの幅が、前記第1面側から前記第2面側に向けて大きくなる請求項1から13のいずれか一項に記載の半導体装置。
- 前記スーパージャンクション構造の第1面側にドレイン領域が形成され、前記スーパージャンクション構造の第2面側にゲート・ソース領域が形成される請求項1から14のいずれか一項に記載の半導体装置。
- 前記第1導電型はn型であり、前記第2導電型はp型である請求項1から15のいずれか一項に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015015457A JP6782529B2 (ja) | 2015-01-29 | 2015-01-29 | 半導体装置 |
US14/957,599 US10199458B2 (en) | 2015-01-29 | 2015-12-03 | Semiconductor device |
CN201510887607.0A CN105845713B (zh) | 2015-01-29 | 2015-12-07 | 半导体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015015457A JP6782529B2 (ja) | 2015-01-29 | 2015-01-29 | 半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019124100A Division JP6777198B2 (ja) | 2019-07-03 | 2019-07-03 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016139761A true JP2016139761A (ja) | 2016-08-04 |
JP6782529B2 JP6782529B2 (ja) | 2020-11-11 |
Family
ID=56554767
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015015457A Active JP6782529B2 (ja) | 2015-01-29 | 2015-01-29 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10199458B2 (ja) |
JP (1) | JP6782529B2 (ja) |
CN (1) | CN105845713B (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6254301B1 (ja) * | 2016-09-02 | 2017-12-27 | 新電元工業株式会社 | Mosfet及び電力変換回路 |
JP2019192932A (ja) * | 2019-07-03 | 2019-10-31 | 富士電機株式会社 | 半導体装置 |
CN111430449A (zh) * | 2020-04-01 | 2020-07-17 | 张清纯 | 一种mosfet器件及其制备工艺 |
JP7403643B2 (ja) | 2020-10-12 | 2023-12-22 | セミコンダクター マニュファクチュアリング エレクトロニクス(シャオシン)コーポレーション | スーパージャンクションデバイス及び製造方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6324805B2 (ja) * | 2014-05-19 | 2018-05-16 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
CN108574011A (zh) * | 2017-03-08 | 2018-09-25 | 无锡华润华晶微电子有限公司 | 垂直超结双扩散金属氧化物半导体器件及其制作方法 |
CN110212018B (zh) * | 2019-05-20 | 2022-08-16 | 上海华虹宏力半导体制造有限公司 | 超结结构及超结器件 |
CN110957351A (zh) * | 2019-12-17 | 2020-04-03 | 华羿微电子股份有限公司 | 一种超结型mosfet器件及制备方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004072068A (ja) * | 2002-06-14 | 2004-03-04 | Fuji Electric Holdings Co Ltd | 半導体素子 |
JP2004119611A (ja) * | 2002-09-25 | 2004-04-15 | Toshiba Corp | 電力用半導体素子 |
JP2006066421A (ja) * | 2004-08-24 | 2006-03-09 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2007036213A (ja) * | 2005-06-20 | 2007-02-08 | Toshiba Corp | 半導体素子 |
WO2014013888A1 (ja) * | 2012-07-19 | 2014-01-23 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4240752B2 (ja) * | 2000-05-01 | 2009-03-18 | 富士電機デバイステクノロジー株式会社 | 半導体装置 |
JP3973395B2 (ja) * | 2001-10-16 | 2007-09-12 | 株式会社豊田中央研究所 | 半導体装置とその製造方法 |
US7166890B2 (en) * | 2003-10-21 | 2007-01-23 | Srikant Sridevan | Superjunction device with improved ruggedness |
US7462909B2 (en) * | 2005-06-20 | 2008-12-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
US20080017897A1 (en) | 2006-01-30 | 2008-01-24 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing same |
JP2008091450A (ja) | 2006-09-29 | 2008-04-17 | Toshiba Corp | 半導体素子 |
JP5217257B2 (ja) * | 2007-06-06 | 2013-06-19 | 株式会社デンソー | 半導体装置およびその製造方法 |
JP4530036B2 (ja) * | 2007-12-17 | 2010-08-25 | 株式会社デンソー | 半導体装置 |
JP2009272397A (ja) * | 2008-05-02 | 2009-11-19 | Toshiba Corp | 半導体装置 |
CN102804386B (zh) * | 2010-01-29 | 2016-07-06 | 富士电机株式会社 | 半导体器件 |
JP2014060299A (ja) * | 2012-09-18 | 2014-04-03 | Toshiba Corp | 半導体装置 |
KR101514537B1 (ko) * | 2013-08-09 | 2015-04-22 | 삼성전기주식회사 | 전력 반도체 소자 및 그 제조 방법 |
-
2015
- 2015-01-29 JP JP2015015457A patent/JP6782529B2/ja active Active
- 2015-12-03 US US14/957,599 patent/US10199458B2/en active Active
- 2015-12-07 CN CN201510887607.0A patent/CN105845713B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004072068A (ja) * | 2002-06-14 | 2004-03-04 | Fuji Electric Holdings Co Ltd | 半導体素子 |
JP2004119611A (ja) * | 2002-09-25 | 2004-04-15 | Toshiba Corp | 電力用半導体素子 |
JP2006066421A (ja) * | 2004-08-24 | 2006-03-09 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2007036213A (ja) * | 2005-06-20 | 2007-02-08 | Toshiba Corp | 半導体素子 |
WO2014013888A1 (ja) * | 2012-07-19 | 2014-01-23 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6254301B1 (ja) * | 2016-09-02 | 2017-12-27 | 新電元工業株式会社 | Mosfet及び電力変換回路 |
JP2019192932A (ja) * | 2019-07-03 | 2019-10-31 | 富士電機株式会社 | 半導体装置 |
CN111430449A (zh) * | 2020-04-01 | 2020-07-17 | 张清纯 | 一种mosfet器件及其制备工艺 |
CN111430449B (zh) * | 2020-04-01 | 2023-06-02 | 清纯半导体(宁波)有限公司 | 一种mosfet器件及其制备工艺 |
JP7403643B2 (ja) | 2020-10-12 | 2023-12-22 | セミコンダクター マニュファクチュアリング エレクトロニクス(シャオシン)コーポレーション | スーパージャンクションデバイス及び製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US10199458B2 (en) | 2019-02-05 |
US20160225847A1 (en) | 2016-08-04 |
CN105845713A (zh) | 2016-08-10 |
CN105845713B (zh) | 2020-11-27 |
JP6782529B2 (ja) | 2020-11-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6782529B2 (ja) | 半導体装置 | |
JP7111681B2 (ja) | SiCベースの超接合半導体装置 | |
JP4005312B2 (ja) | 半導体構成素子の製造方法 | |
KR101795828B1 (ko) | 초접합 반도체 소자 및 제조 방법 | |
JP5052025B2 (ja) | 電力用半導体素子 | |
JP2004119611A (ja) | 電力用半導体素子 | |
CN102804385A (zh) | 半导体器件 | |
US11004963B2 (en) | Insulated gate bipolar transistor having first and second field stop zone portions and manufacturing method | |
JP6279927B2 (ja) | 絶縁ゲート型スイッチング素子を製造する方法及び絶縁ゲート型スイッチング素子 | |
JP2014236120A (ja) | 半導体装置及びその製造方法 | |
CN102254827A (zh) | 制造超结半导体器件的方法 | |
US9257503B2 (en) | Superjunction semiconductor device and method for producing thereof | |
JP5559232B2 (ja) | 電力用半導体素子 | |
JP2016039263A (ja) | 半導体装置の製造方法 | |
JP2013069786A (ja) | 電力用半導体装置 | |
JP2016527722A (ja) | Mos−バイポーラ素子 | |
JP6777198B2 (ja) | 半導体装置 | |
CN102157377B (zh) | 超结vdmos器件及其制造方法 | |
US9059237B2 (en) | Semiconductor device having an insulated gate bipolar transistor | |
JP2014179595A (ja) | 半導体装置およびその製造方法 | |
CN106783940B (zh) | 具有渐变浓度的边缘终端结构的功率半导体装置 | |
JP2015231037A (ja) | 半導体装置、及び、半導体装置の製造方法 | |
US9590093B2 (en) | Semiconductor device | |
TWI606574B (zh) | Semiconductor device | |
JP2018133476A (ja) | サイリスタ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20171214 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20181011 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20181016 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181129 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20190416 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190703 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20190712 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20190913 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200707 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20201020 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6782529 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |