JP2016092166A - 半導体装置とその製造方法 - Google Patents
半導体装置とその製造方法 Download PDFInfo
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- JP2016092166A JP2016092166A JP2014224009A JP2014224009A JP2016092166A JP 2016092166 A JP2016092166 A JP 2016092166A JP 2014224009 A JP2014224009 A JP 2014224009A JP 2014224009 A JP2014224009 A JP 2014224009A JP 2016092166 A JP2016092166 A JP 2016092166A
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- layer
- bonding layer
- joint portion
- tin
- semiconductor device
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Abstract
Description
j:電流経路の臨界電流密度
Y:電流経路の導電体のヤング率
dE:電流経路の導電体の弾性限界値
Om:電流経路の導電体の原子体積
Z*e:電流経路の実効電荷
p:電流経路の比抵抗
dx:電流経路の配線長さ
この工程では、一枚の銅板(フープ材)をプレス加工によってリードフレーム部品を作る。図13に、一枚の銅板41を示す。図13の銅板41をプレス機械で加工し、図14に示すリードフレーム部品42を製造する。リードフレーム部品42は、半導体装置2が有するリードフレーム(中間端子10、正極端子20、負極端子30、制御端子81a、制御端子81b)がランナー部42a、42bで連結された部品である。なお、リードフレーム部品42の他に、第1中継板28、第2中継板29は、このプレス工程において同じフープ材から作られる。
この工程は、プレス工程の後に実施される。この工程では、リードフレーム部品42、第1中継板28、第2中継板29の全面にニッケルメッキが施される。ニッケルメッキは、電気メッキ法で行われてもよいし、無電解ニッケルメッキ法で行われてもよい。無電解ニッケルメッキ法は、ニッケルを含むメッキ液にリードフレーム部品42などを浸すメッキ方法である。メッキ液に含まれる還元剤の酸化によって放出される電子により、リードフレーム部品42などの表面にニッケル被膜が析出される。この方法は、リードフレーム部品などの形状に関わらずに一様な厚みのニッケル被膜が形成できる利点がある。
図15と図16を参照して配置工程(S4)を説明する。この工程では、放熱板12の上にはんだ材を挟んで第1トランジスタ素子3を積層し、その上にはんだ材を挟んでスペーサ7aを積層する。第1トランジスタ素子3は、図14に示した接合予定領域Sa1に積層される。また、放熱板12の上にはんだ材を挟んで第1ダイオード素子4を積層し、その上にはんだ材を挟んでスペーサ7bを積層する。第1ダイオード素子4は、図14に示した接合予定領域Sa2に積層される。一方、放熱板22の上にはんだ材を挟んで第2トランジスタ素子5を積層し、その上にはんだ材を挟んでスペーサ7cを積層する。第2トランジスタ素子5は、図14に示した接合予定領域Sc1に積層される。また、放熱板22の上にはんだ材を挟んで第2ダイオード素子6を積層し、その上にはんだ材を挟んでスペーサ7dを積層する。第2ダイオード素子6は、図14に示した接合予定領域Sc2に積層される。次に、スペーサ7aと7bの上にはんだ材を挟んで第1中継板28を積層する。スペーサ7cと7dの上にはんだ材を挟んで第2中継板29を積層する。第2中継板29は、第2継手部26が、図14で示した接合予定領域Sbと重なるように積層される。なお、第1継手部13と第2継手部26の間にもはんだ材が挟まれる。
この工程では、図16に示した素子とリードフレーム部品42と放熱板15、25のアセンブリを高温炉に入れて所定温度で所定時間加熱する。加熱温度と加熱時間は、接合層8a−8fではスズ系はんだ材の組成が維持された層が残り、接合層8gではスズ系はんだ材の組成が維持された層が消失するように定められる。即ち、加熱は、接合層8a−8fではスズ系はんだ材の組成が維持された層が残り、接合層8gではスズ系はんだ材の組成が維持された層が消失した状態で停止される。接合層8gでは、スズ系はんだ材に含まれるスズ(Sn)の大部分が金属間化合物に変化する。配置工程にて述べたように、第1継手部13と第2継手部26の間に挟まれるはんだ材の量は、他の箇所に挟まれるはんだ材の量よりも少ないので、上記のごとく、1回の加熱で、接合層8gのみスズ系はんだ材の組成を残さず、他の接合層にスズ系はんだ材の組成が維持された層を残すことが可能となる。接合層8gのみ、はんだ材の中のスズをほぼ全て金属間化合物に変化させることで、接合層8gにおけるボイドの発生と成長が抑制される。
加熱工程にてトランジスタ素子と放熱板等が接合されたアセンブリにプライマリを塗布した後、射出成形金型に入れて樹脂製のパッケージ9を成形する。パッケージ9を成形した後のデバイスを図17に示す。最後に、リードフレーム部品42のランナー部42a、42bを図19の破線CLの箇所で切り離し、図1の半導体装置2が完成する。
3:第1トランジスタ素子
3a:コレクタ電極
4、6:ダイオード素子
5:第2トランジスタ素子
5a:エミッタ電極
7a、7b、7c、7d:スペーサ
8a:第1接合層
8g:中間接合層
9:パッケージ
10:中間端子
12、15、22、25:放熱板
13、26:継手部
19a−19f:ニッケル層
20:正極端子
28:第1中継板
29:第2中継板
30:負極端子
42:リードフレーム部品
Claims (8)
- 第1半導体素子と第2半導体素子が第1導電部材と第2導電部材で電気的に接続されている半導体装置であり、
前記第1半導体素子の表面に第1電極が配置されており、
前記第2半導体素子の表面に第2電極が配置されており、
前記第1導電部材は、前記第1電極の側で前記第1半導体素子と積層されている第1積層部と、前記第1積層部から伸びている第1継手部を有しており、
前記第2導電部材は、前記第2電極の側で前記第2半導体素子と積層されている第2積層部と、前記第2積層部から伸びているとともに前記第1継手部に対向している第2継手部を有しており、
前記第1電極と前記第1積層部が第1接合層で接合されており、
前記第2電極と前記第2積層部が第2接合層で接合されており、
前記第1継手部と前記第2継手部が中間接合層で接合されており、
接合面に垂直な方向からみたときに、前記中間接合層の面積が、前記第1接合層の面積と前記第2接合層の面積の双方よりも小さく、
前記第1継手部の前記第2継手部に対向する第1面と、当該第1面に続く側面と、前記第2継手部の前記第1継手部に対向する第2面と、当該第2面に続く側面が、ニッケル層で覆われていることを特徴とする半導体装置。 - 前記中間接合層の厚みが、前記第1接合層の厚みと前記第2接合層の厚みの双方よりも薄いことを特徴とする請求項1に記載の半導体装置。
- 前記中間接合層のヤング率が、前記第1接合層のヤング率と前記第2接合層のヤング率の双方よりも大きいことを特徴とする請求項2に記載の半導体装置。
- 前記第1接合層と前記第2接合層が、スズ系はんだ材の組成が維持された層を含んでおり、前記中間接合層が、スズの金属間化合物で構成されていることを特徴とする請求項3に記載の半導体装置。
- 前記第1接合層と前記第2接合層が、スズ系はんだ材の組成が維持された層を含んでおり、前記中間接合層が、銀と銀化合物の少なくとも一方で構成されていることを特徴とする請求項3に記載の半導体装置。
- 第1半導体素子と第2半導体素子が第1導電部材と第2導電部材で電気的に接続されている半導体装置であり、
前記第1半導体素子の表面に第1電極が形成されており、
前記第2半導体素子の表面に第2電極が形成されており、
前記第1導電部材は、前記第1電極の側で前記第1半導体素子と積層されている第1積層部と、前記第1積層部から伸びている第1継手部を有しており、
前記第2導電部材は、前記第2電極の側で前記第2半導体素子と積層されている第2積層部と、前記第2積層部から伸びているとともに前記第1継手部に対向している第2継手部を有しており、
前記第1電極と前記第1積層部が第1接合層で接合されており、
前記第2電極と前記第2積層部が第2接合層で接合されており、
前記第1継手部と前記第2継手部が中間接合層で接合されており、
接合面に垂直な方向からみたときに、前記中間接合層の面積が、前記第1接合層の面積と前記第2接合層の面積の双方よりも小さく、
前記中間接合層のヤング率が、前記第1接合層のヤング率と前記第2接合層のヤング率の双方よりも大きいことを特徴とする半導体装置。 - 請求項1に記載の半導体装置の製造方法であり、
板状部材をプレス加工して、前記第1導電部材と前記第2導電部材を成形し、
次いで、前記第1面と当該第1面に続く側面と、前記第2面と当該第2面に続く側面にニッケル層を形成することを特徴とする半導体装置の製造方法。 - 請求項6に記載の半導体装置の製造方法であり、
前記第1半導体素子と前記第2半導体素子と前記第1導電部材と前記第2導電部材を、スズ系はんだ材を挟んで前記第1半導体素子と前記第1積層部が積層され、スズ系はんだ材を挟んで前記第2半導体素子と前記第2積層部が積層され、スズ系はんだ材を挟んで前記第1継手部と前記第2継手部が対向する位置関係に配置する配置工程と、
その位置関係で加熱して前記スズ系はんだ材を溶融する加熱工程を備えており、
前記第1継手部と前記第2継手部の間に挟まれるスズ系はんだ材の量が、前記第1半導体素子と前記第1積層部の間に挟まれるスズ系はんだ材の量と、前記第2半導体素子と前記第2積層部の間に挟まれるスズ系はんだ材の量の双方よりも少なく、
前記加熱工程では、前記第1継手部と前記第2継手部の間ではスズ系はんだ材の組成が維持された層が消失し、前記第1半導体素子と前記第1積層部の間、及び、前記第2半導体素子と前記第2積層部の間に、スズ系はんだ材の組成が維持された層が残っている状態で加熱を停止することを特徴とする半導体装置の製造方法。
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AU2015252033A1 (en) | 2016-05-19 |
BR102015027684A2 (pt) | 2016-05-24 |
AU2017248560A1 (en) | 2017-11-09 |
EP3018711B1 (en) | 2019-04-17 |
CN105575937B (zh) | 2018-06-12 |
KR101759398B1 (ko) | 2017-07-31 |
JP6152842B2 (ja) | 2017-06-28 |
US9847311B2 (en) | 2017-12-19 |
BR102015027684B1 (pt) | 2020-12-08 |
EP3018711A1 (en) | 2016-05-11 |
CN105575937A (zh) | 2016-05-11 |
MY173532A (en) | 2020-01-31 |
EP3018711A8 (en) | 2016-08-10 |
AU2017248560B2 (en) | 2018-11-08 |
KR20160052434A (ko) | 2016-05-12 |
RU2612944C1 (ru) | 2017-03-14 |
US20160126205A1 (en) | 2016-05-05 |
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