JP2015508234A - 電子デバイスの三次元実装のための方法 - Google Patents

電子デバイスの三次元実装のための方法 Download PDF

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Publication number
JP2015508234A
JP2015508234A JP2014556596A JP2014556596A JP2015508234A JP 2015508234 A JP2015508234 A JP 2015508234A JP 2014556596 A JP2014556596 A JP 2014556596A JP 2014556596 A JP2014556596 A JP 2014556596A JP 2015508234 A JP2015508234 A JP 2015508234A
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JP
Japan
Prior art keywords
flake
thickness
flakes
via hole
temporary carrier
Prior art date
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Pending
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JP2014556596A
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English (en)
Japanese (ja)
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JP2015508234A5 (https=
Inventor
ムラリ，ベンカテサン
チャリ，アルビンド
プラブ，ゴパル
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GT SOLAR INCORPORATED
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GT SOLAR INCORPORATED
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Publication date
Application filed by GT SOLAR INCORPORATED filed Critical GT SOLAR INCORPORATED
Publication of JP2015508234A publication Critical patent/JP2015508234A/ja
Publication of JP2015508234A5 publication Critical patent/JP2015508234A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
JP2014556596A 2012-02-08 2013-02-05 電子デバイスの三次元実装のための方法 Pending JP2015508234A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261596696P 2012-02-08 2012-02-08
US61/596,696 2012-02-08
US13/490,460 US8629061B2 (en) 2012-02-08 2012-06-07 Method for three-dimensional packaging of electronic devices
US13/490,460 2012-06-07
PCT/US2013/024685 WO2013119514A1 (en) 2012-02-08 2013-02-05 Method for three-dimensional packaging of electronic devices

Publications (2)

Publication Number Publication Date
JP2015508234A true JP2015508234A (ja) 2015-03-16
JP2015508234A5 JP2015508234A5 (https=) 2016-03-10

Family

ID=48903255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014556596A Pending JP2015508234A (ja) 2012-02-08 2013-02-05 電子デバイスの三次元実装のための方法

Country Status (6)

Country Link
US (1) US8629061B2 (https=)
EP (1) EP2812918A4 (https=)
JP (1) JP2015508234A (https=)
KR (1) KR20140123575A (https=)
TW (1) TW201336041A (https=)
WO (1) WO2013119514A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024508510A (ja) * 2021-03-01 2024-02-27 テスラ，インコーポレイテッド ウェハ位置合わせ構造

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9576868B2 (en) * 2012-07-30 2017-02-21 General Electric Company Semiconductor device and method for reduced bias temperature instability (BTI) in silicon carbide devices
US8916038B2 (en) * 2013-03-13 2014-12-23 Gtat Corporation Free-standing metallic article for semiconductors
US8936709B2 (en) 2013-03-13 2015-01-20 Gtat Corporation Adaptable free-standing metallic article for semiconductors
TWI594380B (zh) 2015-05-21 2017-08-01 穩懋半導體股份有限公司 封裝結構及三維封裝結構
WO2019185846A1 (en) * 2018-03-29 2019-10-03 Koninklijke Philips N.V. X-ray radiation detector with a porous silicon interposer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6544862B1 (en) * 2000-01-14 2003-04-08 Silicon Genesis Corporation Particle distribution method and resulting structure for a layer transfer process
JP2004022990A (ja) * 2002-06-19 2004-01-22 Shinko Electric Ind Co Ltd シリコン基板のスルーホールプラギング方法
JP2006351935A (ja) * 2005-06-17 2006-12-28 Shinko Electric Ind Co Ltd 半導体チップ実装基板及びそれを用いた半導体装置
US20100240169A1 (en) * 2009-03-19 2010-09-23 Tswin Creeks Technologies, Inc. Method to make electrical contact to a bonded face of a photovoltaic cell
WO2011046844A1 (en) * 2009-10-12 2011-04-21 Zvi Or-Bach System comprising a semiconductor device and structure
US20110097891A1 (en) * 2009-10-26 2011-04-28 Kyu-Ha Lee Method of Manufacturing the Semiconductor Device

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US5236862A (en) 1992-12-03 1993-08-17 Motorola, Inc. Method of forming oxide isolation
US7713835B2 (en) 2006-10-06 2010-05-11 Brewer Science Inc. Thermally decomposable spin-on bonding compositions for temporary wafer bonding
US20080284037A1 (en) * 2007-05-15 2008-11-20 Andry Paul S Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers
US7825517B2 (en) 2007-07-16 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for packaging semiconductor dies having through-silicon vias
US8143511B2 (en) 2007-09-13 2012-03-27 Silicon China (Hk) Limited Texture process and structure for manufacture of composite photovoltaic device substrates
US8338209B2 (en) 2008-08-10 2012-12-25 Twin Creeks Technologies, Inc. Photovoltaic cell comprising a thin lamina having a rear junction and method of making
US8097525B2 (en) 2008-08-29 2012-01-17 International Business Machines Corporation Vertical through-silicon via for a semiconductor structure
GB0817831D0 (en) 2008-09-30 2008-11-05 Cambridge Silicon Radio Ltd Improved packaging technology
US8049327B2 (en) 2009-01-05 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with scalloped sidewalls
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
US9167694B2 (en) 2010-11-02 2015-10-20 Georgia Tech Research Corporation Ultra-thin interposer assemblies with through vias

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6544862B1 (en) * 2000-01-14 2003-04-08 Silicon Genesis Corporation Particle distribution method and resulting structure for a layer transfer process
JP2004022990A (ja) * 2002-06-19 2004-01-22 Shinko Electric Ind Co Ltd シリコン基板のスルーホールプラギング方法
JP2006351935A (ja) * 2005-06-17 2006-12-28 Shinko Electric Ind Co Ltd 半導体チップ実装基板及びそれを用いた半導体装置
US20100240169A1 (en) * 2009-03-19 2010-09-23 Tswin Creeks Technologies, Inc. Method to make electrical contact to a bonded face of a photovoltaic cell
WO2011046844A1 (en) * 2009-10-12 2011-04-21 Zvi Or-Bach System comprising a semiconductor device and structure
US20110097891A1 (en) * 2009-10-26 2011-04-28 Kyu-Ha Lee Method of Manufacturing the Semiconductor Device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024508510A (ja) * 2021-03-01 2024-02-27 テスラ，インコーポレイテッド ウェハ位置合わせ構造
JP7836326B2 (ja) 2021-03-01 2026-03-26 テスラ，インコーポレイテッド ウェハ位置合わせ構造

Also Published As

Publication number Publication date
TW201336041A (zh) 2013-09-01
EP2812918A1 (en) 2014-12-17
KR20140123575A (ko) 2014-10-22
US20130203251A1 (en) 2013-08-08
EP2812918A4 (en) 2015-09-30
WO2013119514A1 (en) 2013-08-15
US8629061B2 (en) 2014-01-14

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