KR20140123575A - 전자 디바이스들의 3차원 패키징을 위한 방법 - Google Patents

전자 디바이스들의 3차원 패키징을 위한 방법 Download PDF

Info

Publication number
KR20140123575A
KR20140123575A KR1020147025016A KR20147025016A KR20140123575A KR 20140123575 A KR20140123575 A KR 20140123575A KR 1020147025016 A KR1020147025016 A KR 1020147025016A KR 20147025016 A KR20147025016 A KR 20147025016A KR 20140123575 A KR20140123575 A KR 20140123575A
Authority
KR
South Korea
Prior art keywords
interposer
manufacturing
laminar
laminator
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020147025016A
Other languages
English (en)
Korean (ko)
Inventor
벤카테산 머랄리
아르빈드 차리
고팔 프라부
Original Assignee
지티에이티 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 지티에이티 코포레이션 filed Critical 지티에이티 코포레이션
Publication of KR20140123575A publication Critical patent/KR20140123575A/ko
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
KR1020147025016A 2012-02-08 2013-02-05 전자 디바이스들의 3차원 패키징을 위한 방법 Withdrawn KR20140123575A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261596696P 2012-02-08 2012-02-08
US61/596,696 2012-02-08
US13/490,460 US8629061B2 (en) 2012-02-08 2012-06-07 Method for three-dimensional packaging of electronic devices
US13/490,460 2012-06-07
PCT/US2013/024685 WO2013119514A1 (en) 2012-02-08 2013-02-05 Method for three-dimensional packaging of electronic devices

Publications (1)

Publication Number Publication Date
KR20140123575A true KR20140123575A (ko) 2014-10-22

Family

ID=48903255

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020147025016A Withdrawn KR20140123575A (ko) 2012-02-08 2013-02-05 전자 디바이스들의 3차원 패키징을 위한 방법

Country Status (6)

Country Link
US (1) US8629061B2 (https=)
EP (1) EP2812918A4 (https=)
JP (1) JP2015508234A (https=)
KR (1) KR20140123575A (https=)
TW (1) TW201336041A (https=)
WO (1) WO2013119514A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9576868B2 (en) * 2012-07-30 2017-02-21 General Electric Company Semiconductor device and method for reduced bias temperature instability (BTI) in silicon carbide devices
US8916038B2 (en) * 2013-03-13 2014-12-23 Gtat Corporation Free-standing metallic article for semiconductors
US8936709B2 (en) 2013-03-13 2015-01-20 Gtat Corporation Adaptable free-standing metallic article for semiconductors
TWI594380B (zh) 2015-05-21 2017-08-01 穩懋半導體股份有限公司 封裝結構及三維封裝結構
WO2019185846A1 (en) * 2018-03-29 2019-10-03 Koninklijke Philips N.V. X-ray radiation detector with a porous silicon interposer
CN116918065A (zh) * 2021-03-01 2023-10-20 特斯拉公司 晶圆对准结构

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5236862A (en) 1992-12-03 1993-08-17 Motorola, Inc. Method of forming oxide isolation
US6544862B1 (en) 2000-01-14 2003-04-08 Silicon Genesis Corporation Particle distribution method and resulting structure for a layer transfer process
JP3904484B2 (ja) * 2002-06-19 2007-04-11 新光電気工業株式会社 シリコン基板のスルーホールプラギング方法
JP2006351935A (ja) * 2005-06-17 2006-12-28 Shinko Electric Ind Co Ltd 半導体チップ実装基板及びそれを用いた半導体装置
US7713835B2 (en) 2006-10-06 2010-05-11 Brewer Science Inc. Thermally decomposable spin-on bonding compositions for temporary wafer bonding
US20080284037A1 (en) * 2007-05-15 2008-11-20 Andry Paul S Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers
US7825517B2 (en) 2007-07-16 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for packaging semiconductor dies having through-silicon vias
US8143511B2 (en) 2007-09-13 2012-03-27 Silicon China (Hk) Limited Texture process and structure for manufacture of composite photovoltaic device substrates
US8338209B2 (en) 2008-08-10 2012-12-25 Twin Creeks Technologies, Inc. Photovoltaic cell comprising a thin lamina having a rear junction and method of making
US8097525B2 (en) 2008-08-29 2012-01-17 International Business Machines Corporation Vertical through-silicon via for a semiconductor structure
GB0817831D0 (en) 2008-09-30 2008-11-05 Cambridge Silicon Radio Ltd Improved packaging technology
US8049327B2 (en) 2009-01-05 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with scalloped sidewalls
US7964431B2 (en) 2009-03-19 2011-06-21 Twin Creeks Technologies, Inc. Method to make electrical contact to a bonded face of a photovoltaic cell
US8395191B2 (en) * 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
KR101604607B1 (ko) 2009-10-26 2016-03-18 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
US9167694B2 (en) 2010-11-02 2015-10-20 Georgia Tech Research Corporation Ultra-thin interposer assemblies with through vias

Also Published As

Publication number Publication date
JP2015508234A (ja) 2015-03-16
TW201336041A (zh) 2013-09-01
EP2812918A1 (en) 2014-12-17
US20130203251A1 (en) 2013-08-08
EP2812918A4 (en) 2015-09-30
WO2013119514A1 (en) 2013-08-15
US8629061B2 (en) 2014-01-14

Similar Documents

Publication Publication Date Title
US12482776B2 (en) Metal pads over TSV
US10553562B2 (en) Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods
KR102552215B1 (ko) 마이크로 전자 어셈블리를 형성하는 방법
TWI867594B (zh) 用於簡化的輔具晶圓的dbi至矽接合
US10515926B2 (en) System and method for providing 3D wafer assembly with known-good-dies
US11097306B2 (en) Support for bonding a workpiece and method thereof
TWI445101B (zh) 暫時性半導體結構接合方法及相關經接合的半導體結構
US20120315710A1 (en) Method for producing reconstituted wafers and method for producing semiconductor devices
US20100127394A1 (en) Through substrate vias for back-side interconnections on very thin semiconductor wafers
KR20140123575A (ko) 전자 디바이스들의 3차원 패키징을 위한 방법
EP2605269A2 (en) Composite Wafer for Fabrication of Semiconductor Devices
US20120061794A1 (en) Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods
Shen et al. A clamped through silicon via (TSV) interconnection for stacked chip bonding using metal cap on pad and metal column forming in via
CN102738025A (zh) 形成键合半导体结构的方法和用该方法形成的半导体结构
CN103415917A (zh) 施加有底部填料膜的预切割的晶片
WO2012048973A1 (en) Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods
US7378331B2 (en) Methods of vertically stacking wafers using porous silicon
KR101115526B1 (ko) 관통 실리콘 비아 제조 방법
Puligadda Temporary Bonding for Enabling Three‐Dimensional Integration and Packaging
WO2022108677A1 (en) Methods of tsv formation for advanced packaging
EP3093876A1 (en) A method of separating a carrier-workpiece bonded stack
Matthias et al. Wafer-to-Wafer and Chip-to-Wafer Integration Schemes for Systems-in-a-Package and 3D Interconnects
CN103460361A (zh) 在切割胶带上施加有底部填料膜的预切割的晶片

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PC1203 Withdrawal of no request for examination

St.27 status event code: N-1-6-B10-B12-nap-PC1203

WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid
R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000