JP2015233049A - 積層デバイスの製造方法 - Google Patents
積層デバイスの製造方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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Abstract
【解決手段】第1半導体ウェーハ(10)を複数の第1デバイスチップ(15)に分割した後、第2半導体ウェーハ(20)の第2半導体デバイス(23)に対応させて第1デバイスチップを位置付けて、仮接着剤シート(41)を介してサポート基板(40)上に第1デバイスチップを接着する。次いで、第1デバイスチップの第1半導体デバイス(13)と第2半導体ウェーハ(20)の第2半導体デバイス(23)とを対応させて貼り合わせた後、第1デバイスチップからサポート基板及び仮接着剤シートを剥離する。そして、隣接する第1デバイスチップ間及び複数の第1デバイスチップを全て覆うように樹脂(51)で被覆してから平坦化した後、第1半導体デバイスの第1電極及び第2半導体デバイスの第2電極(24)を接続する。
【選択図】図11
Description
12 第1分割予定ライン
13 第1半導体デバイス
15 第1デバイスチップ
20 第2半導体ウェーハ
22 第2分割予定ライン
23 第2半導体デバイス
24 第2電極
25 第2デバイスチップ
40 サポート基板
41 仮接着剤シート
44 仮ウェーハ
50 貼り合わせウェーハ
51 樹脂
58 貫通電極
D 積層デバイス
Claims (1)
- 表面に設定された交差する複数の分割予定ラインで区画される各領域に第1半導体デバイスが形成された第1半導体ウェーハから分割された第1デバイスチップと、表面に設定された交差する複数の分割予定ラインで区画される各領域に第2半導体デバイスが形成された第2半導体ウェーハから分割された第2デバイスチップと、が積層されて形成された積層デバイスの製造方法であって、
該第1半導体ウェーハを該分割予定ラインに沿って複数の第1デバイスチップに分割する第1半導体ウェーハ分割ステップと、
該第1半導体ウェーハ分割ステップを実施した後に、平板形状のサポート基板上に、該第1デバイスチップを該第2半導体ウェーハの各該第2半導体デバイスに対応させた位置に位置付けて、第1デバイスチップの該表面側を仮接着剤を介して接着する第1デバイスチップ接着ステップと、
該第1デバイスチップ接着ステップを実施した後に、露呈する該第1デバイスチップの裏面を薄化する第1デバイスチップ薄化ステップと、
該第1デバイスチップ薄化ステップを実施した後に、該第1デバイスチップの該裏面側を該第2半導体ウェーハの該表面に対面させるとともに、該第1デバイスチップの該第1半導体デバイスと該第2半導体ウェーハの該第2半導体デバイスとを対応させて貼り合わせて、貼り合わせウェーハを形成する貼り合わせウェーハ形成ステップと、
該貼り合わせウェーハ形成ステップを実施した後に、該貼り合わせウェーハの該第1デバイスチップの該表面から該サポート基板及び該仮接着剤を剥離するサポート基板剥離ステップと、
該サポート基板剥離ステップを実施した後に、該貼り合わせウェーハの隣接する該第1デバイスチップ間及び複数の該第1デバイスチップを全て覆うように樹脂を被覆し、次いで該樹脂表面を平坦化して、該貼り合わせウェーハを樹脂で被覆する樹脂被覆ステップと、
該樹脂被覆ステップを実施した後に、該第1半導体ウェーハの該第1デバイスチップに形成された電極と該第2半導体ウェーハの各該第2半導体デバイスに形成された電極とを接続する電極接続ステップと、
該電極接続ステップを実施した後、該貼り合わせウェーハを個々の積層デバイスへと分割する分割ステップと、
を備えたことを特徴とする積層デバイスの製造方法。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20200116423A (ko) | 2019-04-01 | 2020-10-12 | 가부시기가이샤 디스코 | 적층 디바이스 칩의 제조 방법 |
JP2021536131A (ja) * | 2018-09-04 | 2021-12-23 | 中芯集成電路(寧波)有限公司 | ウェハレベルパッケージング方法およびパッケージング構造 |
KR20240033660A (ko) | 2022-09-05 | 2024-03-12 | 가부시기가이샤 디스코 | 적층 디바이스 칩의 제조 방법 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2010226060A (ja) * | 2009-03-25 | 2010-10-07 | Fujitsu Ltd | 半導体装置とその製造方法 |
JP2012134231A (ja) * | 2010-12-20 | 2012-07-12 | Disco Abrasive Syst Ltd | 積層デバイスの製造方法及び積層デバイス |
JP2012212945A (ja) * | 2012-08-08 | 2012-11-01 | Fujitsu Ltd | 半導体装置 |
JP2013256634A (ja) * | 2012-06-14 | 2013-12-26 | Daicel Corp | 半導体素子3次元実装用充填材 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2010226060A (ja) * | 2009-03-25 | 2010-10-07 | Fujitsu Ltd | 半導体装置とその製造方法 |
JP2012134231A (ja) * | 2010-12-20 | 2012-07-12 | Disco Abrasive Syst Ltd | 積層デバイスの製造方法及び積層デバイス |
JP2013256634A (ja) * | 2012-06-14 | 2013-12-26 | Daicel Corp | 半導体素子3次元実装用充填材 |
JP2012212945A (ja) * | 2012-08-08 | 2012-11-01 | Fujitsu Ltd | 半導体装置 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021536131A (ja) * | 2018-09-04 | 2021-12-23 | 中芯集成電路(寧波)有限公司 | ウェハレベルパッケージング方法およびパッケージング構造 |
KR20200116423A (ko) | 2019-04-01 | 2020-10-12 | 가부시기가이샤 디스코 | 적층 디바이스 칩의 제조 방법 |
JP2020170740A (ja) * | 2019-04-01 | 2020-10-15 | 株式会社ディスコ | 積層デバイスチップの製造方法 |
JP7235566B2 (ja) | 2019-04-01 | 2023-03-08 | 株式会社ディスコ | 積層デバイスチップの製造方法 |
TWI822984B (zh) * | 2019-04-01 | 2023-11-21 | 日商迪思科股份有限公司 | 積層器件晶片之製造方法 |
KR20240033660A (ko) | 2022-09-05 | 2024-03-12 | 가부시기가이샤 디스코 | 적층 디바이스 칩의 제조 방법 |
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