JP2015172145A - 樹脂組成物、先供給型半導体封止剤、半導体封止用フィルム、および半導体装置 - Google Patents
樹脂組成物、先供給型半導体封止剤、半導体封止用フィルム、および半導体装置 Download PDFInfo
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- JP2015172145A JP2015172145A JP2014048676A JP2014048676A JP2015172145A JP 2015172145 A JP2015172145 A JP 2015172145A JP 2014048676 A JP2014048676 A JP 2014048676A JP 2014048676 A JP2014048676 A JP 2014048676A JP 2015172145 A JP2015172145 A JP 2015172145A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Polymerisation Methods In General (AREA)
- Polymerization Catalysts (AREA)
- Graft Or Block Polymers (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
表1および2は、実施例1〜9および比較例1〜4の樹脂組成物の組成、および後述する評価の結果を示す。表1および2において、樹脂組成物の組成は質量部で表されている。
実施例1〜9および比較例1〜4に対し、実装試験を行った。試験に用いた試料は、所定の形状の半導体チップを所定の形状の基板に実装することにより作製した。基板としては、電極材料としてCuを用い表面をOSP(Organic Solderability Preservative)処理したもの(以下Cu/OSP基板という)を採用した。図2は、試料の作成に用いた基板および半導体チップの概形を示している。実装には、パナソニックファクトリーソリューションズ株式会社製のフリップチップボンダーFCB3を用いた。実装の条件は以下のとおりである。まず、基板を125℃で30分、ベークした。ベーク後、基板をステージ上に載せ、ディスペンサーで基板上に樹脂組成物を塗布した。樹脂組成物の塗布後、基板を温度70℃のステージに移し、半導体チップを基板に載せると同時に図3の温度プロファイルに従って樹脂組成物の硬化および半導体チップと基板の接合を行った。荷重は15Nであった。接合後、後硬化として、165℃で60分熱処理した。
実施例1〜9および比較例1〜4に対し、吸湿リフロー試験を行った。実装性の評価に用いた試料のうち5つ(半導体チップを研磨していないもの)の試料を、温度30℃、相対湿度60%の恒温恒湿槽に入れ、192時間、吸湿させた。吸湿後、最高温度260℃のリフロー炉に、試料を3回繰り返して通過させた後で、超音波画像観察を行った。超音波画像観察においてデラミネーション(樹脂組成物の剥がれ)が起きていたものを不良品と判断した。また、超音波画像観察に加え、抵抗値測定を行った。抵抗値測定においては、実装性の評価における抵抗値測定と同様、28〜32Ωの抵抗値を示したものを良品と判断し、この範囲外の抵抗値を示したものを不良品と判断した。
実施例1〜9および比較例1〜4に対し、接続安定性を評価する目的でヒートサイクル試験を行った。吸湿リフロー試験に使用した試料を、気槽ヒートサイクル試験機において試験した。試験条件は、高温125℃、低温−55℃に各30分さらすものであった。500サイクル毎に試料を取り出し、超音波画像観察および抵抗値測定を行った。超音波画像観察においてデラミネーションが起きていたものを不良品と判断した。また、抵抗値測定においては、28〜32Ωの抵抗値を示したものを良品と判断し、この範囲外の抵抗値を示したものを不良品と判断した。
Claims (8)
- (A)2官能以上の(メタ)アクリレートと、
(B)無水マレイン酸変性したポリブタジエンと、
(C)有機過酸化物と、
(D)シリカフィラーと、
(E)シランカップリング剤と、
(F)融点が45℃以下のイミダゾール化合物と、
(G)式(1)の化合物と
- (A)2官能以上の(メタ)アクリレートと、
(B)無水マレイン酸変性したポリブタジエンと、
(C)有機過酸化物と、
(D)シリカフィラーと、
(E)シランカップリング剤と、
(F)融点が45℃以下のイミダゾール化合物と、
(G)式(2)の化合物と
- 前記(A)が、式(3)の化合物(ただし、R1およびR2は、それぞれ水素原子またはメチル基である)および式(4)の化合物の少なくとも一方を含む
- 前記(C)が、式(5)の化合物および式(6)の化合物の少なくとも一方を含む
- 前記(G)に対する前記(F)の質量比が、0.1〜1の範囲である
ことを特徴とする請求項1ないし4のいずれか一項に記載の樹脂組成物。 - 請求項1ないし5いずれか一項に記載の樹脂組成物を含む先供給型半導体封止剤。
- 請求項1ないし5のいずれか一項に記載の樹脂組成物を含む半導体封止用フィルム。
- 請求項6に記載の先供給型半導体封止剤または請求項7に記載の半導体封止用フィルムを用いて封止された半導体素子を有する半導体装置。
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Cited By (3)
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JP2017103303A (ja) * | 2015-11-30 | 2017-06-08 | 日立化成株式会社 | 半導体用接着剤、半導体装置、及び半導体装置の製造方法 |
WO2019208614A1 (ja) | 2018-04-26 | 2019-10-31 | 三菱瓦斯化学株式会社 | 樹脂組成物、積層体、樹脂組成物層付き半導体ウェハ、樹脂組成物層付き半導体搭載用基板、及び半導体装置 |
US11053382B2 (en) | 2016-05-31 | 2021-07-06 | Mitsubishi Gas Chemical Company, Inc. | Resin composition, laminate, semiconductor wafer with resin composition layer, substrate for mounting semiconductor with resin composition layer, and semiconductor device |
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JP2017103303A (ja) * | 2015-11-30 | 2017-06-08 | 日立化成株式会社 | 半導体用接着剤、半導体装置、及び半導体装置の製造方法 |
US11053382B2 (en) | 2016-05-31 | 2021-07-06 | Mitsubishi Gas Chemical Company, Inc. | Resin composition, laminate, semiconductor wafer with resin composition layer, substrate for mounting semiconductor with resin composition layer, and semiconductor device |
KR20210093381A (ko) | 2016-05-31 | 2021-07-27 | 미츠비시 가스 가가쿠 가부시키가이샤 | 수지 조성물, 적층체, 수지 조성물층이 부착된 반도체 웨이퍼, 수지 조성물층이 부착된 반도체 탑재용 기판 및 반도체 장치 |
WO2019208614A1 (ja) | 2018-04-26 | 2019-10-31 | 三菱瓦斯化学株式会社 | 樹脂組成物、積層体、樹脂組成物層付き半導体ウェハ、樹脂組成物層付き半導体搭載用基板、及び半導体装置 |
KR20210004971A (ko) | 2018-04-26 | 2021-01-13 | 미츠비시 가스 가가쿠 가부시키가이샤 | 수지 조성물, 적층체, 수지 조성물층이 부착된 반도체 웨이퍼, 수지 조성물층이 부착된 반도체 탑재용 기판, 및 반도체 장치 |
US11935803B2 (en) | 2018-04-26 | 2024-03-19 | Mitsubishi Gas Chemical Company, Inc. | Resin composition, laminate, semiconductor wafer with resin composition layer, substrate for mounting semiconductor with resin composition layer and semiconductor device |
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