JP2015084412A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with a transistor having a high on-state current and a low off-state current; and provide a semiconductor device having stable electrical characteristics.SOLUTION: A semiconductor device uses a gate electrode having Gibbs free energy of oxidation reaction higher than that of a gate insulation film. A manufacturing method of the semiconductor device comprises the steps of: forming a fin-shaped oxide semiconductor on an insulating surface; forming a gate insulation film on the oxide semiconductor; forming a gate electrode which faces a top face and a lateral face of the oxide semiconductor via the gate insulation film and at least includes an oxide layer; and subsequently performing a heat treatment to reduce the gate electrode and to supply oxygen to the oxide semiconductor via the gate insulation film.

Description

The present invention relates to an object, a method, or a manufacturing method. Alternatively, the present invention relates to a process, machine, manufacture, or composition (composition of matter). One embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A display device, an electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.

In recent years, with higher integration of integrated circuits (ICs), miniaturization of transistors has been demanded. However, as transistors are miniaturized, a decrease in on-current due to parasitic resistance and deterioration of subthreshold characteristics have become apparent. . In order to overcome the above-described problems, a transistor in which a semiconductor is processed into a three-dimensional shape called a fin (Fin) and its upper surface and side surfaces are surrounded by a gate electrode has been proposed as a transistor mainly using silicon (non-patent document). Document 1, Non-Patent Document 2).

As another semiconductor applicable to a transistor, an oxide semiconductor has attracted attention. Transistors using oxide semiconductors are easier to manufacture, operate faster than transistors using amorphous silicon, and have very low off-state leakage current. Therefore, integrated circuits and image display devices (also simply referred to as display devices) Application is expected.

Oxygen deficiency existing in the oxide semiconductor film and at the interface is known to fluctuate the electrical characteristics of the transistor, but by supplying oxygen effectively to the oxide semiconductor interface and film, It is known that the above problems can be overcome. As a method for supplying oxygen to an oxide semiconductor, a method for supplying oxygen from an insulator in contact with the oxide semiconductor (Patent Document 1) and a method for supplying oxygen from a gate electrode (Patent Document 2) are disclosed.

JP 2012-009836 A JP 2013-131740 A

IEEE Electron Device Letters Vol. 11, pp. 36-39, 1990 IEEE International Electron Devices Meeting Technical Digest, pp. 1032-1034, 1998

An object of one embodiment of the present invention is to provide a semiconductor device with high on-state current and low off-state current. Another object is to provide a semiconductor device having stable electrical characteristics. Another object is to provide a novel semiconductor device.

Note that the description of a plurality of tasks does not disturb each other's existence. Note that one embodiment of the present invention does not have to solve all of these problems. Problems other than those listed will be apparent from descriptions of the specification, drawings, claims, and the like, and these problems may also be a problem of one embodiment of the present invention.

One embodiment of the present invention is a semiconductor device including an oxide semiconductor, a gate electrode, and a gate insulating film, in which the oxide semiconductor has a fin shape, and the gate electrode includes an upper surface and a side surface of the oxide semiconductor. The gate insulating film is provided between the oxide semiconductor and the gate electrode. The gate electrode includes at least a first layer and a second layer, the first layer of the gate electrode is in contact with the gate insulating film, and the first layer of the gate electrode is the second layer of the gate electrode. It is preferable that the oxygen concentration is lower than that.

In the above aspect, the first layer of the gate electrode is preferably made of a material having a higher Gibbs free energy for oxidation reaction than the gate insulating film.

In the above embodiment, the first layer of the gate electrode preferably contains one or more elements selected from silver, copper, ruthenium, iridium, platinum, and gold.

In the above embodiment, the gate insulating film preferably has oxygen permeability.

One embodiment of the present invention is a semiconductor device including an oxide semiconductor, a first gate electrode, a second gate electrode, a first gate insulating film, and a second gate insulating film, The oxide semiconductor has a fin shape, the first gate electrode faces the top surface and the side surface of the oxide semiconductor, the second gate electrode faces the bottom surface of the oxide semiconductor, and the first gate insulating film Is provided between the oxide semiconductor and the first gate electrode, and the second gate insulating film is provided between the oxide semiconductor and the second gate electrode. The first gate electrode includes at least a first layer and a second layer, and the second gate electrode includes at least a first layer and a second layer, and the first gate electrode includes a first gate electrode. The first layer of the second gate electrode is in contact with the second gate insulating film, and the first layer of the first gate electrode is in contact with the first gate insulating film. Preferably, the oxygen concentration is lower than the second layer of the electrode, and the first layer of the second gate electrode has a lower oxygen concentration than the second layer of the second gate electrode.

In the above aspect, the first layer of the first gate electrode is preferably made of a material having a higher Gibbs free energy for oxidation reaction than the first gate insulating film. The first layer of the second gate electrode is preferably made of a material having a higher Gibbs free energy for oxidation reaction than the second gate insulating film.

In the above aspect, the first layer of the first gate electrode and the first layer of the second gate electrode preferably include one or more elements selected from silver, copper, ruthenium, iridium, platinum, and gold. .

In the above embodiment, it is preferable that the first gate insulating film and the second gate insulating film have oxygen permeability.

One embodiment of the present invention is an electronic device including the semiconductor device described in the above embodiment and at least one of a microphone, a speaker, and an operation key.

According to one embodiment of the present invention, an oxide semiconductor having a fin shape is formed, a gate insulating film is formed over the oxide semiconductor, and the gate electrode including at least the oxide layer is interposed between the oxide semiconductor and the oxide semiconductor. A method for manufacturing a semiconductor device is characterized in that oxygen is supplied from the gate electrode to the oxide semiconductor through the gate insulating film by performing heat treatment so as to face the upper surface and the side surface of the semiconductor device.

According to one embodiment of the present invention, a second gate electrode including at least an oxide layer is formed, a second gate insulating film is formed over the second gate electrode, and the second gate insulating film is formed over the second gate insulating film. An oxide semiconductor having a fin shape is formed so as to overlap with the gate electrode of 2, a first gate insulating film is formed over the oxide semiconductor, and the first gate electrode including at least the oxide layer is formed as the first gate electrode. The oxide semiconductor is formed so as to face the top surface and the side surface of the oxide semiconductor through the gate insulating film, and is subjected to heat treatment, whereby oxygen is transferred from the first gate electrode to the oxide semiconductor through the first gate insulating film. And at the same time oxygen is supplied from the second gate electrode to the oxide semiconductor through the second gate insulating film.

According to one embodiment of the present invention, a semiconductor device with high on-state current and low off-state current can be provided. Further, according to one embodiment of the present invention, a semiconductor device having stable electric characteristics can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a stacked structure included in a semiconductor device of one embodiment of the present invention. 10A to 10D are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 10A to 10D are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 10A to 10D are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. 4A and 4B are a cross-sectional view and a circuit diagram of a semiconductor device according to an embodiment. 4 illustrates a configuration example of a storage device according to an embodiment. 4 shows a configuration example of an RFID tag according to an embodiment. The structural example of CPU which concerns on embodiment. FIG. 6 is a circuit diagram of a memory element according to an embodiment. An electronic device according to an embodiment. The usage example of RFID based on Embodiment. The figure which shows the Gibbs free energy of an oxidation reaction. The figure which shows the result of a TDS analysis. 6A and 6B illustrate oxygen diffusion in a silicon oxide film. FIG. 9 shows a nanobeam electron diffraction pattern of an oxide semiconductor film. The figure which shows an example of a transmission electron diffraction measuring apparatus. The figure which shows an example of the structural analysis by a transmission electron diffraction measurement. 4A and 4B are a configuration example and a circuit diagram of a display device according to an embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments and examples. In the embodiments and examples described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

Note that in each drawing described in this specification, the size, the film thickness, or the region of each component is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale.

In addition, the first and second ordinal numbers used in this specification are given in order to avoid confusion between components, and are not limited in number. Therefore, for example, “first” can be described by appropriately replacing “second” or “third”.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. The functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

(Embodiment 1)
In this embodiment, a transistor according to one embodiment of the present invention will be described with reference to FIGS.

1A and 1B are a top view and a cross-sectional view of a transistor of one embodiment of the present invention. 1A is a top view, and FIG. 1B is a cross-sectional view corresponding to a dashed-dotted line A1-A2 and a dashed-dotted line A3-A4 illustrated in FIG. Note that in the top view of FIG. 1A, some elements are omitted for clarity.

1A and 1B includes a substrate 400, a base insulating film 402 having a convex portion over the substrate 400, an oxide semiconductor 404 over the convex portion of the base insulating film 402, and an oxide film. A source electrode 406a and a drain electrode 406b in contact with an upper surface and a side surface of the physical semiconductor 404; a gate insulating film 408 on the oxide semiconductor 404; a source electrode 406a and a drain electrode 406b; and an upper surface of the gate insulating film 408; A gate electrode 410 facing the top and side surfaces of the physical semiconductor 404, and a protective insulating film 412 over the source electrode 406a, the drain electrode 406b, and the gate electrode 410. The gate electrode 410 includes a conductive film 410a, The conductive film 410a is a stacked film including the conductive film 410b. Note that the base insulating film 402 is not necessarily provided with a convex portion.

Note that at least part (or all) of the source electrode 406a (or / and the drain electrode 406b) is at least part (or all) of a surface, a side surface, an upper surface, and / or a lower surface of a semiconductor such as the oxide semiconductor 404. ).

Alternatively, at least part (or all) of the source electrode 406a (or / and the drain electrode 406b) is at least part (or all) of a surface, a side surface, an upper surface, and / or a lower surface of a semiconductor such as the oxide semiconductor 404. ). Alternatively, at least part (or all) of the source electrode 406a (or / and the drain electrode 406b) is in contact with at least part (or all) of a semiconductor such as the oxide semiconductor 404.

Alternatively, at least part (or all) of the source electrode 406a (or / and the drain electrode 406b) is at least part (or all) of a surface, a side surface, an upper surface, and / or a lower surface of a semiconductor such as the oxide semiconductor 404. ) And are electrically connected. Alternatively, at least part (or all) of the source electrode 406a (or / and the drain electrode 406b) is electrically connected to at least part (or all) of a semiconductor such as the oxide semiconductor 404.

Alternatively, at least part (or all) of the source electrode 406a (or / and the drain electrode 406b) is at least part (or all) of a surface, a side surface, an upper surface, and / or a lower surface of a semiconductor such as the oxide semiconductor 404. ). Alternatively, at least a part (or all) of the source electrode 406a (or / and the drain electrode 406b) is disposed in proximity to at least a part (or all) of a semiconductor such as the oxide semiconductor 404.

Alternatively, at least part (or all) of the source electrode 406a (or / and the drain electrode 406b) is at least part (or all) of a surface, a side surface, an upper surface, and / or a lower surface of a semiconductor such as the oxide semiconductor 404. ). Alternatively, at least a part (or all) of the source electrode 406a (or / and the drain electrode 406b) is disposed on the side of at least a part (or all) of a semiconductor such as the oxide semiconductor 404.

Alternatively, at least part (or all) of the source electrode 406a (or / and the drain electrode 406b) is at least part (or all) of a surface, a side surface, an upper surface, and / or a lower surface of a semiconductor such as the oxide semiconductor 404. ) Diagonally above. Alternatively, at least part (or all) of the source electrode 406 a (or / and the drain electrode 406 b) is disposed obliquely above at least part (or all) of a semiconductor such as the oxide semiconductor 404.

Alternatively, at least part (or all) of the source electrode 406a (or / and the drain electrode 406b) is at least part (or all) of a surface, a side surface, an upper surface, and / or a lower surface of a semiconductor such as the oxide semiconductor 404. ) Above. Alternatively, at least part (or all) of the source electrode 406 a (or / and the drain electrode 406 b) is disposed above at least part (or all) of a semiconductor such as the oxide semiconductor 404.

The substrate 400 is not limited to a simple support, and may be a substrate on which other elements such as transistors and capacitors are formed. In this case, at least one of the gate electrode 410, the source electrode 406a, and the drain electrode 406b of the transistor may be electrically connected to the other element.

The base insulating film 402 can serve to prevent diffusion of impurities from the substrate 400 and can also serve to supply oxygen to the oxide semiconductor 404. Therefore, the base insulating film 402 is preferably an insulator containing oxygen. For example, an insulator containing more oxygen than the stoichiometric composition is more preferable. In addition, when the substrate 400 is a substrate over which another element is formed as described above, the base insulating film 402 also has a function as a protective insulating film. In that case, the surface of the base insulating film 402 may be planarized. For example, planarization treatment may be performed on the base insulating film 402 by a CMP (Chemical Mechanical Polishing) method or the like.

As illustrated in FIG. 1B, the oxide semiconductor 404 is formed in a fin shape, and the oxide semiconductor 404 is surrounded by the gate electrode 410; (A transistor structure in which an oxide semiconductor is electrically surrounded by an electric field of a gate electrode is referred to as a surrounded channel (s-channel) structure). In the s-channel structure, a channel is formed in the whole (bulk) of the oxide semiconductor 404. Therefore, the s-channel structure has a high driving capability and a problem when a transistor is miniaturized. It is possible to prevent an increase in leakage current (off current) due to (Drain Induced Barrier Lowering). Therefore, it can be said that the s-channel structure is suitable for a miniaturized transistor. For example, the channel length of the transistor is preferably 40 nm or less, more preferably 30 nm or less, more preferably 20 nm or less, and the fin width is preferably 40 nm or less, more preferably 30 nm or less, more preferably 20 nm or less. .

Note that the channel length refers to a distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where the semiconductor and the gate electrode overlap with each other in the top view. That is, in FIG. 1A, the channel length is a distance between the source electrode 406a and the drain electrode 406b in a region where the oxide semiconductor 404 and the gate electrode 410 overlap with each other. The fin width refers to the width w of the oxide semiconductor 404 illustrated in FIGS.

The fin shape refers to a shape in which the height h of the oxide semiconductor 404 illustrated in FIG. 1B is greater than or equal to the width w of the oxide semiconductor 404 illustrated in FIG.

In a transistor with an s-channel structure, when a higher on-state current is desired, the height h of the oxide semiconductor 404 needs to be higher. However, the higher the height h, the more difficult it is for oxygen supplied from the base insulating film 402 to be distributed throughout the oxide semiconductor 404, so that oxygen vacancies are generated in the oxide semiconductor 404. Oxygen deficiency causes the electrical characteristics of the transistor to fluctuate.

In this embodiment mode, a method for solving the above-described problem by providing the gate electrode 410 with an oxygen supply capability will be described. In addition to the base insulating film 402, the gate electrode 410 has an oxygen supply capability, so that oxygen can be supplied to the entire oxide semiconductor 404 even when the height h is increased. It is possible to achieve both stable operation. Details will be described below.

The conductive film 410a of the gate electrode 410 is a conductive film containing oxygen and is made of a material having a higher Gibbs free energy for oxidation reaction than the gate insulating film 408. That is, the conductive film 410a has a property of being more easily reduced than the gate insulating film 408. In other words, the conductive film 410 a has a property that it is less likely to be oxidized than the gate insulating film 408. The thickness of the conductive film 410a is preferably 5 nm to 100 nm, more preferably 10 nm to 50 nm, and still more preferably 10 nm to 30 nm.

The conductive film 410b of the gate electrode 410 is made of a material having higher conductivity than the conductive film 410a. In addition, the conductive film 410b is preferably formed using a material having a Gibbs free energy for oxidation reaction that is equal to or higher than that of the conductive film 410a. In other words, the conductive film 410b preferably has a property that the conductive film 410b is less likely to be oxidized than the conductive film 410a. The thickness of the conductive film 410b is preferably 10 nm to 200 nm, more preferably 30 nm to 100 nm.

The gate insulating film 408 has oxygen permeability. A film having oxygen permeability refers to a film that transmits oxygen molecules or a film that has a sufficiently high diffusion coefficient of oxygen atoms and allows oxygen atoms to pass through heat treatment or the like in a manufacturing process. For example, a film that transmits oxygen molecules may have a low density that allows oxygen molecules to pass through. Specifically, the film density may be less than 3.2 g / cm ³ . In addition, a film through which oxygen atoms permeate has a diffusion coefficient of oxygen atoms at 150 ° C. to 450 ° C. of 3 × 10 ⁻¹⁶ cm ² / sec or more, preferably 1 ×, although it depends on the thickness of the gate insulating film 408. It may be 10 ⁻¹⁵ cm ² / second or more, more preferably 8 × 10 ⁻¹⁵ cm ² / second or more.

Since the conductive film 410a containing oxygen is formed using a substance that is more easily reduced than the gate insulating film 408, the conductive film 410a is reduced when heat treatment is performed. As a result, the conductive film 410a releases oxygen. At this time, the conductive film 410b does not deprive oxygen released from the conductive film 410a, and even if deprived, the amount is extremely small. Oxygen released from the conductive film 410 a can pass through the gate insulating film 408 and reach the oxide semiconductor 404.

Note that the heat treatment may be performed at a temperature of 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, or a reduced pressure state.

By using the gate electrode 410 and the gate insulating film 408 as described above, oxygen can be supplied from the gate electrode 410 to the oxide semiconductor 404 through the gate insulating film 408.

For reference, FIG. 14 shows the Gibbs free energy of the oxidation reaction of each element. The horizontal axis of FIG. 14 is temperature [° C.], and the vertical axis is Gibbs free energy (ΔG [kJ / mol]). The Gibbs free energy of the oxidation reaction shown in FIG. 14 is obtained by the following calculation. First, by using the values of standard production enthalpy ΔH and standard entropy S in each substance shown in Table 1 and substituting them into the formulas of each oxidation reaction shown in Table 2, standard production enthalpy ΔH and standard production entropy in each oxidation reaction The value of ΔS is calculated. Table 2 shows the calculated standard production enthalpy ΔH and standard production entropy ΔS in each oxidation reaction. The values of standard generation enthalpy ΔH and standard entropy S for each substance shown in Table 1 are mainly quoted from “Chemical Handbook Basic Edition II Revised 4th Edition, Maruzen Co., Ltd.” edited by the Chemical Society of Japan.

Next, the values of the standard production enthalpy ΔH and the standard production entropy ΔS shown in Table 2 are substituted into the following formula (1), and the Gibbs free energy values of the respective oxidation reactions in the temperature range of 0 ° C. or higher and 900 ° C. or lower. Was calculated. Note that T in Equation (1) is the temperature [K].

From FIG. 14, for example, the conductive film 410a may be a layer formed of an oxide containing one or more elements selected from silver, copper, ruthenium, iridium, platinum, and gold. Since the oxide containing the element has high Gibbs free energy for the oxidation reaction, the oxide itself is easily reduced and the film in contact with the oxide is easily oxidized. Note that an oxide containing ruthenium or iridium is preferably used because of high conductivity. Examples of the oxide containing ruthenium or iridium include RuO _X (X is 0.5 or more and 4 or less), IrO _X (X is 0.5 or more and 4 or less), SrRuO _X (X is 1 or more and 5 or less), and the like. Can be mentioned.

The conductive film 410b is a layer containing one or more elements selected from silver, copper, ruthenium, iridium, molybdenum, tungsten, platinum, and gold, or a metal nitride. The conductive film 410b may have a multilayer structure in order to improve conductivity. In that case, the layer that is not in contact with the conductive film 410a may not contain the above-described element and metal nitride.

The gate insulating film 408 is selected from one or more insulators including silicon oxide, silicon oxynitride, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and is used as a single layer or a stacked layer. That's fine.

FIG. 1C shows a state after the heat treatment is performed to reduce the conductive film 410a.

A gate electrode 411 illustrated in FIG. 1C includes a conductive film 411a, a conductive film 411b, and a conductive film 411c which are sequentially stacked from the bottom. In FIG. 1C, structures other than the gate electrode 411 are the same as those in FIG.

The conductive film 411a is a layer having a lower oxygen concentration than the conductive film 411b, and the conductive film 411c is a layer having higher conductivity than the conductive films 411a and 411b.

The conductive film 410a illustrated in FIG. 1B is subjected to heat treatment so that a region in the vicinity of the gate insulating film 408 is reduced, and a conductive film 411a in which an oxygen concentration is lower than that of the conductive film 410a and the conductive film 410a. It changes to the conductive film 411b having the same oxygen concentration. The conductive film 410b becomes a conductive film 411c with no particular change.

The thickness of the conductive film 411a is preferably 1 nm or more and 50 nm or less, more preferably 1 nm or more and 30 nm or less, and further preferably 1 nm or more and 15 nm or less.

The thickness of the conductive film 411b is preferably 1 nm to 100 nm, more preferably 1 nm to 50 nm, and still more preferably 1 nm to 30 nm.

For the thickness of the conductive film 411c, the description relating to the thickness of the conductive film 410b may be referred to.

Note that depending on the conditions of the heat treatment, the entire region of the conductive film 410a may be changed to the conductive film 411a. That is, the conductive film 411b may not be formed by heat treatment.

As the conductive film 411a of the gate electrode 411, a material having a work function of 5 eV, preferably more than 5.2 eV, such as iridium, platinum, ruthenium oxide, or gold, is used. Compared to the case, the threshold voltage of the NMOS transistor can be shifted in the positive direction, which is preferable.

For the source electrode 406a and the drain electrode 406b illustrated in FIGS. 1A and 1B, a conductive film having a property of extracting oxygen from an oxide semiconductor is preferably used. For example, as a conductive film having a property of extracting oxygen from an oxide semiconductor, a conductive film containing aluminum, titanium, chromium, nickel, molybdenum, tantalum, tungsten, or the like can be given.

In some cases, oxygen in the oxide semiconductor is released by the action of the conductive film having a property of extracting oxygen from the oxide semiconductor, so that an oxygen vacancy is formed in the oxide semiconductor. The extraction of oxygen is more likely to occur as the temperature is higher. Since there are several heating steps in the manufacturing process of the transistor, there is a high possibility that oxygen vacancies are formed in a region in contact with the source electrode or the drain electrode of the oxide semiconductor. In addition, hydrogen may enter the oxygen deficient site by heating, so that the oxide semiconductor becomes n-type. Therefore, by the action of the source electrode and the drain electrode, the resistance of the region where the oxide semiconductor is in contact with the source electrode or the drain electrode can be reduced, so that the on-resistance of the transistor can be reduced.

Note that in the case where a transistor with a small channel length (for example, 200 nm or less or 100 nm or less) is manufactured, the source and the drain may be short-circuited due to formation of the n-type region. Therefore, in the case of forming a transistor with a small channel length, a conductive film having a property of appropriately extracting oxygen from an oxide semiconductor may be used for a source electrode and a drain electrode. Examples of the conductive film having a property of appropriately extracting oxygen include a conductive film containing nickel, molybdenum, or tungsten.

In the case of manufacturing a transistor with a very small channel length (40 nm or less or 30 nm or less), a conductive film that hardly extracts oxygen from an oxide semiconductor may be used as the source electrode 406a and the drain electrode 406b. Examples of the conductive film that hardly extracts oxygen from the oxide semiconductor include a conductive film containing tantalum nitride, titanium nitride, or ruthenium. Note that a plurality of types of conductive films may be stacked.

The protective insulating film 412 is formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or the like. An insulator containing one or more materials selected from the above can be used. In particular, an aluminum oxide film has a high blocking effect that prevents the film from permeating both impurities such as hydrogen and moisture, and oxygen, and is preferable for application to the protective insulating film 412. When the protective insulating film 412 that blocks oxygen is in contact with the side surface of the conductive film 410a, oxygen can be prevented from leaking from the side surface of the conductive film 410a when the conductive film 410a is reduced. Oxygen can be supplied.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
In this embodiment, the oxide semiconductor 404 described in Embodiment 1 will be described in detail.

The oxide semiconductor 404 is an oxide containing indium. For example, when the oxide contains indium, the carrier mobility (electron mobility) increases. The oxide semiconductor 404 preferably contains the element M. Examples of the element M include aluminum, gallium, yttrium, and tin. The element M is an element having a high binding energy with oxygen, for example. The element M is an element having a function of increasing the energy gap of the oxide, for example. The oxide semiconductor 404 preferably contains zinc. When the oxide contains zinc, for example, the oxide is easily crystallized. The energy at the upper end of the valence band of the oxide can be controlled by, for example, the atomic ratio of zinc.

Note that the oxide semiconductor 404 is not limited to an oxide containing indium. The oxide semiconductor 404 may be, for example, a Zn—Sn oxide or a Ga—Sn oxide.

For the oxide semiconductor 404, an oxide with a wide energy gap is used. The energy gap of the oxide semiconductor 404 is, for example, 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV.

The oxide semiconductor 404 is formed by a sputtering method, a CVD (Chemical Vapor Deposition) method, a MOCVD (Metal Organic Chemical Deposition) method, an ALD (Atomic Layer Deposition Method), a thermal CVD method, or a PECVD (Plasma Deposition Method). ), MBE (Molecular Beam Epitaxy) method or PLD (Pulsed Laser Deposition) method. In particular, when the MOCVD method, the ALD method, or the thermal CVD method is used, the oxide semiconductor 404 is hardly damaged because plasma is not used. As a result, the leakage current in the off state of the transistor can be suppressed low, which is preferable.

For example, when an oxide semiconductor InGaZnO _x (X> 0) film is formed by a thermal CVD method, trimethylindium, trimethylgallium, and dimethylzinc are used. Note that the chemical formula of trimethylindium is In (CH ₃ ) ₃ . The chemical formula of trimethylgallium is Ga (CH ₃ ) ₃ . The chemical formula of dimethylzinc is (CH ₃ ) ₂ Zn. The invention is not limited to these combinations, in place of trimethyl gallium can also be used triethyl gallium (chemical formula _{Ga (C 2 H 5) 3} ), diethyl zinc (Formula instead of dimethylzinc _{(C 2} H _{5) 2} Zn) can also be used.

For example, in the case of forming an oxide semiconductor InGaZnO _X (X> 0) film by an ALD method, an In (CH ₃ ) ₃ gas and an O ₃ gas are sequentially introduced to form an InO ₂ layer, and then , Ga (CH ₃ ) ₃ gas and O ₃ gas are simultaneously introduced to form a GaO layer, and then (CH ₃ ) ₂ Zn and O ₃ gas are simultaneously introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Alternatively, a mixed compound layer such as an InGaO ₂ layer, an InZnO ₂ layer, a GaInO layer, a ZnInO layer, or a GaZnO layer may be formed by mixing these gases. Incidentally, O ₃ may be used bubbled with the H _{2 O} gas in place of the gas with an inert gas such as Ar, but better to use an O ₃ gas containing no H are preferred. Further, In (C ₂ H ₅ ) ₃ gas or tris (acetylacetonato) indium may be used instead of In (CH ₃ ) ₃ gas. Tris (acetylacetonato) indium is also called In (acac) ₃ . Further, Ga (C ₂ H ₅ ) ₃ gas or tris (acetylacetonato) gallium may be used instead of Ga (CH ₃ ) ₃ gas. Tris (acetylacetonato) gallium is also called Ga (acac) ₃ . Further, In (C ₂ H ₅ ) ₃ gas may be used instead of In (CH ₃ ) ₃ gas. Further, (CH ₃ ) ₂ Zn gas or zinc acetate may be used. It is not limited to these gas types.

In the case where the oxide semiconductor 404 is formed by a sputtering method, a target containing indium is preferably used in order to reduce the number of particles. Further, when an oxide target having a high atomic ratio of the element M is used, the conductivity of the target may be lowered. In the case of using a target containing indium, the conductivity of the target can be increased, and DC discharge and AC discharge are facilitated, so that it is easy to deal with a large-area substrate. Therefore, the productivity of the semiconductor device can be increased.

In the case where the oxide semiconductor 404 is formed by a sputtering method, the atomic ratio of the target is 3: 1: 1, 3: 1: 2, 3: 1: 4, 1: 1: 0. 5, 1: 1: 1, 1: 1: 2, 1: 4: 4, etc.

In the case where the oxide semiconductor 404 is formed by a sputtering method, a film with an atomic ratio that deviates from the atomic ratio of the target may be formed. In particular, zinc may have a film atomic ratio smaller than the target atomic ratio. Specifically, the atomic ratio of zinc contained in the target may be 40 atomic% or more and 90 atomic% or less.

Hereinafter, effects of impurities in the oxide semiconductor 404 are described. Note that in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor 404 to reduce carrier density and purity. Note that the carrier density of the oxide semiconductor 404 is less than 1 × 10 ¹⁷ pieces / cm ^3, less than 1 × 10 ¹⁵ pieces / cm ³ , or less than 1 × 10 ¹³ pieces / cm ³ . In order to reduce the impurity concentration in the oxide semiconductor 404, it is preferable to reduce the impurity concentration in an adjacent film.

For example, silicon in the oxide semiconductor 404 might serve as a carrier trap or a carrier generation source. Therefore, the silicon concentration between the oxide semiconductor 404 and the base insulating film 402 is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 8 in secondary ion mass spectrometry (SIMS). ^It is less than ¹⁸ atoms / cm ³ , more preferably less than 2 × 10 ¹⁸ atoms / cm ³ . The silicon concentration between the oxide semiconductor 404 and the gate insulating film 408 is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , more preferably 2 × 10 in SIMS. It should be less than ¹⁸ atoms / cm ³ .

Further, when hydrogen is contained in the oxide semiconductor 404, the carrier density may be increased. The hydrogen concentration of the oxide semiconductor 404 is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 5 or less in SIMS. × 10 ¹⁸ atoms / cm ³ or less. In addition, when nitrogen is contained in the oxide semiconductor 404, the carrier density may be increased. The nitrogen concentration of the oxide semiconductor 404 in SIMS is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, further preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In order to reduce the hydrogen concentration of the oxide semiconductor 404, it is preferable to reduce the hydrogen concentration of the base insulating film 402. The hydrogen concentration of the base insulating film 402 is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 5 or less in SIMS. × 10 ¹⁸ atoms / cm ³ or less. In order to reduce the nitrogen concentration in the oxide semiconductor 404, it is preferable to reduce the nitrogen concentration in the base insulating film 402. The nitrogen concentration of the base insulating film 402 is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably SIMS. 5 × 10 ¹⁷ atoms / cm ³ or less.

It is preferable to reduce the hydrogen concentration in the gate insulating film 408 in order to reduce the hydrogen concentration in the oxide semiconductor 404. The hydrogen concentration of the gate insulating film 408 is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 5 or less in SIMS. × 10 ¹⁸ atoms / cm ³ or less. In order to reduce the nitrogen concentration of the oxide semiconductor 404, it is preferable to reduce the nitrogen concentration of the gate insulating film 408. The nitrogen concentration of the gate insulating film 408 is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably SIMS, in SIMS. 5 × 10 ¹⁷ atoms / cm ³ or less.

The structure of an oxide semiconductor that can be used for the oxide semiconductor 404 is described below.

In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

An oxide semiconductor film is roughly classified into a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film refers to a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, or the like.

First, the CAAC-OS film is described.

The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.

Confirming a plurality of crystal parts by observing a bright field image of a CAAC-OS film and a combined analysis image (also referred to as a high-resolution TEM image) of a CAAC-OS film with a transmission electron microscope (TEM: Transmission Electron Microscope). Can do. On the other hand, a clear boundary between crystal parts, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even by a high-resolution TEM image. Therefore, it can be said that the CAAC-OS film is unlikely to decrease in electron mobility due to crystal grain boundaries.

When a high-resolution TEM image of a cross section of the CAAC-OS film is observed from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface on which the CAAC-OS film is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS film. .

On the other hand, when a high-resolution TEM image of the plane of the CAAC-OS film is observed from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

Note that when electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, when electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam of 1 nm to 30 nm is performed on the top surface of the CAAC-OS film, spots are observed (see FIG. 17A).

From the high-resolution TEM image of the cross section and the high-resolution TEM image of the plane, it is found that the crystal part of the CAAC-OS film has orientation.

Note that most crystal parts included in the CAAC-OS film fit in a cube whose one side is less than 100 nm. Therefore, the case where a crystal part included in the CAAC-OS film fits in a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm is included. Note that a plurality of crystal parts included in the CAAC-OS film may be connected to form one large crystal region. For example, in a planar high-resolution TEM image, a crystal region having a thickness of 2500 nm ² or more, 5 μm ² or more, or 1000 μm ² or more may be observed.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS film crystal has c-axis orientation, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear when 2θ is around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of a single crystal oxide semiconductor film of InGaZnO ₄ , when 2θ is fixed in the vicinity of 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), Six peaks attributed to the crystal plane equivalent to the (110) plane are observed. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 2θ fixed at around 56 °.

From the above, in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal parts, but the c-axis is aligned, and the c-axis is a normal line of the formation surface or the top surface. It can be seen that the direction is parallel to the vector. Therefore, each layer of metal atoms arranged in a layer shape confirmed by high-resolution TEM observation of the cross section described above is a plane parallel to the ab plane of the crystal.

Note that the crystal part is formed when a CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film.

In the CAAC-OS film, the distribution of c-axis aligned crystal parts is not necessarily uniform. For example, in the case where the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the ratio of the crystal part in which the region near the upper surface is c-axis aligned than the region near the formation surface May be higher. In addition, in the case where an impurity is added to the CAAC-OS film, the region to which the impurity is added may be changed, and a region having a different ratio of partially c-axis aligned crystal parts may be formed.

Note that when the CAAC-OS film including an InGaZnO ₄ crystal is analyzed by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. The impurity is an element other than the main component of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element such as silicon, which has a stronger bonding force with oxygen than the metal element included in the oxide semiconductor film, disturbs the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen, and has crystallinity. It becomes a factor to reduce. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii). Therefore, if they are contained inside an oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, resulting in crystallinity. It becomes a factor to reduce. Note that the impurity contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source.

The CAAC-OS film is an oxide semiconductor film with a low density of defect states. For example, oxygen vacancies in the oxide semiconductor film can serve as carrier traps or can generate carriers by capturing hydrogen.

A low impurity concentration and a low density of defect states (small number of oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Therefore, a transistor including the oxide semiconductor film has a small change in electrical characteristics and has high reliability. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released, and may behave as if it were a fixed charge. Therefore, a transistor including an oxide semiconductor film with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

In addition, a transistor including a CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

Next, a microcrystalline oxide semiconductor film is described.

The microcrystalline oxide semiconductor film includes a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. In most cases, a crystal part included in the microcrystalline oxide semiconductor film has a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film including a nanocrystal (nc) that is a microcrystal of 1 nm to 10 nm, or 1 nm to 3 nm is referred to as an nc-OS (nanocrystalline Oxide Semiconductor) film. In the nc-OS film, for example, a crystal grain boundary may not be clearly confirmed in a high-resolution TEM image.

The nc-OS film has periodicity in atomic arrangement in a very small region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS film may not be distinguished from an amorphous oxide semiconductor film depending on an analysis method. For example, when structural analysis is performed on the nc-OS film using an XRD apparatus using X-rays having a diameter larger than that of the crystal part, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction (also referred to as limited-field electron diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of the crystal part is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. Is done. On the other hand, when nanobeam electron diffraction is performed on the nc-OS film using an electron beam having a probe diameter that is close to or smaller than the size of the crystal part, spots are observed. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance may be observed so as to draw a circle (in a ring shape). Further, when nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region (see FIG. 17B).

The nc-OS film is an oxide semiconductor film that has higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. Note that the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film.

Next, an amorphous oxide semiconductor film is described.

An amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example.

In the amorphous oxide semiconductor film, a crystal part cannot be confirmed in a high-resolution TEM image.

When structural analysis using an XRD apparatus is performed on an amorphous oxide semiconductor film, a peak indicating a crystal plane is not detected by analysis using an out-of-plane method. Further, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when nanobeam electron diffraction is performed on an amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

Note that the oxide semiconductor film may have a structure having physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS) film.

In the a-like OS film, a void (also referred to as a void) may be observed in a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has the area | region which can confirm a crystal part clearly, and the area | region which cannot confirm a crystal part. In some cases, the a-like OS film is crystallized by a small amount of electron irradiation as observed by a TEM, and a crystal part is grown. On the other hand, in the case of a good-quality nc-OS film, crystallization due to a small amount of electron irradiation comparable to that observed by TEM is hardly observed.

Note that the crystal part size of the a-like OS film and the nc-OS film can be measured using high-resolution TEM images. For example, a crystal of InGaZnO ₄ has a layered structure, and two Ga—Zn—O layers are provided between In—O layers. The unit cell of InGaZnO ₄ crystal has a structure in which a total of nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, it was considered that each lattice fringe corresponds to the ab plane of the InGaZnO ₄ crystal in a portion where the interval between the lattice fringes is 0.28 nm or more and 0.30 nm or less. The maximum length in the region where the lattice fringes are observed is the size of the crystal part of the a-like OS film and the nc-OS film. Note that a crystal part having a size of 0.8 nm or more is selectively evaluated.

Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

In the case where the oxide semiconductor film has a plurality of structures, the structure analysis may be possible by using nanobeam electron diffraction.

18A shows an electron gun chamber 10, an optical system 12 below the electron gun chamber 10, a sample chamber 14 below the optical system 12, an optical system 16 below the sample chamber 14, and an optical system 16 1 shows a transmission electron diffraction measurement apparatus having an observation room 20 below, a camera 18 installed in the observation room 20, and a film chamber 22 below the observation room 20. The camera 18 is installed toward the inside of the observation room 20. Note that the film chamber 22 may not be provided.

FIG. 18B shows the internal structure of the transmission electron diffraction measurement apparatus shown in FIG. Inside the transmission electron diffraction measurement apparatus, electrons emitted from the electron gun installed in the electron gun chamber 10 are irradiated to the substance 28 arranged in the sample chamber 14 through the optical system 12. The electrons that have passed through the substance 28 are incident on the fluorescent plate 32 installed inside the observation room 20 via the optical system 16. On the fluorescent plate 32, a transmission electron diffraction pattern can be measured by the appearance of a pattern corresponding to the intensity of incident electrons.

The camera 18 is installed facing the fluorescent screen 32, and can capture a pattern that appears on the fluorescent screen 32. The angle formed between the center of the lens of the camera 18 and the straight line passing through the center of the fluorescent plate 32 and the upper surface of the fluorescent plate 32 is, for example, 15 ° to 80 °, 30 ° to 75 °, or 45 ° to 70 °. The following. The smaller the angle, the greater the distortion of the transmission electron diffraction pattern photographed by the camera 18. However, if the angle is known in advance, the distortion of the obtained transmission electron diffraction pattern can be corrected. The camera 18 may be installed in the film chamber 22 in some cases. For example, the camera 18 may be installed in the film chamber 22 so as to face the incident direction of the electrons 24. In this case, a transmission electron diffraction pattern with less distortion can be taken from the back surface of the fluorescent plate 32.

The sample chamber 14 is provided with a holder for fixing the substance 28 as a sample. The holder has a structure that transmits electrons passing through the substance 28. The holder may have a function of moving the substance 28 to the X axis, the Y axis, the Z axis, and the like, for example. The movement function of the holder may have an accuracy of moving in the range of 1 nm to 10 nm, 5 nm to 50 nm, 10 nm to 100 nm, 50 nm to 500 nm, 100 nm to 1 μm, and the like. These ranges may be set to optimum ranges depending on the structure of the substance 28.

Next, a method for measuring a transmission electron diffraction pattern of a substance using the above-described transmission electron diffraction measurement apparatus will be described.

For example, as shown in FIG. 18B, the state in which the structure of the substance is changed can be confirmed by changing (scanning) the irradiation position of the electron 24 that is a nanobeam in the substance. At this time, when the substance 28 is a CAAC-OS film, a diffraction pattern as illustrated in FIG. Alternatively, when the substance 28 is an nc-OS film, a diffraction pattern as illustrated in FIG. 17B is observed.

By the way, even if the substance 28 is a CAAC-OS film, a diffraction pattern partially similar to that of the nc-OS film or the like may be observed. Therefore, the quality of the CAAC-OS film can be expressed by a ratio of a region where a diffraction pattern of the CAAC-OS film is observed in a certain range (also referred to as a CAAC conversion rate) in some cases. For example, in the case of a high-quality CAAC-OS film, the CAAC conversion ratio is 60% or more, preferably 80% or more, more preferably 90% or more, and more preferably 95% or more. Note that a region where a diffraction pattern different from that of the CAAC-OS film is observed is referred to as a non-CAAC conversion rate.

As an example, a transmission electron diffraction pattern was acquired while scanning the upper surface of each sample having a CAAC-OS film immediately after film formation (denoted as as-depo), after 350 ° C. heat treatment or after 450 ° C. heat treatment. . Here, the diffraction pattern was observed while scanning at a speed of 5 nm / second for 60 seconds, and the observed diffraction pattern was converted into a still image every 0.5 seconds, thereby deriving the CAAC conversion rate. As the electron beam, a nanobeam electron beam having a probe diameter of 1 nm was used.

The CAAC conversion rate in each sample is shown in FIG. It can be seen that the CAAC conversion rate after 450 ° C. heat treatment is higher than that immediately after film formation and after 350 ° C. heat treatment. That is, it can be seen that heat treatment at a temperature higher than 350 ° C. (for example, 400 ° C. or higher) reduces the non-CAAC conversion rate (the CAAC conversion rate increases). Here, most of the diffraction patterns different from those of the CAAC-OS film were the same as those of the nc-OS film. Therefore, it is suggested that a region having a structure similar to that of the nc-OS film is converted to CAAC by the influence of the structure of the adjacent region by the heat treatment.

When such a measurement method is used, the structure analysis of an oxide semiconductor film having a plurality of structures may be possible.

The oxide semiconductor 404 may be a stacked film of oxide semiconductors. For example, the oxide semiconductor 404 may have a two-layer structure or a three-layer structure.

For example, the case where the oxide semiconductor 404 has a three-layer structure is described. FIG. 2 illustrates the case where the oxide semiconductor 404 includes an oxide semiconductor 404a, an oxide semiconductor 404b, and an oxide semiconductor 404c which are sequentially stacked from the bottom.

For the oxide semiconductor 404b (middle layer), the description of the oxide semiconductor 404 so far is referred to. The oxide semiconductor 404a (lower layer) and the oxide semiconductor 404c (upper layer) are oxide semiconductors composed of one or more elements other than oxygen or two or more elements constituting the oxide semiconductor 404b. Therefore, interface states are unlikely to be formed at the interface between the oxide semiconductor 404a and the oxide semiconductor 404b and at the interface between the oxide semiconductor 404b and the oxide semiconductor 404c.

Note that when the oxide semiconductor 404a is an In-M-Zn oxide, the atomic ratio of In to M when the sum of In and M is 100 atomic% is preferably less than 50 atomic% for In and 50 atomic% for M. More preferably, In is less than 25 atomic% and M is 75 atomic% or more. In the case where the oxide semiconductor 404b is an In-M-Zn oxide, the atomic ratio of In to M when the sum of In and M is 100 atomic% is preferably 25 atomic% or more for In and 75 atomic% for M. Or less, more preferably, In is 34 atomic% or more and M is less than 66 atomic%. In the case where the oxide semiconductor 404c is an In—M—Zn oxide, the atomic ratio of In to M when the sum of In and M is 100 atomic% is preferably less than 50 atomic% for In and 50 atomic% for M. More preferably, In is less than 25 atomic% and M is 75 atomic% or more. Note that the oxide semiconductor 404c may be an oxide of the same type as the oxide semiconductor 404a.

Here, in some cases, there is a mixed region of the oxide semiconductor 404a and the oxide semiconductor 404b between the oxide semiconductor 404a and the oxide semiconductor 404b. Further, in some cases, there is a mixed region of the oxide semiconductor 404b and the oxide semiconductor 404c between the oxide semiconductor 404b and the oxide semiconductor 404c. In the mixed region, the interface state density is low. Therefore, the stack of the oxide semiconductor 404a, the oxide semiconductor 404b, and the oxide semiconductor 404c has a band structure in which energy continuously changes (also referred to as a continuous junction) in the vicinity of each interface.

As the oxide semiconductor 404b, an oxide having an electron affinity higher than those of the oxide semiconductor 404a and the oxide semiconductor 404c is used. For example, as the oxide semiconductor 404b, the electron affinity of the oxide semiconductor 404a and the oxide semiconductor 404c is 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, and more preferably 0.15 eV to 0. An oxide larger than 4 eV is used. Note that the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.

At this time, when an electric field is applied to the gate electrode 410, a channel is formed in the oxide semiconductor 404b having a high electron affinity among the oxide semiconductor 404a, the oxide semiconductor 404b, and the oxide semiconductor 404c.

For the on-state current of the transistor, the thickness of the oxide semiconductor 404c is preferably as small as possible. For example, the oxide semiconductor 404c is less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less. On the other hand, the oxide semiconductor 404c has a function of blocking entry of elements other than oxygen (such as silicon) included in the gate insulating film 408 into the oxide semiconductor 404b where a channel is formed. Therefore, the oxide semiconductor 404c preferably has a certain thickness. For example, the thickness of the oxide semiconductor 404c is 0.3 nm or more, preferably 1 nm or more, more preferably 2 nm or more.

In order to increase reliability, the oxide semiconductor 404a is preferably thick and the oxide semiconductor 404c is preferably thin. Specifically, the thickness of the oxide semiconductor 404a is 20 nm or more, preferably 30 nm or more, more preferably 40 nm or more, more preferably 60 nm or more. By setting the thickness of the oxide semiconductor 404a to 20 nm or more, preferably 30 nm or more, more preferably 40 nm or more, more preferably 60 nm or more, a channel is formed from the interface between the base insulating film 402 and the oxide semiconductor 404a. The oxide semiconductor 404b can be separated by 20 nm or more, preferably 30 nm or more, more preferably 40 nm or more, more preferably 60 nm or more. However, since the productivity of the semiconductor device may be reduced, the thickness of the oxide semiconductor 404a is 200 nm or less, preferably 120 nm or less, more preferably 80 nm or less.

For example, the silicon concentration between the oxide semiconductor 404b and the oxide semiconductor 404a is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , more preferably 2 × 10 in SIMS. It should be less than ¹⁸ atoms / cm ³ . The silicon concentration between the oxide semiconductor 404b and the oxide semiconductor 404c is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , more preferably 2 × 10 in SIMS. It should be less than ¹⁸ atoms / cm ³ .

In order to reduce the hydrogen concentration of the oxide semiconductor 404b, it is preferable to reduce the hydrogen concentration of the oxide semiconductor 404a and the oxide semiconductor 404c. The hydrogen concentration of the oxide semiconductor 404a and the oxide semiconductor 404c is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less in SIMS. More preferably, it is 5 × 10 ¹⁸ atoms / cm ³ or less. In order to reduce the nitrogen concentration of the oxide semiconductor 404b, it is preferable to reduce the nitrogen concentrations of the oxide semiconductor 404a and the oxide semiconductor 404c. The nitrogen concentration of the oxide semiconductor 404a and the oxide semiconductor 404c is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ^{3 in} SIMS. In the following, it is more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

The above three-layer structure is an example. For example, a two-layer structure without the oxide semiconductor 404a or the oxide semiconductor 404c may be employed.

This embodiment can be implemented in appropriate combination with any of the other embodiments.
(Embodiment 3)

Next, a method for manufacturing the transistor described in Embodiment 1 will be described with reference to FIGS.

First, the base insulating film 402 is formed over the substrate 400 (see FIG. 3A).

The base insulating film 402 may be formed by a sputtering method, a CVD method (including an ALD method, an MOCVD method, a thermal CVD method, or a PECVD method), an MBE method, or a PLD method. In particular, the ALD method, the MOCVD method, or the thermal CVD method is preferable because it does not use plasma and causes little damage.

Next, CMP treatment may be performed to planarize the surface of the base insulating film 402. By performing CMP treatment, the average surface roughness (Ra) of the base insulating film 402 is set to 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less. When Ra is equal to or lower than the above numerical value, the crystallinity of the oxide semiconductor 404 may be increased. Ra can be measured with an atomic force microscope (AFM).

Next, an insulating layer containing excess oxygen may be formed by adding oxygen to the base insulating film 402. Oxygen may be added by plasma treatment or ion implantation. In the case where oxygen is added by an ion implantation method, for example, the acceleration voltage may be 2 kV to 100 kV and the dose may be 5 × 10 ¹⁴ ions / cm ^{2 to} 5 × 10 ¹⁶ ions / cm ² .

Next, the oxide semiconductor 404 is formed over the base insulating film 402 by the method described in Embodiment 2 (see FIG. 3B). At this time, the base insulating film 402 may be appropriately etched. By appropriately etching the base insulating film 402, the oxide semiconductor 404 can be easily covered with a gate electrode 410 to be formed later. Note that a hard mask may be used when the oxide semiconductor 404 is processed in order to reduce the size of the transistor.

Further, in the case where a stacked film including the oxide semiconductor 404a, the oxide semiconductor 404b, and the oxide semiconductor 404c illustrated in FIGS. 2A to 2C is formed as the oxide semiconductor 404, each layer is formed continuously without being exposed to the air. preferable.

The oxide semiconductor 404 is formed with a substrate temperature of 100 ° C. or higher, preferably 150 ° C. or higher, more preferably 200 ° C. or higher in order to reduce the entry of impurities and to form an oxide semiconductor with high crystallinity. The oxygen gas or argon gas used as the film forming gas is a gas that has been highly purified to a dew point of −40 ° C. or lower, preferably −80 ° C. or lower, more preferably −100 ° C. or lower. Note that a low impurity concentration and a low density of defect states (low oxygen vacancies) are referred to as high purity intrinsic or substantially high purity intrinsic.

After the oxide semiconductor 404 is formed, first heat treatment may be performed. The first heat treatment may be performed at a temperature of 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, or a reduced pressure state. The atmosphere of the first heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement desorbed oxygen after heat treatment in an inert gas atmosphere. By the first heat treatment, the crystallinity of the oxide semiconductor 404 can be increased and impurities such as hydrogen and water can be removed from the base insulating film 402.

Next, a conductive film 405 to be the source electrode 406a and the drain electrode 406b is formed over the oxide semiconductor 404 (see FIG. 3C). The conductive film 405 may be formed by a sputtering method, a CVD method (including an ALD method, an MOCVD method, a thermal CVD method, or a PECVD method), an MBE method, or a PLD method. In particular, the ALD method, the MOCVD method, or the thermal CVD method is preferable because it does not use plasma and causes little damage.

For example, in the case where tungsten is formed as the conductive film 405 by using the ALD method, an initial tungsten film is formed by sequentially introducing WF ₆ gas and B ₂ H ₆ gas, and then the WF ₆ gas and H ₂ gas is simultaneously introduced to form a tungsten film. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

Next, etching is performed so that the conductive film 405 is divided, so that the source electrode 406a and the drain electrode 406b are formed (see FIG. 4A). Note that when the conductive film 405 is etched, end portions of the source electrode 406a and the drain electrode 406b may be rounded (having a curved surface) in some cases. Further, when the conductive film 405 is etched, the base insulating film 402 and the oxide semiconductor 404 may be appropriately etched.

Next, the gate insulating film 408 is formed over the oxide semiconductor 404, the source electrode 406a, and the drain electrode 406b. The gate insulating film 408 may be formed by a sputtering method, a CVD method (including an ALD method, an MOCVD method, a thermal CVD method, or a PECVD method), an MBE method, or a PLD method. In particular, the ALD method, the MOCVD method, or the thermal CVD method is preferable because it does not use plasma and causes little damage.

For example, in the case where silicon oxide is formed as the gate insulating film 408 using a thermal CVD method, hexachlorodisilane is adsorbed on the deposition surface, chlorine contained in the adsorbed material is removed, and an oxidizing gas (O ₂ , radicals of dinitrogen monoxide) are supplied to react with the adsorbate.

For example, in the case where hafnium oxide is formed as the gate insulating film 408 by using a thermal CVD method, a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide solution, typically tetrakisdimethylamide hafnium (TDMAH)). Two types of gases, vaporized raw material gas and ozone (O ₃ ) as an oxidizing agent, are used. Note that the chemical formula of tetrakisdimethylamide hafnium is Hf [N (CH ₃ ) ₂ ] ₄ . Other material liquids include tetrakis (ethylmethylamide) hafnium.

Next, a conductive film 410a and a conductive film 410b are formed over the gate insulating film 408, so that the gate electrode 410 is formed (see FIG. 4B). The conductive film 410a and the conductive film 410b may be formed by a sputtering method, a CVD method (including an ALD method, an MOCVD method, a thermal CVD method, or a PECVD method), an MBE method, or a PLD method. In particular, the ALD method, the MOCVD method, or the thermal CVD method is preferable because it does not use plasma and causes little damage.

Next, a protective insulating film 412 is formed over the source electrode 406a, the drain electrode 406b, the gate insulating film 408, and the gate electrode 410 (see FIG. 4C). The protective insulating film 412 may be formed by a sputtering method, a CVD method (including an ALD method, an MOCVD method, a thermal CVD method, or a PECVD method), an MBE method, or a PLD method. In particular, the ALD method, the MOCVD method, or the thermal CVD method is preferable because it does not use plasma and causes little damage.

For example, in the case where aluminum oxide is formed as the protective insulating film 412 using a thermal CVD method, a source gas obtained by vaporizing a liquid (such as TMA) containing a solvent and an aluminum precursor compound and H ₂ as an oxidizing agent are used. Two kinds of gases of O are used. Note that the chemical formula of trimethylaluminum is Al (CH ₃ ) ₃ . Other material liquids include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.

Next, second heat treatment is performed. The second heat treatment can be performed under conditions similar to those of the heat treatment described in Embodiment 1. Through the second heat treatment, the gate electrode 410 is reduced, so that the conductive films 411a, 411b, and 411c are formed (see FIG. 5). At that time, oxygen released from the conductive film 410a can be supplied to the oxide semiconductor 404 through the gate insulating film 408, so that oxygen vacancies in the oxide semiconductor 404 can be reduced.

Through the above steps, the transistor described in Embodiment 1 can be manufactured.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.
(Embodiment 4)

In this embodiment, the case where a bottom gate electrode (a gate electrode existing between an oxide semiconductor and a substrate) is added to the transistor described in Embodiment 1 will be described with reference to drawings.

6A and 6B are a top view and a cross-sectional view of a transistor of one embodiment of the present invention. 6A is a top view, and FIG. 6B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 illustrated in FIG. 6A. Note that in the top view of FIG. 6A, some elements are omitted for clarity.

The transistor illustrated in FIGS. 6A and 6B includes a substrate 600, a first gate electrode 620 over the substrate 600, and a first gate insulating film over the substrate 600 and the first gate electrode 620. 602, an oxide semiconductor 604 which overlaps with the first gate electrode 620 with the first gate insulating film 602 interposed therebetween, a source electrode 606a and a drain electrode 606b which are in contact with an upper surface and a side surface of the oxide semiconductor 604, and an oxide semiconductor 604 In addition, a second gate insulating film 608 over the source electrode 606a and the drain electrode 606b, and a second gate electrode 610 which is in contact with the top surface of the second gate insulating film 608 and faces the top surface and side surfaces of the oxide semiconductor 604. A protective insulating film 612 over the source electrode 606a, the drain electrode 606b, and the second gate electrode 610, and the first gate The second electrode 620 includes a conductive film 620b and a conductive film 620a over the conductive film 620b. The second gate electrode 610 includes a conductive film 610a and a conductive film 610b over the conductive film 610a. It consists of a membrane. Note that a base insulating film may be provided between the substrate 600 and the first gate electrode 620.

In FIG. 6B, since the first gate electrode 620 and the second gate electrode 610 are not connected to each other, different potentials can be applied at the same time, but these electrodes are electrically connected and the same potential is applied. Can be given at the same time.

For the conductive film 610a and the conductive film 620a, the description of the conductive film 410a described in Embodiment 1 is referred to. For the conductive film 610b and the conductive film 620b, the description of the conductive film 410b described in Embodiment 1 is referred to. For the first gate insulating film 602 and the second gate insulating film 608, the description of the gate insulating film 408 described in Embodiment 1 is referred to. Note that the description of each corresponding component in FIG. 1B may be referred to for other components.

FIG. 6C illustrates a state after the heat treatment is performed to reduce the conductive films 610a and 620a.

FIG. 6C illustrates a first gate electrode 621 including a conductive film 621c, a conductive film 621b over the conductive film 621c, and a conductive film 621a over the conductive film 621b, and a conductive film 611a and a conductive film 611b over the conductive film 611a. And the second gate electrode 611 including the conductive film 611c over the conductive film 611b. In FIG. 6C, structures other than the first gate electrode 621 and the second gate electrode 611 are the same as those in FIG.

For the conductive film 611a and the conductive film 621a, the description of the conductive film 411a described in Embodiment 1 is referred to. For the conductive film 611b and the conductive film 621b, the description of the conductive film 411b described in Embodiment 1 is referred to. For the conductive film 611c and the conductive film 621c, the description of the conductive film 411c described in Embodiment 1 is referred to.

As in Embodiment 1, this embodiment also aims to supply oxygen released to the oxide semiconductor 604 by reducing the conductive films 620a and 610a.

The transistor described in Embodiment 1 includes the base insulating film 402 having an oxygen supply capability under the oxide semiconductor 404. By increasing the thickness of the base insulating film 402, the amount of oxygen that can be supplied is increased. Can be increased. The transistor described in this embodiment includes the first gate insulating film 602 under the oxide semiconductor 604; however, the first gate insulating film 602 cannot be thick enough from the viewpoint of gate capacitance, and is sufficient. It is not possible to have a sufficient oxygen supply capacity. Therefore, in the transistor described in this embodiment, it is extremely important to supply oxygen from gate electrodes arranged above and below an oxide semiconductor.
(Embodiment 5)

In this embodiment, an example of a circuit using the transistor of one embodiment of the present invention will be described with reference to drawings.

FIG. 7A is a cross-sectional view of the semiconductor device of one embodiment of the present invention. A semiconductor device illustrated in FIG. 7A includes a substrate 2201, a transistor 2200, a transistor 2100, a wiring 2202, a plug 2203, a wiring 2206, a wiring 2205, an element isolation layer 2204, an insulating layer 2207, And an insulating layer 2208. The transistor 2200 includes an impurity region 2001 functioning as a source region or a drain region, a gate electrode 2003, a gate insulating film 2004, and a sidewall insulating layer 2005.

A semiconductor device illustrated in FIG. 7A includes a transistor 2200 using a first semiconductor material in a lower portion and a transistor 2100 using a second semiconductor material in an upper portion. FIG. 7A illustrates an example in which the transistor illustrated in Embodiment 1 is used as the transistor 2100 including the second semiconductor material. Note that the left side of the alternate long and short dash line is a cross section in the channel length direction of the transistors 2100 and 2200, and the right side is a cross section in the channel width direction of the transistors 2100 and 2200.

The first semiconductor material and the second semiconductor material are preferably materials having different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide), and the second semiconductor material can be an oxide semiconductor. A transistor using single crystal silicon or the like as a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor has low off-state current.

The transistor 2200 may be either an n-channel transistor or a p-channel transistor, and an appropriate transistor may be used depending on a circuit. In addition to the use of the transistor of one embodiment of the present invention using an oxide semiconductor, the specific structure of the semiconductor device, such as a material and a structure used, is not necessarily limited to that described here.

In the transistor 2200, an impurity region functioning as an LDD (Lightly Doped Drain) region or an extension region may be provided under the sidewall insulating layer 2005. In particular, when the transistor 2200 is an n-channel transistor, an LDD region or an extension region is preferably provided in order to suppress deterioration due to hot carriers.

Alternatively, the transistor 2200 may be a transistor having silicide (salicide) or a transistor not having the sidewall insulating layer 2005. When the structure has silicide (salicide), the resistance of the source region and the drain region can be further reduced, and the speed of the semiconductor device can be increased. In addition, since the semiconductor device can operate at a low voltage, power consumption of the semiconductor device can be reduced.

Thus, by stacking two types of transistors, the area occupied by the circuit is reduced, and a plurality of circuits can be arranged at a higher density.

As the substrate 2201, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI (Silicon on Insulator) substrate, or the like can be used. A transistor formed using a semiconductor substrate can easily operate at high speed. Note that in the case where a p-type single crystal silicon substrate is used as the substrate 2201, an n-type well is formed by adding an impurity element imparting n-type to part of the substrate 2201, and the n-type well is formed. It is also possible to form a p-type transistor in the region. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B) or the like can be used.

The substrate 2201 may be a substrate in which a semiconductor film is provided over an insulating substrate. Examples of the insulating substrate include a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, and a bonded substrate. Examples thereof include a film, a paper containing a fibrous material, and a base film. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. As an example of the flexible substrate, there are plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic. Examples of the laminated film include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the base film include polyester, polyamide, polyimide, aramid, epoxy, inorganic vapor deposition film, and papers.

Note that a semiconductor element may be formed using a certain substrate, and then the semiconductor element may be transferred to another substrate. Examples of substrates on which semiconductor elements are transferred include paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (natural fibers (silk, cotton, hemp)) , Synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), leather substrates, rubber substrates, etc. By using these substrates, transistors with good characteristics can be obtained. Formation, formation of a transistor with low power consumption, manufacture of a device that is not easily broken, imparting heat resistance, weight reduction, or thickness reduction can be achieved.

The transistor 2200 is separated from other transistors formed over the substrate 2201 by an element isolation layer 2204. The element isolation layer 2204 includes aluminum oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and hafnium oxide. An insulator containing one or more selected from tantalum oxide and the like can be used.

Here, in the case where a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, hydrogen in the insulating layer provided in the vicinity of the semiconductor layer of the transistor 2200 terminates a dangling bond of silicon, thereby improving the reliability of the transistor 2200. There is an effect to improve. On the other hand, in the case where an oxide semiconductor is used for the transistor 2100 provided in the upper layer, hydrogen in the insulating layer provided in the vicinity of the semiconductor layer of the transistor 2100 serves as one factor for generating carriers in the oxide semiconductor. In some cases, the reliability of the transistor 2100 may be reduced. Therefore, in the case where the transistor 2100 using an oxide semiconductor is stacked over the transistor 2200 using a silicon-based semiconductor material, it is particularly preferable to provide the insulating layer 2207 having a function of preventing hydrogen diffusion therebetween. It is effective. In addition to improving the reliability of the transistor 2200 by confining hydrogen in the lower layer with the insulating layer 2207, the reliability of the transistor 2100 can be improved at the same time by suppressing diffusion of hydrogen from the lower layer to the upper layer. it can.

As the insulating layer 2207, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.

In addition, an insulating layer 2208 having a function of preventing hydrogen diffusion is preferably formed over the transistor 2100 so as to cover the transistor 2100 including an oxide semiconductor layer. As the insulating layer 2208, a material similar to that of the insulating layer 2207 can be used, and aluminum oxide is particularly preferably used. The aluminum oxide film has a high blocking effect that prevents the film from permeating both impurities such as hydrogen and moisture and oxygen. Therefore, by using an aluminum oxide film as the insulating layer 2208 that covers the transistor 2100, oxygen is prevented from being released from the oxide semiconductor layer included in the transistor 2100 and water and hydrogen are prevented from entering the oxide semiconductor layer. Can be prevented.

Note that the transistor 2200 can be a transistor of various types as well as a planar transistor. For example, a transistor of FIN (fin) type, TRI-GATE (trigate) type, or the like can be used. An example of a cross-sectional view in that case is shown in FIG. An insulating layer 2212 is provided over the semiconductor substrate 2211. The semiconductor substrate 2211 has a protruding portion (also referred to as a fin) with a thin tip. Note that an insulating film may be provided on the convex portion. The insulating film functions as a mask for preventing the semiconductor substrate 2211 from being etched when the convex portion is formed. In addition, the convex part does not need to have a thin tip, for example, it may be a substantially rectangular parallelepiped convex part or a thick convex part. A gate insulating film 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. A source region and a drain region 2215 are formed in the semiconductor substrate 2211. Note that although the example in which the semiconductor substrate 2211 includes a convex portion is described here, the semiconductor device according to one embodiment of the present invention is not limited thereto. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion.

Note that in FIGS. 7A and 7D, a region to which no code or hatching pattern is given represents a region formed of an insulator. These regions include aluminum oxide, aluminum nitride oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide An insulator containing one or more selected from tantalum oxide and the like can be used. In the region, an organic resin such as a polyimide resin, a polyamide resin, an acrylic resin, a siloxane resin, an epoxy resin, or a phenol resin can be used.

In the above structure, various circuits can be formed by changing connection structures of the electrodes of the transistor 2100 and the transistor 2200. An example of a circuit configuration that can be realized by using the semiconductor device of one embodiment of the present invention will be described below.

The circuit diagram illustrated in FIG. 7B illustrates a structure of a so-called CMOS circuit in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and gates thereof are connected.

In addition, the circuit diagram illustrated in FIG. 7C illustrates a structure in which the sources and drains of the transistors 2100 and 2200 are connected to each other. With such a configuration, it can function as a so-called analog switch.

FIG. 8 illustrates an example of a semiconductor device (memory device) in which a transistor which is one embodiment of the present invention is used and stored data can be stored even when power is not supplied and the number of writing operations is not limited.

A semiconductor device illustrated in FIG. 8A includes a transistor 3200 using a first semiconductor material, a transistor 3300 using a second semiconductor material, and a capacitor 3400. Note that as the transistor 3300, the transistor described in Embodiment 1 can be used.

The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 3300 has low off-state current, stored data can be held for a long time by using the transistor 3300. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

In FIG. 8A, the first wiring 3001 is electrically connected to the source electrode of the transistor 3200, and the second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is electrically connected to one of a source electrode and a drain electrode of the transistor 3300, and the fourth wiring 3004 is electrically connected to a gate electrode of the transistor 3300. The other of the gate electrode of the transistor 3200 and the source and drain electrodes of the transistor 3300 is electrically connected to the first terminal of the capacitor 3400, and the fifth wiring 3005 is a second terminal of the capacitor 3400. And are electrically connected.

In the semiconductor device illustrated in FIG. 8A, information can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode of the transistor 3200 can be held.

Information writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the gate electrode of the transistor 3200 and the capacitor 3400. That is, predetermined charge is supplied to the gate of the transistor 3200 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off, so that the transistor 3300 is turned off, whereby the charge given to the gate of the transistor 3200 is held (held).

Since the off-state current of the transistor 3300 is extremely small, the charge of the gate of the transistor 3200 is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, according to the amount of charge held in the gate of the transistor 3200, The second wiring 3002 has different potentials. In general, when the transistor 3200 is an n-channel transistor, the apparent threshold V _{th_H in the} case where a high-level charge is applied to the gate electrode of the transistor 3200 is a low-level charge applied to the gate electrode of the transistor 3200. This is because it becomes lower than the apparent threshold value V _{th_L} of the case. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for turning on the transistor 3200. Therefore, the charge applied to the gate of the transistor 3200 can be determined by _setting the potential of the fifth wiring 3005 to a potential V ₀ between V _{th_H} and V _{th_L} . For example, in the case where a high-level charge is applied in writing, the transistor 3200 is turned on when the potential of the fifth wiring 3005 is V ₀ (> V _{th_H} ). In the case where a low-level charge is _supplied , the transistor 3200 remains in the “off state” even when the potential of the fifth wiring 3005 is V ₀ (<V _{th_L} ). Therefore, the stored information can be read by determining the potential of the second wiring 3002.

Note that in the case of using memory cells arranged in an array, it is necessary to read only information of a desired memory cell. In the case where information is not read out in this manner, the fifth wiring 3005 may be _{supplied with a} potential at which the transistor 3200 is turned off regardless of the state of the gate, that is, a potential lower than V _{th_H} . _{Alternatively} , a potential that turns on the transistor 3200 regardless of the state of the gate, that is, a potential higher than V _{th_L} may be _supplied to the fifth wiring 3005.

The semiconductor device illustrated in FIG. 8B is different from FIG. 8A in that the transistor 3200 is not provided. In this case, information can be written and held by the same operation as described above.

Next, reading of information from the semiconductor device illustrated in FIG. 8B is described. When the transistor 3300 is turned on, the third wiring 3003 in a floating state and the capacitor 3400 are brought into conduction, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in potential of the third wiring 3003 varies depending on the potential of the first terminal of the capacitor 3400 (or charge accumulated in the capacitor 3400).

For example, the potential of the first terminal of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before charge is redistributed Is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, when the potential of the first terminal of the capacitor 3400 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 in the case where the potential V1 is held. The potential (= (CB × VB0 + C × V1) / (CB + C)) is higher than the potential of the third wiring 3003 when the potential V0 is held (= CB × VB0 + C × V0) / (CB + C)). I understand that.

Then, information can be read by comparing the potential of the third wiring 3003 with a predetermined potential.

In this case, a transistor to which the first semiconductor material is applied is used for a driver circuit for driving the memory cell, and a transistor to which the second semiconductor material is applied is stacked over the driver circuit as the transistor 3300. And it is sufficient.

In the semiconductor device described in this embodiment, stored data can be held for an extremely long time by using a transistor with an extremely small off-state current that uses an oxide semiconductor for a channel formation region. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

In addition, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that there is no problem of deterioration of the gate insulating film. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, since data is written depending on the on / off state of the transistor, high-speed operation can be easily realized.

(Embodiment 6)
In this embodiment, an RFID tag including the transistor or the memory device described in the above embodiment will be described with reference to FIGS.

The RFID tag in this embodiment has a storage circuit inside, stores necessary information in the storage circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. Because of these characteristics, the RFID tag can be used in an individual authentication system that identifies an article by reading individual information such as the article. Note that extremely high reliability is required for use in these applications.

The configuration of the RFID tag will be described with reference to FIG. FIG. 9 is a block diagram illustrating a configuration example of an RFID tag.

As shown in FIG. 9, the RFID tag 800 includes an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator or a reader / writer). The RFID tag 800 includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a storage circuit 810, and a ROM 811. Note that a material that can sufficiently suppress a reverse current, such as an oxide semiconductor, may be used for the transistor including the rectifying action included in the demodulation circuit 807. Thereby, the fall of the rectification effect | action resulting from a reverse current can be suppressed, and it can prevent that the output of a demodulation circuit is saturated. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linear. Note that there are three major data transmission formats: an electromagnetic coupling method in which a pair of coils are arranged facing each other to perform communication by mutual induction, an electromagnetic induction method in which communication is performed by an induction electromagnetic field, and a radio wave method in which communication is performed using radio waves. Separated. The RFID tag 800 described in this embodiment can be used for any of the methods.

Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 to and from the antenna 802 connected to the communication device 801. Further, the rectifier circuit 805 rectifies an input AC signal generated by receiving a radio signal by the antenna 804, for example, half-wave double voltage rectification, and the signal rectified by a capacitive element provided in the subsequent stage. It is a circuit for generating an input potential by smoothing. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling not to input more than a certain amount of power to a subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.

The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may include a reset signal generation circuit. The reset signal generation circuit is a circuit for generating a reset signal of the logic circuit 809 using a stable rise of the power supply voltage.

The demodulation circuit 807 is a circuit for demodulating an input AC signal by detecting an envelope and generating a demodulated signal. The modulation circuit 808 is a circuit for performing modulation according to data output from the antenna 804.

A logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The memory circuit 810 is a circuit that holds input information and includes a row decoder, a column decoder, a storage area, and the like. The ROM 811 is a circuit for storing a unique number (ID) or the like and outputting it according to processing.

Note that the above-described circuits can be appropriately disposed as necessary.

Here, the memory circuit described in the above embodiment can be used for the memory circuit 810. The memory circuit of one embodiment of the present invention can hold information even when the power is cut off, and thus can be preferably used for an RFID tag. Further, the memory circuit of one embodiment of the present invention does not cause a difference in maximum communication distance between data reading and writing because power (voltage) necessary for data writing is significantly smaller than that of a conventional nonvolatile memory. It is also possible. Furthermore, it is possible to suppress the occurrence of malfunction or erroneous writing due to insufficient power during data writing.

The memory circuit of one embodiment of the present invention can also be applied to the ROM 811 because it can be used as a nonvolatile memory. In that case, it is preferable that the producer separately prepares a command for writing data in the ROM 811 so that the user cannot freely rewrite the command. By shipping the product after the producer has written the unique number before shipping, it is possible to assign a unique number only to the good products to be shipped, rather than assigning a unique number to all RFID tags produced, The unique number of the product after shipment does not become discontinuous, and customer management corresponding to the product after shipment becomes easy.

This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 7)
In this embodiment, a CPU including at least the transistor described in the above embodiment and including the memory device described in the above embodiment will be described.

FIG. 10 is a block diagram illustrating a configuration example of a CPU using at least part of the transistor described in the above embodiment.

10 includes an ALU 1191 (ALU: arithmetic logic unit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198. (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F). As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 10 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, the configuration including the CPU or the arithmetic circuit illustrated in FIG. 10 may be a single core, and a plurality of the cores may be included so that each core operates in parallel. Further, the number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

In addition, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the various circuits.

In the CPU illustrated in FIG. 10, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the transistor described in the above embodiment can be used.

In the CPU illustrated in FIG. 10, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

FIG. 11 is an example of a circuit diagram of a memory element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized by power-off, a circuit 1202 in which stored data is not volatilized by power-off, a switch 1203, a switch 1204, a logic element 1206, a capacitor 1207, and a selection function. Circuit 1220 having. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include other elements such as a diode, a resistance element, and an inductor, as necessary.

Here, the memory device described in the above embodiment can be used for the circuit 1202. When supply of power supply voltage to the memory element 1200 is stopped, the gate of the transistor 1209 in the circuit 1202 is continuously input with the ground potential (0 V) or the potential at which the transistor 1209 is turned off. For example, the gate of the transistor 1209 is grounded through a load such as a resistor.

The switch 1203 is configured using a transistor 1213 of one conductivity type (eg, n-channel type), and the switch 1204 is configured using a transistor 1214 of conductivity type (eg, p-channel type) opposite to the one conductivity type. An example is shown. Here, the first terminal of the switch 1203 corresponds to one of the source and the drain of the transistor 1213, the second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213, and the switch 1203 is the gate of the transistor 1213. In accordance with the control signal RD input to the second terminal, conduction or non-conduction between the first terminal and the second terminal (that is, the on state or the off state of the transistor 1213) is selected. The first terminal of the switch 1204 corresponds to one of the source and the drain of the transistor 1214, the second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and the switch 1204 is input to the gate of the transistor 1214. The control signal RD selects the conduction or non-conduction between the first terminal and the second terminal (that is, the on state or the off state of the transistor 1214).

One of a source and a drain of the transistor 1209 is electrically connected to one of a pair of electrodes of the capacitor 1208 and a gate of the transistor 1210. Here, the connection part is referred to as a node M2. One of a source and a drain of the transistor 1210 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential, and the other is electrically connected to a first terminal of the switch 1203. A second terminal of the switch 1203 is electrically connected to a first terminal of the switch 1204. A second terminal of the switch 1204 is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203, the first terminal of the switch 1204 (the input terminal of the logic element 1206, and one of the pair of electrodes of the capacitor 1207 are electrically connected. The other of the pair of electrodes of the capacitor 1207 can be input with a constant potential, for example, a low power supply potential (GND or the like) or a high power supply potential ( The other of the pair of electrodes of the capacitor 1207 is electrically connected to a wiring that can supply a low power supply potential (eg, a GND line). A constant potential can be input to the other of the pair of electrodes of the capacitor 1208. For example, a low power supply potential (GND or the like) or a high power supply potential (VDD or the like) is input. The other of the. Pair of electrodes of the capacitor 1208 may be are electrically connected to a wiring capable of supplying a low power supply potential (e.g., GND line).

Note that the capacitor 1207 and the capacitor 1208 can be omitted by positively using a parasitic capacitance of a transistor or a wiring.

A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE. When the terminals of the other switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.

A signal corresponding to data held in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. FIG. 11 illustrates an example in which the signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209. A signal output from the second terminal of the switch 1203 becomes an inverted signal obtained by inverting the logic value by the logic element 1206 and is input to the circuit 1201 through the circuit 1220.

Note that FIG. 11 illustrates an example in which the signal output from the second terminal of the switch 1203 is input to the circuit 1201 through the logic element 1206 and the circuit 1220; however, the present invention is not limited to this. A signal output from the second terminal of the switch 1203 may be input to the circuit 1201 without inversion of the logical value. For example, when there is a node in the circuit 1201 that holds a signal obtained by inverting the logical value of a signal input from an input terminal, the signal output from the second terminal of the switch 1203 is input to the node. be able to.

Further, in FIGS. 11A and 11B, among the transistors used in the memory element 1200, a transistor other than the transistor 1209 can be a transistor in which a channel is formed in a layer formed of a semiconductor other than an oxide semiconductor or the substrate 1190. For example, a transistor in which a channel is formed in a silicon layer or a silicon substrate can be used. Further, all the transistors used for the memory element 1200 can be transistors whose channel is formed using an oxide semiconductor layer. Alternatively, the memory element 1200 may include a transistor whose channel is formed using an oxide semiconductor layer in addition to the transistor 1209, and the remaining transistors may be formed in a layer formed using a semiconductor other than an oxide semiconductor or the substrate 1190. It can also be a formed transistor.

For the circuit 1201 in FIG. 11, for example, a flip-flop circuit can be used. As the logic element 1206, for example, an inverter, a clocked inverter, or the like can be used.

In the semiconductor device which is one embodiment of the present invention, data stored in the circuit 1201 can be held by the capacitor 1208 provided in the circuit 1202 while the power supply voltage is not supplied to the memory element 1200.

In addition, a transistor in which a channel is formed in the oxide semiconductor layer has extremely low off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer is significantly lower than the off-state current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held in the capacitor 1208 is maintained for a long time even when the power supply voltage is not supplied to the memory element 1200. In this manner, the memory element 1200 can hold stored data (data) even while the supply of power supply voltage is stopped.

Further, by providing the switch 1203 and the switch 1204, the memory element is characterized by performing a precharge operation; therefore, after the supply of power supply voltage is resumed, the time until the circuit 1201 retains the original data again is shortened. be able to.

In the circuit 1202, the signal held by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after the supply of the power supply voltage to the memory element 1200 is restarted, the signal held by the capacitor 1208 can be converted into the state of the transistor 1210 (on state or off state) and read from the circuit 1202. it can. Therefore, the original signal can be accurately read even if the potential corresponding to the signal held in the capacitor 1208 slightly fluctuates.

By using such a storage element 1200 for a storage device such as a register or a cache memory included in the processor, loss of data in the storage device due to stop of supply of power supply voltage can be prevented. In addition, after the supply of the power supply voltage is resumed, the state before the power supply stop can be restored in a short time. Accordingly, power can be stopped in a short time in the entire processor or in one or a plurality of logic circuits constituting the processor, so that power consumption can be suppressed.

In this embodiment, the memory element 1200 is described as an example of using the CPU. However, the memory element 1200 is an LSI such as a DSP (Digital Signal Processor), a custom LSI, or a PLD (Programmable Logic Device), or an RF-ID (Radio Frequency Frequency). (Identification).

(Embodiment 8)
In this embodiment, structural examples of the display device of one embodiment of the present invention will be described.

[Configuration example]
20A is a top view of the display device of one embodiment of the present invention, and FIG. 20B can be used when a liquid crystal element is applied to a pixel of the display device of one embodiment of the present invention. It is a circuit diagram for demonstrating a pixel circuit. FIG. 20C is a circuit diagram illustrating a pixel circuit that can be used when an organic EL element is applied to a pixel of the display device of one embodiment of the present invention.

The transistor provided in the pixel portion can be formed according to the above embodiment mode. In addition, since the transistor can easily be an n-channel transistor, a part of the driver circuit that can be formed using an n-channel transistor is formed over the same substrate as the transistor in the pixel portion. In this manner, a highly reliable display device can be provided by using the transistor described in the above embodiment for the pixel portion and the driver circuit.

An example of a top view of the active matrix display device is shown in FIG. A pixel portion 701, a first scan line driver circuit 702, a second scan line driver circuit 703, and a signal line driver circuit 704 are provided over a substrate 700 of the display device. In the pixel portion 701, a plurality of signal lines are extended from the signal line driver circuit 704, and a plurality of scan lines are extended from the first scan line driver circuit 702 and the second scan line driver circuit 703. Has been placed. Note that pixels each having a display element are provided in a matrix in the intersection region between the scan line and the signal line. In addition, the substrate 700 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) through a connection unit such as an FPC (Flexible Printed Circuit).

In FIG. 20A, the first scan line driver circuit 702, the second scan line driver circuit 703, and the signal line driver circuit 704 are formed over the same substrate 700 as the pixel portion 701. For this reason, the number of components such as a drive circuit provided outside is reduced, so that cost can be reduced. Further, when a drive circuit is provided outside the substrate 700, it is necessary to extend the wiring, and the number of connections between the wirings increases. In the case where a driver circuit is provided over the same substrate 700, the number of connections between the wirings can be reduced, so that reliability or yield can be improved.

[Liquid Crystal Display]
An example of a circuit configuration of the pixel is shown in FIG. Here, a pixel circuit which can be applied to a pixel of a VA liquid crystal display device is shown.

This pixel circuit can be applied to a configuration having a plurality of pixel electrode layers in one pixel. Each pixel electrode layer is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. Thereby, the signals applied to the individual pixel electrode layers of the multi-domain designed pixels can be controlled independently.

The gate wiring 712 of the transistor 716 and the gate wiring 713 of the transistor 717 are separated so that different gate signals can be given. On the other hand, the source or drain electrode layer 714 functioning as a data line is used in common for the transistor 716 and the transistor 717. The transistors described in the above embodiments can be used as appropriate as the transistors 716 and 717. Thereby, a highly reliable liquid crystal display device can be provided.

The shapes of the first pixel electrode layer electrically connected to the transistor 716 and the second pixel electrode layer electrically connected to the transistor 717 are described. The shapes of the first pixel electrode layer and the second pixel electrode layer are separated by a slit. The first pixel electrode layer has a V-shaped shape, and the second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

A gate electrode of the transistor 716 is connected to the gate wiring 712, and a gate electrode of the transistor 717 is connected to the gate wiring 713. Different gate signals are given to the gate wiring 712 and the gate wiring 713 so that the operation timings of the transistors 716 and 717 are different, whereby the alignment of the liquid crystal can be controlled.

Further, a storage capacitor may be formed using the capacitor wiring 710, a gate insulating film functioning as a dielectric, and a capacitor electrode electrically connected to the first pixel electrode layer or the second pixel electrode layer.

The multi-domain structure includes a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 includes a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween, and the second liquid crystal element 719 includes a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. Consists of.

Note that the pixel circuit illustrated in FIG. 20B is not limited thereto. For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG.

[Organic EL display device]
Another example of the circuit configuration of the pixel is shown in FIG. Here, a pixel structure of a display device using an organic EL element is shown.

In the organic EL element, by applying a voltage to the light-emitting element, electrons are injected from one of the pair of electrodes and holes from the other into the layer containing the light-emitting organic compound, and a current flows. Then, by recombination of electrons and holes, the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

FIG. 20C illustrates an example of an applicable pixel circuit. Here, an example in which two n-channel transistors are used for one pixel is shown. Note that the metal oxide film of one embodiment of the present invention can be used for a channel formation region of an n-channel transistor. In addition, digital time grayscale driving can be applied to the pixel circuit.

An applicable pixel circuit configuration and pixel operation when digital time gray scale driving is applied will be described.

The pixel 720 includes a switching transistor 721, a driving transistor 722, a light-emitting element 724, and a capacitor 723. The switching transistor 721 has a gate electrode layer connected to the scan line 726, a first electrode (one of the source electrode layer and the drain electrode layer) connected to the signal line 725, and a second electrode (the source electrode layer and the drain electrode layer). Is connected to the gate electrode layer of the driving transistor 722. In the driving transistor 722, the gate electrode layer is connected to the power supply line 727 via the capacitor 723, the first electrode is connected to the power supply line 727, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 724. It is connected. The second electrode of the light emitting element 724 corresponds to the common electrode 728. The common electrode 728 is electrically connected to a common potential line formed over the same substrate.

The transistor described in the above embodiment can be used as appropriate as the switching transistor 721 and the driving transistor 722. Thereby, an organic EL display device with high reliability can be provided.

The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. Note that the low power supply potential is lower than the high power supply potential set to the power supply line 727. For example, GND, 0 V, or the like can be set as the low power supply potential. A high power supply potential and a low power supply potential are set so as to be equal to or higher than the threshold voltage in the forward direction of the light emitting element 724, and by applying the potential difference to the light emitting element 724, a current is passed through the light emitting element 724 to emit light. Note that the forward voltage of the light-emitting element 724 refers to a voltage for obtaining desired luminance, and includes at least a forward threshold voltage.

Note that the capacitor 723 can be omitted by substituting the gate capacitance of the driving transistor 722. With respect to the gate capacitance of the driving transistor 722, a capacitance may be formed between the channel formation region and the gate electrode layer.

Next, a signal input to the driving transistor 722 will be described. In the case of the voltage input voltage driving method, a video signal that causes the driving transistor 722 to be sufficiently turned on or off is input to the driving transistor 722. Note that a voltage higher than the voltage of the power supply line 727 is applied to the gate electrode layer of the driving transistor 722 in order to operate the driving transistor 722 in a linear region. In addition, a voltage equal to or higher than a value obtained by adding the threshold voltage Vth of the driving transistor 722 to the power supply line voltage is applied to the signal line 725.

In the case of performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 722 to the forward voltage of the light emitting element 724 is applied to the gate electrode layer of the driving transistor 722. Note that a video signal is input so that the driving transistor 722 operates in a saturation region, and a current is supplied to the light-emitting element 724. Further, in order to operate the driving transistor 722 in the saturation region, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By making the video signal analog, current corresponding to the video signal can be passed through the light-emitting element 724 to perform analog gradation driving.

Note that the structure of the pixel circuit is not limited to the pixel structure illustrated in FIG. For example, a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be added to the pixel circuit illustrated in FIG.

When the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIG. 20, the source electrode (first electrode) is electrically connected to the low potential side, and the drain electrode (second electrode) is electrically connected to the high potential side. It is assumed that it is connected. Further, the potential of the first gate electrode is controlled by a control circuit or the like, and the potential exemplified above can be input to the second gate electrode, such as a potential lower than the potential applied to the source electrode by a wiring (not shown). do it.

For example, in this specification and the like, a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element have various forms or have various elements. I can do it. As an example of a display element, a display device, a light emitting element, or a light emitting device, an EL (electroluminescence) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED) , Blue LED, etc.), transistor (transistor that emits light in response to current), electron-emitting device, liquid crystal device, electronic ink, electrophoretic device, grating light valve (GLV), plasma display (PDP), MEMS (micro electro Mechanical system), digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interference modulation) element, electrowetting element, piezoelectric ceramic display , Carbon nanotubes, etc., by an electric magnetic action, those having contrast, brightness, reflectance, a display medium such as transmittance changes. An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-Conduction Electron-Emitter Display), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink or an electrophoretic element is electronic paper.

This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 9)
A semiconductor device according to one embodiment of the present invention includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image) Device). In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book, a video camera, a camera such as a digital still camera, or a goggle type Display (head-mounted display), navigation system, sound playback device (car audio, digital audio player, etc.), copier, facsimile, printer, printer multifunction device, automatic teller machine (ATM), vending machine, etc. . Specific examples of these electronic devices are shown in FIGS.

FIG. 12A illustrates a portable game machine, which includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, speakers 906, operation keys 907, a stylus 908, and the like. Note that although the portable game machine illustrated in FIG. 12A includes the two display portions 903 and 904, the number of display portions included in the portable game device is not limited thereto.

FIG. 12B illustrates a portable data terminal, which includes a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, operation keys 916, and the like. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connection portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connection portion 915. is there. It is good also as a structure which switches the image | video in the 1st display part 913 according to the angle between the 1st housing | casing 911 and the 2nd housing | casing 912 in the connection part 915. FIG. Further, a display device to which a function as a position input device is added to at least one of the first display portion 913 and the second display portion 914 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.

FIG. 12C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

FIG. 12D illustrates an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, a refrigerator door 933, and the like.

FIG. 12E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. is there. The video on the display portion 943 may be switched according to the angle between the first housing 941 and the second housing 942 in the connection portion 946.

FIG. 12F illustrates an ordinary automobile, which includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.

(Embodiment 10)
In this embodiment, an example of using RFID according to one embodiment of the present invention will be described with reference to FIGS. Although RFID has a wide range of uses, for example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 13A), packaging containers (wrapping paper and bottles, etc.) Etc., see FIG. 13C), recording medium (DVD software, video tape, etc., see FIG. 13B), vehicles (bicycles, etc., see FIG. 13D), personal items (such as bags and glasses) , Articles such as foods, plants, animals, human bodies, clothing, daily necessities, medical products including drugs and drugs, or electronic devices (liquid crystal display devices, EL display devices, television devices, or mobile phones), Alternatively, it can be used by being provided on a tag (see FIGS. 13E and 13F) attached to each article.

The RFID 4000 according to one embodiment of the present invention is fixed to an article by being attached to or embedded in the surface. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin and fixed to each article. The RFID 4000 according to one embodiment of the present invention achieves small size, thinness, and light weight, and thus does not impair the design of the product itself even after being fixed to the product. In addition, an authentication function can be provided by providing the RFID 4000 according to one embodiment of the present invention on bills, coins, securities, bearer bonds, certificates, etc., and if this authentication function is utilized, counterfeiting can be performed. Can be prevented. In addition, by attaching an RFID according to one embodiment of the present invention to packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, or the like, the efficiency of a system such as an inspection system is improved. be able to. Further, even with vehicles, security against theft can be improved by attaching the RFID according to one embodiment of the present invention.

As described above, by using the RFID according to one embodiment of the present invention for each application described in this embodiment, operating power including writing and reading of information can be reduced; thus, the maximum communication distance can be increased. It becomes possible. In addition, since the information can be held for a very long period even when the power is cut off, it can be suitably used for applications where the frequency of writing and reading is low.

Note that in the above embodiment, an example in which an oxide semiconductor is used for a channel or the like is described; however, one embodiment of the present invention is not limited thereto. For example, in the channel and its vicinity, the source region, the drain region, etc., depending on the case or depending on the situation, Si (silicon), Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), etc. You may form with the material which has.

In this example, the results of investigation on desorption of oxygen contained in ruthenium oxide by temperature programmed desorption analysis (TDS analysis) will be described.

Thermal desorption analysis is to obtain a mass spectrum of desorbed components from a sample for each temperature by mass analysis of gas molecules emitted while heating the sample with infrared in high vacuum. Since the background vacuum degree of the measuring apparatus is 1.33 × 10 ⁻⁷ Pa (10 ⁻⁹ Torr), it is possible to analyze a trace amount component. In this example, EMD-WA1000S manufactured by ESCO was used.

Moreover, the peak in the curve showing the result of the TDS analysis is a peak that appears when atoms or molecules contained in the analyzed sample are released to the outside. Note that the total amount of atoms or molecules released to the outside corresponds to the integrated value of the peak. Therefore, the total amount of atoms or molecules contained in the ruthenium oxide film can be evaluated based on the level of the peak intensity.

In this example, a ruthenium oxide film was formed on a silicon wafer by a sputtering method. The ruthenium oxide film formation conditions were an oxygen flow rate of 20 sccm, a pressure in the processing chamber of 0.4 Pa, 100 W (DC), a target-substrate distance of 60 mm, and a substrate temperature of 150 ° C. The film thickness of ruthenium oxide was set to five conditions of 10 nm, 30 nm, 50 nm, 100 nm, and 200 nm. Here, ruthenium oxide having a thickness of 10 nm is sample A, 30 nm ruthenium oxide is sample B, 50 nm ruthenium oxide is sample C, 100 nm ruthenium oxide is sample D, and 200 nm ruthenium oxide is sample E. To do.

Next, the results of TDS analysis performed on Sample A to Sample E are shown in FIG. FIG. 15 is a graph showing the amount of released oxygen molecules with respect to the substrate temperature.

From the TDS analysis results shown in FIG. 15, the release of oxygen molecules was confirmed even when the ruthenium oxide was 10 nm. It was also confirmed that the amount of released oxygen molecules increased as the ruthenium oxide film thickness increased.

From the above results, it was confirmed that ruthenium oxide is a film capable of desorbing oxygen by heating.

In this example, the behavior of oxygen in a silicon oxide film by heat treatment is described using secondary ion mass spectrometry (SIMS).

For SIMS, a quadrupole secondary ion mass spectrometer PHI ADEPT1010 manufactured by ULVAC-PHI Co., Ltd. was used.

A method for manufacturing the sample is described below.

First, a quartz substrate was prepared, and a silicon oxide film was formed on the quartz substrate using ¹⁸ O ₂ . Note that the silicon oxide film was formed by a sputtering method. Specifically, using a silicon oxide target, in an atmosphere containing 25 sccm of argon and 25 sccm of oxygen ( ¹⁸ O ₂ ), the pressure is controlled to 0.4 Pa, the substrate heating temperature during film formation is 100 ° C., and the film formation power Was formed to a thickness of 300 nm at 1.5 kW (13.56 MHz).

Here, ¹⁸ O ₂ refers to an oxygen molecule composed of an isotope of oxygen atom ( ¹⁸ O) having an atomic weight of 18.

Next, a silicon oxide film was formed over the silicon oxide film using ¹⁸ O ₂ . Note that the silicon oxide film was formed by a sputtering method. Specifically, using a silicon oxide target, in an atmosphere containing 25 sccm of argon and 25 sccm of oxygen, the pressure is controlled to 0.4 Pa, the substrate heating temperature during film formation is 100 ° C., and the film formation power is 1.5 kW ( The film was formed with a thickness of 100 nm. The silicon oxide film does not intentionally contain ¹⁸ O.

The sample manufactured as described above was subjected to heat treatment at 150 ° C., 250 ° C., 350 ° C., and 550 ° C. for 1 hour in a nitrogen atmosphere. In addition, a sample not particularly subjected to heat treatment was also prepared (referred to as as-depo).

FIG. 16 is a result of analyzing the depth direction of ¹⁸ O by SIMS. The displays of as-depo, 150 ° C., 250 ° C., 350 ° C., and 550 ° C. shown in FIG. 16 respectively correspond to the heat treatment conditions. Also, the right side of the broken line shown in FIG. ^16, showing a film forming the silicon oxide film (silicon oxide ⁽¹⁸ _{O 2)} hereinafter) using a 18 _{O 2.}

FIG. 16 shows that ¹⁸ O diffuses from the silicon oxide film formed using ¹⁸ O ₂ into the silicon oxide film by heat treatment. Further, as the temperature of the heat treatment is high, ¹⁸ O ^{18 O} ₂ of a silicon oxide film formed using the silicon oxide film was found to often amounts diffuses.

From the above, it was found that oxygen was diffused by about 40 nm in the silicon oxide film even in the heat treatment at about 150 ° C.

This example shows that oxygen diffuses in the silicon oxide film by heat treatment.

DESCRIPTION OF SYMBOLS 10 Electron gun chamber 12 Optical system 14 Sample chamber 16 Optical system 18 Camera 20 Observation chamber 22 Film chamber 24 Electron 28 Material 32 Fluorescent plate 400 Substrate 402 Base insulating film 404 Oxide semiconductor 404a Oxide semiconductor 404b Oxide semiconductor 404c Oxide semiconductor 405 Conductive film 406a source electrode 406b drain electrode 408 gate insulating film 410 gate electrode 410a conductive film 410b conductive film 411 gate electrode 411a conductive film 411b conductive film 411c conductive film 412 protective insulating film 600 substrate 602 gate insulating film 604 oxide semiconductor 606a source electrode 606b Drain electrode 608 Gate insulating film 610 Gate electrode 610a Conductive film 610b Conductive film 611 Gate electrode 611a Conductive film 611b Conductive film 611c Conductive film 612 Protective insulating film 620 Gate electrode 620a Electrode film 620b Conductive film 621 Gate electrode 621a Conductive film 621b Conductive film 621c Conductive film 700 Substrate 701 Pixel portion 702 Scan line driver circuit 703 Scan line driver circuit 704 Signal line driver circuit 710 Capacitance wiring 712 Gate wiring 713 Gate wiring 714 Drain electrode layer 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 Pixel 721 Switching transistor 722 Driving transistor 723 Capacitance element 724 Light emitting element 725 Signal line 726 Scan line 727 Power line 728 Common electrode 800 RFID tag 801 Communication device 802 Antenna 803 Radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulator circuit 808 Modulator circuit 809 Logic circuit 810 Memory circuit 811 ROM
901 Case 902 Case 903 Display unit 904 Display unit 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Case 912 Case 913 Display unit 914 Display unit 915 Connection unit 916 Operation key 921 Case 922 Display unit 923 Keyboard 924 Pointing device 931 Case 932 Refrigerating room door 933 Freezing room door 941 Case 942 Case 943 Display unit 944 Operation key 945 Lens 946 Connection unit 951 Car body 952 Wheel 953 Dashboard 954 Light 1189 ROM interface 1190 Board 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
1200 memory element 1201 circuit 1202 circuit 1203 switch 1204 switch 1206 logic element 1207 capacitor element 1208 capacitor element 1209 transistor 1210 transistor 1213 transistor 1214 transistor 1220 circuit 2001 impurity region 2003 gate electrode 2004 gate insulating film 2005 sidewall insulating layer 2100 transistor 2200 transistor 2201 substrate 2202 Wiring 2203 Plug 2204 Element isolation layer 2205 Wiring 2206 Wiring 2207 Insulating layer 2208 Insulating layer 2211 Semiconductor substrate 2212 Insulating layer 2213 Gate electrode 2214 Gate insulating film 2215 Drain region 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistor 3300 Transistor 3400 Capacitor element 4000 RFID

Claims (11)

An oxide semiconductor;
A gate electrode;
A gate insulating film,
The oxide semiconductor has a fin shape,
The gate electrode faces an upper surface and a side surface of the oxide semiconductor;
The gate insulating film is provided between the oxide semiconductor and the gate electrode;
The gate electrode includes at least a first layer and a second layer;
The first layer is in contact with the gate insulating film;
The semiconductor device, wherein the first layer has an oxygen concentration lower than that of the second layer. In claim 1,
The semiconductor device is characterized in that the first layer is made of a material having higher Gibbs free energy of oxidation reaction than the gate insulating film. In claim 1 or claim 2,
The semiconductor device, wherein the first layer includes one or more elements selected from silver, copper, ruthenium, iridium, platinum, and gold. In any one of Claim 1 thru | or 3,
A semiconductor device, wherein the gate insulating film has oxygen permeability. An oxide semiconductor;
A first gate electrode;
A second gate electrode;
A first gate insulating film;
A second gate insulating film,
The oxide semiconductor has a fin shape,
The first gate electrode faces an upper surface and a side surface of the oxide semiconductor;
The second gate electrode faces a lower surface of the oxide semiconductor;
The first gate insulating film is provided between the oxide semiconductor and the first gate electrode;
The second gate insulating film is provided between the oxide semiconductor and the second gate electrode;
The first gate electrode includes at least a first layer and a second layer;
The second gate electrode includes at least a third layer and a fourth layer,
The first layer is in contact with the first gate insulating film;
The third layer is in contact with the second gate insulating film;
The first layer has a lower oxygen concentration than the second layer,
The semiconductor device, wherein the third layer has an oxygen concentration lower than that of the fourth layer. In claim 5,
The first layer is made of a material having a higher Gibbs free energy for oxidation reaction than the first gate insulating film,
The semiconductor device, wherein the third layer is made of a material having a higher Gibbs free energy for oxidation reaction than the second gate insulating film. In claim 5 or claim 6,
The semiconductor device, wherein the first layer and the third layer contain one or more elements selected from silver, copper, ruthenium, iridium, platinum and gold. In any one of Claim 5 thru | or 7,
The semiconductor device, wherein the first gate insulating film and the second gate insulating film have oxygen permeability. A semiconductor device according to any one of claims 1 to 8,
An electronic apparatus having at least one of a microphone, a speaker, and operation keys. Forming an oxide semiconductor having a fin shape;
Forming a gate insulating film on the oxide semiconductor;
Forming a gate electrode including at least an oxide layer so as to face an upper surface and a side surface of the oxide semiconductor through the gate insulating film;
A method for manufacturing a semiconductor device, in which oxygen is supplied from the gate electrode to the oxide semiconductor through the gate insulating film by performing heat treatment. Forming a second gate electrode including at least an oxide layer;
Forming a second gate insulating film on the second gate electrode;
An oxide semiconductor having a fin shape is formed over the second gate insulating film so as to overlap the second gate electrode,
Forming a first gate insulating film on the oxide semiconductor;
Forming a first gate electrode including at least an oxide layer so as to face an upper surface and a side surface of the oxide semiconductor through the first gate insulating film;
By performing heat treatment, oxygen is supplied from the first gate electrode to the oxide semiconductor through the first gate insulating film, and at the same time, the second gate insulating film is used to supply the second A method for manufacturing a semiconductor device, wherein oxygen is supplied from a gate electrode to the oxide semiconductor.