JP2015035554A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2015035554A JP2015035554A JP2013166808A JP2013166808A JP2015035554A JP 2015035554 A JP2015035554 A JP 2015035554A JP 2013166808 A JP2013166808 A JP 2013166808A JP 2013166808 A JP2013166808 A JP 2013166808A JP 2015035554 A JP2015035554 A JP 2015035554A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- chip
- terminal
- resin sealing
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013166808A JP2015035554A (ja) | 2013-08-09 | 2013-08-09 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013166808A JP2015035554A (ja) | 2013-08-09 | 2013-08-09 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2015035554A true JP2015035554A (ja) | 2015-02-19 |
| JP2015035554A5 JP2015035554A5 (enExample) | 2016-09-23 |
Family
ID=52543869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013166808A Pending JP2015035554A (ja) | 2013-08-09 | 2013-08-09 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2015035554A (enExample) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018170331A (ja) * | 2017-03-29 | 2018-11-01 | 旭化成エレクトロニクス株式会社 | 半導体装置 |
| CN108831871A (zh) * | 2018-06-08 | 2018-11-16 | 郑州云海信息技术有限公司 | 一种提升qfn封装零件焊接质量的设计方法 |
| KR20200087200A (ko) * | 2017-12-27 | 2020-07-20 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 |
| CN112635411A (zh) * | 2019-09-24 | 2021-04-09 | 英飞凌科技股份有限公司 | 具有顶侧或底侧冷却的半导体封装 |
| JP2022118411A (ja) * | 2021-02-02 | 2022-08-15 | ローム株式会社 | 半導体装置および検査方法 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11307675A (ja) * | 1998-04-20 | 1999-11-05 | Matsushita Electron Corp | 樹脂封止型半導体装置及びその製造方法 |
| JP2001177007A (ja) * | 1999-12-21 | 2001-06-29 | Hitachi Ltd | 半導体装置及びその製造方法 |
| JP2003289128A (ja) * | 2002-01-23 | 2003-10-10 | Matsushita Electric Ind Co Ltd | 回路部品内蔵モジュールおよびその製造方法 |
| JP2007503721A (ja) * | 2003-08-26 | 2007-02-22 | アドバンスド インターコネクト テクノロジーズ リミテッド | リバーシブル・リードレス・パッケージとその製造および使用方法 |
-
2013
- 2013-08-09 JP JP2013166808A patent/JP2015035554A/ja active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11307675A (ja) * | 1998-04-20 | 1999-11-05 | Matsushita Electron Corp | 樹脂封止型半導体装置及びその製造方法 |
| JP2001177007A (ja) * | 1999-12-21 | 2001-06-29 | Hitachi Ltd | 半導体装置及びその製造方法 |
| JP2003289128A (ja) * | 2002-01-23 | 2003-10-10 | Matsushita Electric Ind Co Ltd | 回路部品内蔵モジュールおよびその製造方法 |
| JP2007503721A (ja) * | 2003-08-26 | 2007-02-22 | アドバンスド インターコネクト テクノロジーズ リミテッド | リバーシブル・リードレス・パッケージとその製造および使用方法 |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018170331A (ja) * | 2017-03-29 | 2018-11-01 | 旭化成エレクトロニクス株式会社 | 半導体装置 |
| KR20200087200A (ko) * | 2017-12-27 | 2020-07-20 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 |
| KR102351764B1 (ko) * | 2017-12-27 | 2022-01-14 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 |
| US11335619B2 (en) | 2017-12-27 | 2022-05-17 | Mitsubishi Electric Corporation | Semiconductor device |
| CN108831871A (zh) * | 2018-06-08 | 2018-11-16 | 郑州云海信息技术有限公司 | 一种提升qfn封装零件焊接质量的设计方法 |
| CN112635411A (zh) * | 2019-09-24 | 2021-04-09 | 英飞凌科技股份有限公司 | 具有顶侧或底侧冷却的半导体封装 |
| JP2022118411A (ja) * | 2021-02-02 | 2022-08-15 | ローム株式会社 | 半導体装置および検査方法 |
| JP7636186B2 (ja) | 2021-02-02 | 2025-02-26 | ローム株式会社 | 半導体装置および検査方法 |
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