JP2014504015A5 - - Google Patents

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Publication number
JP2014504015A5
JP2014504015A5 JP2013544873A JP2013544873A JP2014504015A5 JP 2014504015 A5 JP2014504015 A5 JP 2014504015A5 JP 2013544873 A JP2013544873 A JP 2013544873A JP 2013544873 A JP2013544873 A JP 2013544873A JP 2014504015 A5 JP2014504015 A5 JP 2014504015A5
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JP
Japan
Prior art keywords
nitride layer
forming
region
silicon
dielectric region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2013544873A
Other languages
English (en)
Japanese (ja)
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JP2014504015A (ja
JP5727036B2 (ja
Filing date
Publication date
Priority claimed from US12/973,631 external-priority patent/US8263458B2/en
Application filed filed Critical
Publication of JP2014504015A publication Critical patent/JP2014504015A/ja
Publication of JP2014504015A5 publication Critical patent/JP2014504015A5/ja
Application granted granted Critical
Publication of JP5727036B2 publication Critical patent/JP5727036B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2013544873A 2010-12-20 2011-12-19 電荷トラップ電界効果トランジスタにおけるプロセスマージンのエンジニアリング Expired - Fee Related JP5727036B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/973,631 US8263458B2 (en) 2010-12-20 2010-12-20 Process margin engineering in charge trapping field effect transistors
US12/973,631 2010-12-20
PCT/US2011/065923 WO2012087974A2 (en) 2010-12-20 2011-12-19 Process margin engineering in charge trapping field effect transistors

Publications (3)

Publication Number Publication Date
JP2014504015A JP2014504015A (ja) 2014-02-13
JP2014504015A5 true JP2014504015A5 (enExample) 2014-03-27
JP5727036B2 JP5727036B2 (ja) 2015-06-03

Family

ID=46234933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013544873A Expired - Fee Related JP5727036B2 (ja) 2010-12-20 2011-12-19 電荷トラップ電界効果トランジスタにおけるプロセスマージンのエンジニアリング

Country Status (6)

Country Link
US (1) US8263458B2 (enExample)
EP (1) EP2656382A4 (enExample)
JP (1) JP5727036B2 (enExample)
KR (1) KR20140007824A (enExample)
CN (1) CN103380489B (enExample)
WO (1) WO2012087974A2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101847629B1 (ko) * 2012-02-10 2018-04-10 삼성전자주식회사 반도체 소자
US20150255480A1 (en) * 2012-10-01 2015-09-10 Spansion Llc Method to Improve Charge Trap Flash Memory Top Oxide Quality
US8836012B2 (en) 2012-10-04 2014-09-16 Spansion Llc Spacer design to prevent trapped electrons
US8866213B2 (en) 2013-01-30 2014-10-21 Spansion Llc Non-Volatile memory with silicided bit line contacts
US9614105B2 (en) 2013-04-22 2017-04-04 Cypress Semiconductor Corporation Charge-trap NOR with silicon-rich nitride as a charge trap layer
WO2014175202A1 (ja) * 2013-04-23 2014-10-30 ピーエスフォー ルクスコ エスエイアールエル 装置の製造方法
US8993457B1 (en) * 2014-02-06 2015-03-31 Cypress Semiconductor Corporation Method of fabricating a charge-trapping gate stack using a CMOS process flow

Family Cites Families (45)

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Publication number Priority date Publication date Assignee Title
US4870470A (en) * 1987-10-16 1989-09-26 International Business Machines Corporation Non-volatile memory cell having Si rich silicon nitride charge trapping layer
US6498064B2 (en) * 2001-05-14 2002-12-24 Vanguard International Semiconductor Corporation Flash memory with conformal floating gate and the method of making the same
US6974995B1 (en) 2001-12-27 2005-12-13 Advanced Micro Devices, Inc. Method and system for forming dual gate structures in a nonvolatile memory using a protective layer
US6808992B1 (en) 2002-05-15 2004-10-26 Spansion Llc Method and system for tailoring core and periphery cells in a nonvolatile memory
US7566929B2 (en) * 2002-07-05 2009-07-28 Samsung Electronics Co., Ltd. Nonvolatile memory devices having floating gate electrodes with nitrogen-doped layers on portions thereof
US6828212B2 (en) * 2002-10-22 2004-12-07 Atmel Corporation Method of forming shallow trench isolation structure in a semiconductor device
JP2004303918A (ja) * 2003-03-31 2004-10-28 Renesas Technology Corp 半導体装置の製造方法および半導体装置
JP4040534B2 (ja) * 2003-06-04 2008-01-30 株式会社東芝 半導体記憶装置
US6943401B1 (en) 2003-09-11 2005-09-13 Advanced Micro Devices, Inc. Flash memory cell with drain and source formed by diffusion of a dopant from a silicide
US7301193B2 (en) 2004-01-22 2007-11-27 Spansion Llc Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell
TWI244166B (en) 2004-03-11 2005-11-21 Ememory Technology Inc A non-volatile memory cell and fabricating method thereof
US6927129B1 (en) 2004-04-08 2005-08-09 Advanced Micro Devices Narrow wide spacer
US7029975B1 (en) 2004-05-04 2006-04-18 Advanced Mirco Devices, Inc. Method and apparatus for eliminating word line bending by source side implantation
US6987696B1 (en) 2004-07-06 2006-01-17 Advanced Micro Devices, Inc. Method of improving erase voltage distribution for a flash memory array having dummy wordlines
US7170130B2 (en) 2004-08-11 2007-01-30 Spansion Llc Memory cell with reduced DIBL and Vss resistance
US7151028B1 (en) 2004-11-04 2006-12-19 Spansion Llc Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability
US7488657B2 (en) 2005-06-17 2009-02-10 Spansion Llc Method and system for forming straight word lines in a flash memory array
US20070037371A1 (en) 2005-08-10 2007-02-15 Zhigang Wang Method of forming gate electrode structures
US7675104B2 (en) 2006-07-31 2010-03-09 Spansion Llc Integrated circuit memory system employing silicon rich layers
US8809936B2 (en) 2006-07-31 2014-08-19 Globalfoundries Inc. Memory cell system with multiple nitride layers
US8143661B2 (en) 2006-10-10 2012-03-27 Spansion Llc Memory cell system with charge trap
US20080142874A1 (en) 2006-12-16 2008-06-19 Spansion Llc Integrated circuit system with implant oxide
US20080153224A1 (en) 2006-12-21 2008-06-26 Spansion Llc Integrated circuit system with memory system
US20080150011A1 (en) 2006-12-21 2008-06-26 Spansion Llc Integrated circuit system with memory system
US20080149990A1 (en) 2006-12-21 2008-06-26 Spansion Llc Memory system with poly metal gate
US20080150000A1 (en) 2006-12-21 2008-06-26 Spansion Llc Memory system with select gate erase
CN102522430B (zh) * 2007-03-23 2014-10-22 株式会社半导体能源研究所 半导体装置及其制造方法
US7732276B2 (en) 2007-04-26 2010-06-08 Spansion Llc Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications
US8367537B2 (en) 2007-05-10 2013-02-05 Spansion Llc Flash memory cell with a flair gate
TW200847327A (en) * 2007-05-25 2008-12-01 Dongbu Hitek Co Ltd Semiconductor device and methods of manufacturing the same
US7829936B2 (en) 2007-10-17 2010-11-09 Spansion Llc Split charge storage node inner spacer process
JP5405737B2 (ja) * 2007-12-20 2014-02-05 スパンション エルエルシー 半導体装置およびその製造方法
JP5208537B2 (ja) * 2008-02-19 2013-06-12 株式会社東芝 不揮発性記憶素子
US20090261406A1 (en) 2008-04-17 2009-10-22 Suh Youseok Use of silicon-rich nitride in a flash memory device
US8987092B2 (en) 2008-04-28 2015-03-24 Spansion Llc Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges
US7867899B2 (en) 2008-04-29 2011-01-11 Spansion, Llc Wordline resistance reduction method and structure in an integrated circuit memory device
US7951704B2 (en) 2008-05-06 2011-05-31 Spansion Llc Memory device peripheral interconnects and method of manufacturing
US8669597B2 (en) 2008-05-06 2014-03-11 Spansion Llc Memory device interconnects and method of manufacturing
US7998846B2 (en) 2008-09-12 2011-08-16 Spansion Llc 3-D integrated circuit system and method
US20100078814A1 (en) 2008-09-29 2010-04-01 Roy Alok Nandini System and method for using porous low dielectric films
US7907448B2 (en) 2008-10-07 2011-03-15 Spansion Llc Scaled down select gates of NAND flash memory cell strings and method of forming same
US8076199B2 (en) 2009-02-13 2011-12-13 Spansion Llc Method and device employing polysilicon scaling
US8487373B2 (en) 2009-04-29 2013-07-16 Spanion Llc SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same
US8551858B2 (en) 2010-02-03 2013-10-08 Spansion Llc Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory
JP5232835B2 (ja) * 2010-07-28 2013-07-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置

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