Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
  • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
  • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/031—Manufacture or treatment of data-storage electrodes
  • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

Definitions

• CT-NAND NAND integrated circuit Figure 1 shows an exemplary CT-NAND based flash memory IC.
• the flash memory IC 100 includes a CT-NAND memory cell array 1 10, control circuits 120, column decoders 130, row decoders 140, input/output (I/O) buffers 150, and the like fabricated on a monolithic semiconductor substrate.
• the control circuits 120, column decoders 130, row decoders 140, I/O buffers 150, and the like operate to read and write data 160 at an address 170, 175 in the memory cell array 1 10 in accordance with various control signals 180 received by, internal to, and/or output from the flash memory IC 100.
• the circuits of the flash memory IC 100 is well known in the art and therefore those aspects of the flash memory IC 100 not particular to embodiments of the present technology will not be discussed further.
• the CT-NAND memory cell array 1 10 includes a plurality of CT field effect transistors (FET) 210, a plurality of drain select gates 220, a plurality of source select gates 230, a plurality of bit lines 240, a plurality of word lines 250, a plurality of drain select signal lines 260, and a plurality of source select signal lines 270.
• Each column of the array 1 10 includes a drain select gate 220, a plurality of CT-FETs 210, and a source select gate 230 serially connected source to drain between a corresponding bit line 240 and a ground potential 280.
• each of a plurality of CT-FETs 210 in each row of the array 1 10 arc coupled to a corresponding word line 250.
• the gate of each drain select gate 220 is connected to a corresponding drain select signal line 260.
• the gate of each source select gate 230 is connected to a corresponding drain select signal line 270.
• the CT-FETs may be silicon-oxide-nitridc-oxidc- silicon (SONOS) FETs or the like.
• SONOS silicon-oxide-nitridc-oxidc- silicon
• the CT-NAND memory cell array 1 10 is well known in the art and therefore those aspects of the CT-NAND memory cell array 1 10 not particular to embodiments of the present technology will not be discussed further. During fabrication of a CT- A D memory cell array 1 10 there arc variances in various processes.
• the thickness of a deposited layer may vary from one wafer to another and from one region to another on a given wafer.
• the amount of material removed by an etching process may vary from one wafer to another and from one region to another on a given wafer. Accordingly, there is a continued need for improved fabrication techniques that can compensate for process variances in one or more fabrication processes.
• a fabrication method includes forming a plurality of shallow trench isolation regions on a substrate.
• a tunneling dielectric region is also formed on a substrate.
• a first nitride layer is formed on the tunneling dielectric region and shallow trench isolation regions.
• a portion of the first nitride layer is etched back to the tops of the trench isolation regions.
• a second nitride layer is formed on the etched back first nitride layer. Portions of the first and second nitride layers are oxidized to form a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region.
• a gate region is then formed on the blocking dielectric region.
• a fabrication method includes forming a plurality of shallow trench isolation regions on a substrate, wherein the tops of the shallow trench isolation regions extend above the substrate by a given amount.
• a tunneling dielectric region is formed on a substrate.
• a nitride layer is formed on the tunneling dielectric region and shallow trench isolation regions, wherein a thickness of the nitride layer is approximately half of a given amount that the tops of the shallow trench isolation regions extend above the substrate.
• a portion of the nitride layer is etched back to the tops of the trench isolation regions to form a charge trapping region between the trenches.
• a blocking dielectric region is formed on the charge trapping region, and a gate region is formed on the blocking dielectric region.
• Figure I shows a block diagram of an exemplary CT-NAND based flash memory IC according to the conventional art.
• Figure 2 shows a block diagram of an exemplary memory cell array according to the conventional art.
• Figure 3 shows a block diagram of a memory cell array structure, in accordance with one embodiment of the present technology.
• Figures 4A and 4B show a flow diagram of a method of fabricating a charge trapping field effect transistor, in accordance with one embodiment of the present technology.
• FIGS. 5A-5I show block diagrams illustrating fabrication of a charge trapping field effect transistor, in accordance with one embodiment of the present technology.
• Figures 6A and 6B show block diagrams illustrating the difference in process fabrication margins for a thin nitride layer and a thick nitride layer used for a charge trapping region, in accordance with one embodiment of the present technology.
• the use of the disjunctive is intended to include the conjunctive.
• the use of definite or indefinite articles is not intended to indicate cardinality.
• a reference to "the" object or "a” object is intended to denote also one of a possible plurality of such objects.
• FIG. 3 a memory cell array structure, in accordance with one embodiment of the present technology, is shown.
• the memory cell array may be a CT- AND memory cell array 1 10.
• each column of CT-FETs may be separated by a shallow trench isolation (STI) region 305.
• STI shallow trench isolation
• Each CT-FET may include a drain region 310, a source region 315, a channel region 320, a tunneling dielectric region 325 (also commonly referred to as a bottom dielectric region), a charge trapping region 330, a blocking dielectric region 335 (also commonly referred to as a top dielectric region), and a gate region 340.
• the source and drain regions 310, 315 may be semiconductor regions of the substrate 345 having a heavy doping concentration of a first type of impurity.
• the source and drain regions 310, 315 may be silicon heavily doped with phosphorous or arsenic.
• the channel region 320 may be a semiconductor region of the substrate 345 having moderate doping concentration of a second type of impurity, disposed laterally between the source and drain regions 310, 315.
• the channel region 320 may be silicon moderately doped with boron.
• the tunneling dielectric region 325 may be a dielectric layer disposed over the channel region 320 and adjacent portions of the source and drain regions 310, 315.
• the tunneling dielectric region 325 may be silicon oxide, oxynitridc, silicon oxynitridc, or the like layer.
• the charge trapping region 330 may be a dielectric, semiconductor or the like layer disposed between the tunneling dielectric region 325 and the blocking dielectric region 335.
• the charge trapping region 330 may be a nitride, silicon-rich-nitride, or the like layer.
• the blocking dielectric region 335 may be a dielectric layer disposed between the charge trapping region 330 and the gate region 340.
• the blocking dielectric region 335 may be a silicon oxide, oxynitridc, silicon oxynitridc, or the like layer.
• the gate region 340 may be a semiconductor or a conductor layer disposed on the blocking dielectric region 335 opposite the charge trapping region 330.
• the gate region 340 may be a polysilicon layer having a heavy doping concentration of the first type of impurity.
• FIGS 4A-4B a method of fabricating a CT-FET, in accordance with one embodiment of the present technology, is shown.
• the method of fabricating the CT- FET will be further explained with reference to Figures 5A-51, which illustrates fabrication of the CT-FET, in accordance with one embodiment of the present technology.
• the process begins, at 405, with various initial processes upon a semiconductor wafer substrate 502, such as cleaning, depositing, doping, etching and/or the like to form one or more regions.
• the substrate 502 may be a semiconductor doped at a first concentration with a first dopant type.
• the substrate 502 may be silicon moderately doped with boron (P).
• a plurality of shallow trench isolation regions arc formed.
• a sacrificial oxide 504 may be formed on the substrate 502 by any well known oxidation process.
• a photo resist is then deposited on the sacrificial oxide and patterned by any well known photolithography process to form a shallow trench isolation (ST1) mask 506.
• ST1 mask 506 The substrate 502 and sacrificial oxide 504 in the memory cell array region exposed by the STI mask 506 is then selectively etched by any well known etching process to form a plurality of trenches 508.
• the trenches 508 may be filled with a dielectric 510.
• a conformal oxide, spin on glass or the like is deposited.
• the dielectric layer 510 may then be etched back, by any well known etching process or chemical mechanical polishing (CMP) process, to form shallow trench isolation regions 512 having a portion that extends above the substrate by a given amount commonly referred to a STI mesa.
• the STI mask 506 may then be removed by any well known process such as resist striping or resist ashing.
• the sacrificial oxide 504 may also be removed by any well known selective etching process.
• a tunneling dielectric region 514 is formed on the substrate 502, at 415.
• die tunneling dielectric region 514 may be formed by oxidizing the exposed surface of the substrate 502 in the memory cell array region by any well known thermal oxidation process.
• the tunneling dielectric region 514 may be formed by depositing a silicon oxynitride film by any well known chemical vapor deposition process.
• the tunneling dielectric region 514 may be formed to a thickness of about 3 to 8 nanometers.
• a first set of one or more nitride and/or the like layers 516 is formed on the tunneling dielectric region 514, at 420.
• the first set of one or more nitride or the like layers 516 is formed by depositing a nitride and or the like by any well known process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), on the tunneling dielectric region 514.
• the first nitride or the like layer 516 may include silicon-rich-nitride having an atomic ratio of silicon to nitrogen that is about 3:4 or greater.
• the thickness of the first set of one or more nitride and/or the like layers may have a thickness that is approximately one third to two thirds of the height that die tops of the shallow trench isolation regions extend above the substrate.
• a sacrificial oxide layer 518 may be formed on the first nitride layer 516 by any well known process such as oxidation.
• a portion of the first set of one or more nitride and/or the like layers and a portion of the sacrificial oxide layer are etched back 520 to the tops of the shallow trench isolation regions 512, at 425.
• the remaining portion of the sacrificial oxide layer is then removed after the etch-back process.
• a second set of one or more nitride and/or the like layers 522 is formed on the etched back first set of one or more nitride and or the like layers 520, at 430.
• the second set of one or more nitride and/or the like layers 522 is formed by depositing a nitride or the like by any well known process such as chemical vapor deposition (CVD), on the etched back first set of nitride or the like layer 520.
• the second set of nitride or the like layer 522 may include silicon-rich-nitridc having an atomic ratio of silicon to nitrogen that is about 3:4 or greater.
• portions of the first and second nitride or the like layers 520, 522, arc oxidized to form a charge trapping region 524 on the tunneling dielectric region 514 and a blocking dielectric region 526 on the charge trapping region 524, at 435.
• the nitride or silicon-rich-nitridc 520, 522 is oxidized down to the tops of the shallow trench isolation region 512 to form oxynitridc or silicon oxynitride.
• the resulting charge trapping region 524 may be formed to a thickness of about 4 to 15 nanometers and the resulting blocking dielectric region 524 may be formed to a thickness of about 3 to 8 nanometers.
• first and second nitride or the like layers advantageously increases the etch back process margin.
• the process of depositing a thin first nitride or the like layer, etching back a portion thereof, depositing a thin second nitride or the like layer and oxidizing advantageously reduces the wing height of the charge trapping region proximate the STI regions and reduces intcr-ccll coupling/interference.
• the thin second nitride or the like layer is consumed to form the blocking dielectric region, there is no additional process complications or etch back needed.
• a second nitride layer and oxidization thereof at 430-435 may be eliminated.
• the etched back first nitride layer may form the charge trapping region and a dielectric may be deposited to form the blocking dielectric region.
• a gate region 528 is formed on the blocking dielectric region 524, at 440.
• a polysilicon layer 528 is deposited, by any well known process such as chemical vapor deposition, on the oxynitridc or silicon oxynitridc layer 526.
• the process continues with various subsequent processes, such as implanting, doping, etching, cleaning and/or the like, to further form the charge trapping, blocking dielectric, and gate regions and/or one or more additional regions, such as gate, source and drain contacts, peripheral circuits, interconnects, vias, passivation layer and/or the like.
• various subsequent processes such as implanting, doping, etching, cleaning and/or the like, to further form the charge trapping, blocking dielectric, and gate regions and/or one or more additional regions, such as gate, source and drain contacts, peripheral circuits, interconnects, vias, passivation layer and/or the like.
• Figure 6A illustrates the gate stack of a CT-FET fabricated by depositing a thin first nitride or the like layer 516 that will then be partially etched back before a thin second nitride or the like layer is deposited and oxidized.
• the etch back process margin is illustrated at 610.
• Figure 6B illustrates the gate stack fabricated by depositing a thick nitride or the like layer 620 that will then be partially etched back before it is partially oxidized.
• the smaller etch back process margin for the single thick nitride or the like layer 620 is illustrated at 630.
• the larger process margin 10 of embodiments of the present technology illustrated in Figure 6A as compared to Figure 6B compensates for other process variances, thereby advantageously improving fabrication and performance of the CT-FET.
• the process of depositing a thin first nitride or the like layer 5 16, etching back a portion thereof, depositing a thin second nitride or the like layer and oxidizing advantageously reduces the wing height of the charge trapping region proximate the STI regions and reduces inter-cell coupling interference.

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• 2010
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