KR20140007824A - 전하 트랩핑 전계 효과 트랜지스터에서 공정 마진 엔지니어링 - Google Patents

전하 트랩핑 전계 효과 트랜지스터에서 공정 마진 엔지니어링 Download PDF

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Publication number
KR20140007824A
KR20140007824A KR1020137019144A KR20137019144A KR20140007824A KR 20140007824 A KR20140007824 A KR 20140007824A KR 1020137019144 A KR1020137019144 A KR 1020137019144A KR 20137019144 A KR20137019144 A KR 20137019144A KR 20140007824 A KR20140007824 A KR 20140007824A
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KR
South Korea
Prior art keywords
region
trench isolation
nitride
dielectric region
forming
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KR1020137019144A
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English (en)
Korean (ko)
Inventor
퉁-셍 첸
센칭 팡
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스펜션 엘엘씨
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Application filed by 스펜션 엘엘씨 filed Critical 스펜션 엘엘씨
Publication of KR20140007824A publication Critical patent/KR20140007824A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
KR1020137019144A 2010-12-20 2011-12-19 전하 트랩핑 전계 효과 트랜지스터에서 공정 마진 엔지니어링 Ceased KR20140007824A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/973,631 US8263458B2 (en) 2010-12-20 2010-12-20 Process margin engineering in charge trapping field effect transistors
US12/973,631 2010-12-20
PCT/US2011/065923 WO2012087974A2 (en) 2010-12-20 2011-12-19 Process margin engineering in charge trapping field effect transistors

Publications (1)

Publication Number Publication Date
KR20140007824A true KR20140007824A (ko) 2014-01-20

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020137019144A Ceased KR20140007824A (ko) 2010-12-20 2011-12-19 전하 트랩핑 전계 효과 트랜지스터에서 공정 마진 엔지니어링

Country Status (6)

Country Link
US (1) US8263458B2 (enExample)
EP (1) EP2656382A4 (enExample)
JP (1) JP5727036B2 (enExample)
KR (1) KR20140007824A (enExample)
CN (1) CN103380489B (enExample)
WO (1) WO2012087974A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
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KR20160141705A (ko) * 2014-02-06 2016-12-09 사이프레스 세미컨덕터 코포레이션 Cmos 프로세스 흐름을 이용하여 전하-트랩핑 게이트 스택을 제조하는 방법

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US8866213B2 (en) 2013-01-30 2014-10-21 Spansion Llc Non-Volatile memory with silicided bit line contacts
US9614105B2 (en) * 2013-04-22 2017-04-04 Cypress Semiconductor Corporation Charge-trap NOR with silicon-rich nitride as a charge trap layer
WO2014175202A1 (ja) * 2013-04-23 2014-10-30 ピーエスフォー ルクスコ エスエイアールエル 装置の製造方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160141705A (ko) * 2014-02-06 2016-12-09 사이프레스 세미컨덕터 코포레이션 Cmos 프로세스 흐름을 이용하여 전하-트랩핑 게이트 스택을 제조하는 방법

Also Published As

Publication number Publication date
CN103380489B (zh) 2016-08-24
EP2656382A2 (en) 2013-10-30
WO2012087974A2 (en) 2012-06-28
JP2014504015A (ja) 2014-02-13
US8263458B2 (en) 2012-09-11
JP5727036B2 (ja) 2015-06-03
EP2656382A4 (en) 2017-11-29
CN103380489A (zh) 2013-10-30
WO2012087974A3 (en) 2012-08-23
US20120156856A1 (en) 2012-06-21

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