CN103380489B - 电荷捕捉场效晶体管中的制程界限工程 - Google Patents

电荷捕捉场效晶体管中的制程界限工程 Download PDF

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Publication number
CN103380489B
CN103380489B CN201180067986.9A CN201180067986A CN103380489B CN 103380489 B CN103380489 B CN 103380489B CN 201180067986 A CN201180067986 A CN 201180067986A CN 103380489 B CN103380489 B CN 103380489B
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China
Prior art keywords
nitride layer
region
nitride
substrate
silicon
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CN201180067986.9A
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Chinese (zh)
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CN103380489A (zh
Inventor
T-S·陈
S·房
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Cypress Semiconductor Corp
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Cypress Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
CN201180067986.9A 2010-12-20 2011-12-19 电荷捕捉场效晶体管中的制程界限工程 Active CN103380489B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/973,631 US8263458B2 (en) 2010-12-20 2010-12-20 Process margin engineering in charge trapping field effect transistors
US12/973,631 2010-12-20
PCT/US2011/065923 WO2012087974A2 (en) 2010-12-20 2011-12-19 Process margin engineering in charge trapping field effect transistors

Publications (2)

Publication Number Publication Date
CN103380489A CN103380489A (zh) 2013-10-30
CN103380489B true CN103380489B (zh) 2016-08-24

Family

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Family Applications (1)

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CN201180067986.9A Active CN103380489B (zh) 2010-12-20 2011-12-19 电荷捕捉场效晶体管中的制程界限工程

Country Status (6)

Country Link
US (1) US8263458B2 (enExample)
EP (1) EP2656382A4 (enExample)
JP (1) JP5727036B2 (enExample)
KR (1) KR20140007824A (enExample)
CN (1) CN103380489B (enExample)
WO (1) WO2012087974A2 (enExample)

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KR101847629B1 (ko) * 2012-02-10 2018-04-10 삼성전자주식회사 반도체 소자
US20150255480A1 (en) * 2012-10-01 2015-09-10 Spansion Llc Method to Improve Charge Trap Flash Memory Top Oxide Quality
US8836012B2 (en) 2012-10-04 2014-09-16 Spansion Llc Spacer design to prevent trapped electrons
US8866213B2 (en) 2013-01-30 2014-10-21 Spansion Llc Non-Volatile memory with silicided bit line contacts
US9614105B2 (en) 2013-04-22 2017-04-04 Cypress Semiconductor Corporation Charge-trap NOR with silicon-rich nitride as a charge trap layer
WO2014175202A1 (ja) * 2013-04-23 2014-10-30 ピーエスフォー ルクスコ エスエイアールエル 装置の製造方法
US8993457B1 (en) * 2014-02-06 2015-03-31 Cypress Semiconductor Corporation Method of fabricating a charge-trapping gate stack using a CMOS process flow

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US7592666B2 (en) * 2003-06-04 2009-09-22 Kabushiki Kaisha Toshiba Semiconductor memory
US20100133646A1 (en) * 2010-02-03 2010-06-03 Shenqing Fang Self-aligned si rich nitride charge trap layer isolation for charge trap flash memory

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US4870470A (en) * 1987-10-16 1989-09-26 International Business Machines Corporation Non-volatile memory cell having Si rich silicon nitride charge trapping layer
US6974995B1 (en) 2001-12-27 2005-12-13 Advanced Micro Devices, Inc. Method and system for forming dual gate structures in a nonvolatile memory using a protective layer
US6808992B1 (en) 2002-05-15 2004-10-26 Spansion Llc Method and system for tailoring core and periphery cells in a nonvolatile memory
US7566929B2 (en) * 2002-07-05 2009-07-28 Samsung Electronics Co., Ltd. Nonvolatile memory devices having floating gate electrodes with nitrogen-doped layers on portions thereof
US6828212B2 (en) * 2002-10-22 2004-12-07 Atmel Corporation Method of forming shallow trench isolation structure in a semiconductor device
US6943401B1 (en) 2003-09-11 2005-09-13 Advanced Micro Devices, Inc. Flash memory cell with drain and source formed by diffusion of a dopant from a silicide
US7301193B2 (en) 2004-01-22 2007-11-27 Spansion Llc Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell
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US7029975B1 (en) 2004-05-04 2006-04-18 Advanced Mirco Devices, Inc. Method and apparatus for eliminating word line bending by source side implantation
US6987696B1 (en) 2004-07-06 2006-01-17 Advanced Micro Devices, Inc. Method of improving erase voltage distribution for a flash memory array having dummy wordlines
US7170130B2 (en) 2004-08-11 2007-01-30 Spansion Llc Memory cell with reduced DIBL and Vss resistance
US7151028B1 (en) 2004-11-04 2006-12-19 Spansion Llc Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability
US7488657B2 (en) 2005-06-17 2009-02-10 Spansion Llc Method and system for forming straight word lines in a flash memory array
US20070037371A1 (en) 2005-08-10 2007-02-15 Zhigang Wang Method of forming gate electrode structures
US7675104B2 (en) 2006-07-31 2010-03-09 Spansion Llc Integrated circuit memory system employing silicon rich layers
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US20080150011A1 (en) 2006-12-21 2008-06-26 Spansion Llc Integrated circuit system with memory system
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US7829936B2 (en) 2007-10-17 2010-11-09 Spansion Llc Split charge storage node inner spacer process
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Patent Citations (4)

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US20020168819A1 (en) * 2001-05-14 2002-11-14 Horng-Huei Tseng Flash memory with conformal floating gate and the method of making the same
CN1534768A (zh) * 2003-03-31 2004-10-06 ��ʽ���������Ƽ� 半导体器件及其制造方法
US7592666B2 (en) * 2003-06-04 2009-09-22 Kabushiki Kaisha Toshiba Semiconductor memory
US20100133646A1 (en) * 2010-02-03 2010-06-03 Shenqing Fang Self-aligned si rich nitride charge trap layer isolation for charge trap flash memory

Also Published As

Publication number Publication date
WO2012087974A3 (en) 2012-08-23
WO2012087974A2 (en) 2012-06-28
CN103380489A (zh) 2013-10-30
US8263458B2 (en) 2012-09-11
US20120156856A1 (en) 2012-06-21
EP2656382A2 (en) 2013-10-30
KR20140007824A (ko) 2014-01-20
JP5727036B2 (ja) 2015-06-03
JP2014504015A (ja) 2014-02-13
EP2656382A4 (en) 2017-11-29

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