JP2014157858A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2014157858A JP2014157858A JP2013026593A JP2013026593A JP2014157858A JP 2014157858 A JP2014157858 A JP 2014157858A JP 2013026593 A JP2013026593 A JP 2013026593A JP 2013026593 A JP2013026593 A JP 2013026593A JP 2014157858 A JP2014157858 A JP 2014157858A
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Abstract
【解決手段】表面の酸化膜が厚く、濡れ性が劣るSn−高Sb系はんだ材料に対し、表面積が低減するように形成したコの字形状のはんだ板を用いて、絶縁回路基板と半導体チップ等とのはんだ接合を行なうことで、酸化膜が少なく、ボイドが生じにくい良好なはんだ接合面の形成が可能になる。さらに、コの字形状に形成したはんだ板上に半導体チップを積層させたはんだ溶融前の状態は、半導体チップおよび絶縁回路基板のはんだ接合面中央部に隙間が設けられ、水素ガスとの接触面積が増大するため、還元現象によるはんだ接合面のクリーニング効果が高められる。
【選択図】図2
Description
この汚染を起こさないためにフラックスを使用せず、かつはんだ濡れ性を高める方法として、リフロー炉の内部に水素ガスを導入し、この水素を用いた酸素還元反応(2H2+O2→2H2O)を利用して、接合対象物の酸化膜を除去する方法が知られている(特許文献1)。
このはんだ付け方法では、はんだ及び接合対象物に対して、水素ラジカル等の遊離基ガスを供給することにより、はんだの溶融ではんだに含まれる酸化物の還元が行われ、同時に接合対象物の接合面も還元して洗浄を行う。これにより、はんだ濡れ性を良好にすることができる。
一方、近年パワー半導体モジュールの使用環境条件が厳しく、はんだ付け接合面に対する要求も、さらなる高強度・高耐熱性が必要になってきている。そこで従来用いられているSn−Ag系などのはんだ材料に代わり、機械的な接合強度に優れているSn−高Sb系はんだ材料が適用されるようになってきている。
まず特許文献1に記載されたはんだ付け方法を、従来のはんだ材に比べ表面に形成する酸化膜が厚いSn−高Sb系はんだ材料に適用した場合、板形状に凹凸を形成したはんだ板の表面積は広く、はんだ中の酸化膜量が増大するために、水素ガスとの接触面積を増大させるのみでは十分な還元処理を行なうことができない。その結果、半導体チップとはんだの接合面に酸化膜が残存するためボイドが発生し、接合状態を低下させるという課題がある。
さらに、前記状態から加熱を行ない、はんだ板が溶融した状態では、半導体装置動作時の発熱量が大きい半導体チップのはんだ接合面中央部へ、酸化物が含まれない濡れ性が良好なはんだが供給される。それゆえはんだ接合面中央部にボイドが少ない良好なはんだ接合面が形成でき、熱抵抗が低減できるため、半導体チップの性能を最大限に活用することができる。
実施の形態を通して共通の構成には同一の符号を付すものとし、重複する説明は省略する。
図1は、本発明の実施形態に係る半導体装置の製造におけるはんだ付け対象の、はんだ溶融前の全体斜視図を示している。
図1で示すパワーセルユニット10は、絶縁回路基板11と第一の半導体チップ13および第二の半導体チップ15とを電気的及び熱的に接合するために、絶縁回路基板11上の所定の接合面に第一のはんだ板12および第二のはんだ板14が載置されている。さらにそれらの上にIGBTなどの第一の半導体チップ13、およびFWDなどの第二の半導体チップ15が載置されて構成されている。
最初にコの字形状を有する第一のはんだ板12および第二のはんだ板14を準備する。続いて絶縁回路基板11の所定の接合面に第一のはんだ板12および第二のはんだ板14を載置する。さらに第一のはんだ板12および第二のはんだ板14上に、第一の半導体チップ13および第二の半導体チップ15を載置することにより、パワーセルユニット10の準備が完了する。
またはんだ板の形状をコの字形状にすることにより、接合部の各辺ごとに細長いはんだ板を複数枚用意する場合に比べ、ピックアップ等の取り扱いを容易にすることができる。
なお本発明の実施形態に係るはんだ板は、Sn−高Sb系はんだ材料で構成されている。これはSn−Ag系などの既存の鉛フリーはんだ材料に比べて機械的な接合強度に優れており、高強度・高耐熱性を備えたパワー半導体モジュールの実現に寄与することができる。一方で従来のはんだ材に比べ表面に形成する酸化膜が厚く、濡れ性で劣っているが、はんだ板をコの字形状にすることにより表面積を小さくできるため、高い酸化膜量低減の効果を得ることができる。
気密状態を維持することができるチャンバー21の内部には、ヒータなどの加熱手段(図示せず)が搭載されている加熱板22と、冷却水などの冷却手段(図示せず)が搭載されている冷却板23とが設置されている。
また、チャンバー21にはチャンバー21内部に水素ガスを供給可能とする水素ガス供給機構(図示せず)が、水素ガス供給管35及び水素ガス供給弁36を介して接続されており、はんだ付けの際の還元ガスとして供給できるようにされている。さらに、チャンバー21にはチャンバー21内部に窒素ガスを供給可能とする窒素ガス供給機構(図示せず)が、窒素ガス供給管33及び窒素ガス供給弁34を介して接続されており、チャンバー21を開放する際の置換ガスとして供給できるようにされている。
また前記パワーセルユニット10をはんだ付け処理させるチャンバー21内部の圧力が、還元性ガスで正圧状態にならないよう、圧力をベントする放出管(図示せず)が設けられた構造である。
チャンバー21内が開放されている状態で、冷却板23上で待機される搬送トレイ24上に、パワーセルユニット10をセットした後、チャンバー21を閉鎖する。次に真空ポンプを作動し、排気弁32を開放すると、チャンバー21内部のガスが排気管31より排出されて、チャンバー21内に真空状態が形成される。
次に排気弁32を閉じ、水素ガス供給弁36を開放させ、チャンバー21内部に水素ガスを供給することにより、チャンバー21内部の雰囲気を水素ガスで置換する。同時にチャンバー内部が正圧状態にならないようにするため、放出管も解放される。
次に搬送機構により搬送トレイ24が加熱板22上に移動され、パワーセルユニット10の加熱処理が行なわれる。
この時に形成する真空状態は、絶縁回路基板11と第一の半導体チップ13および第二の半導体チップ15間に挿入した、第一のはんだ板12および第二のはんだ板14内に混入しているガスを圧力差で脱気させ、ボイドを低減するための処理である。
チャンバー21内部が真空状態に達した後、再び排気弁32を閉じ、水素ガス供給弁34を開放させ、チャンバー21内部に水素ガスを供給して還元処理を行なう。
このように水素ガス中で加熱を行なうことにより、はんだ溶融前の絶縁回路基板11、第一の半導体チップ13および第二の半導体チップ15の接合面を直接還元することができ、表面のクリーニング効果が発揮されている。
さらに本実施例においては、コの字形状のはんだ材料を適用することにより、はんだ溶融前の絶縁回路基板11、第一の半導体チップ13および第二の半導体チップ15の接合面の中央部に対しても水素ガスが円滑にいきわたるため、さらに表面のクリーニング効果を高めることができる。
この場合四角形状(板状)で打ち抜かれたはんだ板を用いているため、半導体チップ裏面とSn−高Sb系はんだ材料が接触する部位に集中したボイドが発生する。このボイドは、Sn−高Sb系はんだ材料の表面に生じている酸化膜が、半導体チップ裏面の界面に現れ、接合状態を低下させていることを示している。
図6(b)は本発明に係るコの字形状に形成したはんだ板を、絶縁回路基板と半導体チップ間にセットし加熱させ、はんだ溶融時にチャンバー21内を真空状態にさせた場合のSAT画像である。
11 絶縁回路基板
11a 放熱板
11b 絶縁板
11c 回路板
12 第一のはんだ板
13 第一の半導体チップ
14 第二のはんだ板
15 第二の半導体チップ
21 チャンバー
22 加熱板
23 冷却板
24 搬送トレイ
31 排気管
32 排気弁
33 窒素ガス供給管
34 窒素ガス供給弁
35 水素ガス供給管
36 水素ガス供給弁
Claims (4)
- コの字形状を有するはんだ板を準備する工程と、
基板上に前記はんだ板を載置する工程と、
前記はんだ板上に半導体チップを載置する工程と、
還元性ガスの雰囲気中で前記はんだ板を溶融する工程と、
前記はんだ板が溶融している際に前記還元性ガスの雰囲気を大気圧より低い圧力に減圧する工程と、
を有する半導体装置の製造方法。 - 前記はんだ板がSnおよびSbを含んでいることを特徴とする、
請求項1に記載の半導体装置の製造方法。 - 前記はんだ板がSbを9〜15wt%含んでいることを特徴とする、
請求項2に記載の半導体装置の製造方法。 - 前記還元性ガスが水素ガスであることを特徴とする、
請求項1ないし3のいずれか一項に記載の半導体装置の製造方法。
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CN201410048867.4A CN103996631A (zh) | 2013-02-14 | 2014-02-12 | 半导体装置的制造方法 |
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US10879211B2 (en) | 2016-06-30 | 2020-12-29 | R.S.M. Electron Power, Inc. | Method of joining a surface-mount component to a substrate with solder that has been temporarily secured |
JP6641524B1 (ja) * | 2018-02-26 | 2020-02-05 | 新電元工業株式会社 | 半導体装置の製造方法 |
JP7078595B2 (ja) * | 2019-11-15 | 2022-05-31 | 矢崎総業株式会社 | 回路体と導電体との接続構造 |
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