JP2014050103A5 - - Google Patents

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Publication number
JP2014050103A5
JP2014050103A5 JP2013169110A JP2013169110A JP2014050103A5 JP 2014050103 A5 JP2014050103 A5 JP 2014050103A5 JP 2013169110 A JP2013169110 A JP 2013169110A JP 2013169110 A JP2013169110 A JP 2013169110A JP 2014050103 A5 JP2014050103 A5 JP 2014050103A5
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JP
Japan
Prior art keywords
memory
data items
chip
sequence
dram
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JP2013169110A
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English (en)
Japanese (ja)
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JP2014050103A (ja
JP5575310B2 (ja
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Priority claimed from GB1215425.8A external-priority patent/GB2497154B/en
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Publication of JP2014050103A publication Critical patent/JP2014050103A/ja
Publication of JP2014050103A5 publication Critical patent/JP2014050103A5/ja
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Publication of JP5575310B2 publication Critical patent/JP5575310B2/ja
Expired - Fee Related legal-status Critical Current
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JP2013169110A 2012-08-30 2013-08-16 デジタル信号処理のためのタイルベースインタリーブ処理及びデインタリーブ処理 Expired - Fee Related JP5575310B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1215425.8 2012-08-30
GB1215425.8A GB2497154B (en) 2012-08-30 2012-08-30 Tile based interleaving and de-interleaving for digital signal processing

Publications (3)

Publication Number Publication Date
JP2014050103A JP2014050103A (ja) 2014-03-17
JP2014050103A5 true JP2014050103A5 (enExample) 2014-04-24
JP5575310B2 JP5575310B2 (ja) 2014-08-20

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Family Applications (1)

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JP2013169110A Expired - Fee Related JP5575310B2 (ja) 2012-08-30 2013-08-16 デジタル信号処理のためのタイルベースインタリーブ処理及びデインタリーブ処理

Country Status (6)

Country Link
US (4) US10296456B2 (enExample)
JP (1) JP5575310B2 (enExample)
CN (1) CN103678190B (enExample)
DE (1) DE102013014168B4 (enExample)
GB (1) GB2497154B (enExample)
TW (1) TWI604726B (enExample)

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