DE102013014168B4 - Kachel-basiertes verschachteln und entschachteln für digitale signalverarbeitung - Google Patents

Kachel-basiertes verschachteln und entschachteln für digitale signalverarbeitung Download PDF

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Publication number
DE102013014168B4
DE102013014168B4 DE102013014168.0A DE102013014168A DE102013014168B4 DE 102013014168 B4 DE102013014168 B4 DE 102013014168B4 DE 102013014168 A DE102013014168 A DE 102013014168A DE 102013014168 B4 DE102013014168 B4 DE 102013014168B4
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Germany
Prior art keywords
memory
data elements
dram
addresses
tiles
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Expired - Fee Related
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DE102013014168.0A
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German (de)
English (en)
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DE102013014168A1 (de
Inventor
Paul Murrin
Adrian John Anderson
Mohammad El-Hajjar
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Imagination Technologies Ltd
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Imagination Technologies Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H03M13/6505—Memory efficient implementations

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE102013014168.0A 2012-08-30 2013-08-26 Kachel-basiertes verschachteln und entschachteln für digitale signalverarbeitung Expired - Fee Related DE102013014168B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1215425.8 2012-08-30
GB1215425.8A GB2497154B (en) 2012-08-30 2012-08-30 Tile based interleaving and de-interleaving for digital signal processing

Publications (2)

Publication Number Publication Date
DE102013014168A1 DE102013014168A1 (de) 2014-03-06
DE102013014168B4 true DE102013014168B4 (de) 2016-07-07

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DE102013014168.0A Expired - Fee Related DE102013014168B4 (de) 2012-08-30 2013-08-26 Kachel-basiertes verschachteln und entschachteln für digitale signalverarbeitung

Country Status (6)

Country Link
US (4) US10296456B2 (enExample)
JP (1) JP5575310B2 (enExample)
CN (1) CN103678190B (enExample)
DE (1) DE102013014168B4 (enExample)
GB (1) GB2497154B (enExample)
TW (1) TWI604726B (enExample)

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US12474928B2 (en) * 2020-12-22 2025-11-18 Intel Corporation Processors, methods, systems, and instructions to select and store data elements from strided data element positions in a first dimension from three source two-dimensional arrays in a result two-dimensional array
US12001887B2 (en) * 2020-12-24 2024-06-04 Intel Corporation Apparatuses, methods, and systems for instructions for aligning tiles of a matrix operations accelerator
US12137141B2 (en) * 2022-07-06 2024-11-05 Mellanox Technologies, Ltd. Patterned remote direct memory access (RDMA)
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Also Published As

Publication number Publication date
GB201215425D0 (en) 2012-10-17
US11210217B2 (en) 2021-12-28
US10296456B2 (en) 2019-05-21
US11755474B2 (en) 2023-09-12
US20220075723A1 (en) 2022-03-10
US20200242029A1 (en) 2020-07-30
CN103678190A (zh) 2014-03-26
TWI604726B (zh) 2017-11-01
US20190236006A1 (en) 2019-08-01
JP5575310B2 (ja) 2014-08-20
GB2497154B (en) 2013-10-16
CN103678190B (zh) 2016-10-26
GB2497154A (en) 2013-06-05
US20140068168A1 (en) 2014-03-06
TW201419837A (zh) 2014-05-16
US10657050B2 (en) 2020-05-19
JP2014050103A (ja) 2014-03-17
DE102013014168A1 (de) 2014-03-06

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