TWI604726B - 用於數位信號處理之以瓦狀塊為基礎的交插及解交插技術 - Google Patents
用於數位信號處理之以瓦狀塊為基礎的交插及解交插技術 Download PDFInfo
- Publication number
- TWI604726B TWI604726B TW102128080A TW102128080A TWI604726B TW I604726 B TWI604726 B TW I604726B TW 102128080 A TW102128080 A TW 102128080A TW 102128080 A TW102128080 A TW 102128080A TW I604726 B TWI604726 B TW I604726B
- Authority
- TW
- Taiwan
- Prior art keywords
- memory
- data items
- sequence
- dram
- data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/276—Interleaving address generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
- H03M13/6505—Memory efficient implementations
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Error Detection And Correction (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1215425.8A GB2497154B (en) | 2012-08-30 | 2012-08-30 | Tile based interleaving and de-interleaving for digital signal processing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201419837A TW201419837A (zh) | 2014-05-16 |
| TWI604726B true TWI604726B (zh) | 2017-11-01 |
Family
ID=47074965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW102128080A TWI604726B (zh) | 2012-08-30 | 2013-08-06 | 用於數位信號處理之以瓦狀塊為基礎的交插及解交插技術 |
Country Status (6)
| Country | Link |
|---|---|
| US (4) | US10296456B2 (enExample) |
| JP (1) | JP5575310B2 (enExample) |
| CN (1) | CN103678190B (enExample) |
| DE (1) | DE102013014168B4 (enExample) |
| GB (1) | GB2497154B (enExample) |
| TW (1) | TWI604726B (enExample) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9256531B2 (en) | 2012-06-19 | 2016-02-09 | Samsung Electronics Co., Ltd. | Memory system and SoC including linear addresss remapping logic |
| GB2497154B (en) * | 2012-08-30 | 2013-10-16 | Imagination Tech Ltd | Tile based interleaving and de-interleaving for digital signal processing |
| US10186236B2 (en) * | 2013-05-23 | 2019-01-22 | Intel Corporation | Universal codec |
| KR102354992B1 (ko) | 2015-03-02 | 2022-01-24 | 삼성전자주식회사 | 양안 시차 영상에 대한 타일 기반 렌더링 방법 및 장치 |
| KR102341267B1 (ko) | 2015-05-04 | 2021-12-20 | 삼성전자주식회사 | 양안 시차 영상에 대한 렌더링 방법 및 장치 |
| CN105681904A (zh) * | 2016-01-18 | 2016-06-15 | 四川长虹电器股份有限公司 | 提高电视响应速度的方法 |
| TWI617138B (zh) * | 2016-01-26 | 2018-03-01 | 晨星半導體股份有限公司 | 時間解交錯電路與方法 |
| CN107038122A (zh) * | 2016-02-04 | 2017-08-11 | 晨星半导体股份有限公司 | 时间解交错电路与方法 |
| US11979340B2 (en) | 2017-02-12 | 2024-05-07 | Mellanox Technologies, Ltd. | Direct data placement |
| CN110383785B (zh) * | 2017-02-27 | 2020-09-25 | 高拓讯达(北京)科技有限公司 | 在dvb-t2接收机中执行二进制数据流的时域去交织的装置 |
| US10484136B2 (en) * | 2017-06-06 | 2019-11-19 | Hughes Network Systems, Llc | High speed interleaver/deinterleaver device supporting line rate, and method thereof |
| CN109728826B (zh) * | 2017-10-27 | 2023-07-07 | 深圳市中兴微电子技术有限公司 | 一种数据交织与解交织方法和装置 |
| US10657078B1 (en) * | 2018-10-30 | 2020-05-19 | Micron Technology, Inc. | Providing information for a controller memory buffer elasticity status of a memory sub-system to a host system |
| GB202008299D0 (en) * | 2020-06-02 | 2020-07-15 | Imagination Tech Ltd | Manipulation of data in a memory |
| US12112167B2 (en) | 2020-06-27 | 2024-10-08 | Intel Corporation | Matrix data scatter and gather between rows and irregularly spaced memory locations |
| US20220188552A1 (en) * | 2020-12-11 | 2022-06-16 | Waymo Llc | Systems, Apparatus, and Methods for Reordering Image Data |
| US12474928B2 (en) * | 2020-12-22 | 2025-11-18 | Intel Corporation | Processors, methods, systems, and instructions to select and store data elements from strided data element positions in a first dimension from three source two-dimensional arrays in a result two-dimensional array |
| US12001887B2 (en) * | 2020-12-24 | 2024-06-04 | Intel Corporation | Apparatuses, methods, and systems for instructions for aligning tiles of a matrix operations accelerator |
| US12135662B2 (en) | 2022-07-06 | 2024-11-05 | Mellanox Technologies, Ltd. | Patterned direct memory access (DMA) |
| US12137141B2 (en) * | 2022-07-06 | 2024-11-05 | Mellanox Technologies, Ltd. | Patterned remote direct memory access (RDMA) |
| US12216575B2 (en) | 2022-07-06 | 2025-02-04 | Mellanox Technologies, Ltd | Patterned memory-network data transfer |
| CN115620781B (zh) * | 2022-10-18 | 2025-10-24 | 山东云海国创云计算装备产业创新中心有限公司 | 用于固态硬盘的闪存控制器配置方法、装置、设备及介质 |
| WO2025193341A1 (en) * | 2024-03-13 | 2025-09-18 | Northrop Grumman Systems Corporation | Interleaver and deinterleaver with delay memory for a transmitter or receiver |
Family Cites Families (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5802387A (en) * | 1996-12-27 | 1998-09-01 | Lucent Technologies Inc. | Efficient data transfer in a digital signal processor |
| EP1000499B1 (en) * | 1997-07-31 | 2008-12-31 | Cisco Technology, Inc. | Generation of voice messages |
| JP3738134B2 (ja) * | 1998-06-19 | 2006-01-25 | 三洋電機株式会社 | デジタル信号処理装置 |
| JP2000307440A (ja) * | 1999-04-23 | 2000-11-02 | Denso Corp | データ列変換装置,及びデータ伝送システム |
| AU5679401A (en) * | 2000-05-22 | 2001-12-03 | Yozan Inc. | Address converter, interleaver and de-interleaver |
| US6868519B2 (en) * | 2001-04-23 | 2005-03-15 | Lucent Technologies Inc. | Reducing scintillation effects for optical free-space transmission |
| US7809902B2 (en) | 2002-01-24 | 2010-10-05 | Broadcom Corporation | Method and system for copying DMA with separate strides by a modulo-n counter |
| JP3980901B2 (ja) * | 2002-02-12 | 2007-09-26 | 沖電気工業株式会社 | デジタル信号処理装置 |
| JPWO2003085838A1 (ja) * | 2002-04-05 | 2005-08-18 | ソニー株式会社 | インターリーブ装置及びインターリーブ方法、並びにデインターリーブ装置及びデインターリーブ方法 |
| GB2391337B (en) * | 2002-04-26 | 2005-06-15 | Motorola Inc | Instruction cache and method for reducing memory conflicts |
| US7600163B2 (en) * | 2003-09-23 | 2009-10-06 | Realtek Semiconductor Corp. | Convolutional interleaver and deinterleaver |
| CN100512361C (zh) | 2004-06-22 | 2009-07-08 | 中兴通讯股份有限公司 | 一种非对称数字用户线中卷积交织和解交织的实现装置 |
| CN101032085B (zh) | 2004-09-29 | 2010-06-09 | 松下电器产业株式会社 | 数据交织装置 |
| US20060236045A1 (en) | 2005-04-13 | 2006-10-19 | Analog Devices, Inc. | Apparatus for deinterleaving interleaved data using direct memory access |
| US20080028188A1 (en) * | 2006-07-25 | 2008-01-31 | Legend Silicon | Time de-interleaver implementation using sdram in a tds-ofdm receiver |
| JP2008159109A (ja) | 2006-12-21 | 2008-07-10 | Matsushita Electric Ind Co Ltd | データ転送装置 |
| US8108648B2 (en) * | 2007-06-25 | 2012-01-31 | Sonics, Inc. | Various methods and apparatus for address tiling |
| CN101237240B (zh) | 2008-02-26 | 2011-07-20 | 北京海尔集成电路设计有限公司 | 一种利用外部存储器实现卷积交织/解交织的方法及设备 |
| US20090313399A1 (en) | 2008-06-13 | 2009-12-17 | Texas Instruments Incorporated | Direct memory access channel |
| US8352834B2 (en) * | 2009-11-12 | 2013-01-08 | Broadlogic Network Technologies Inc. | High throughput interleaver / deinterleaver |
| GB2502556B (en) * | 2012-05-30 | 2017-08-02 | Imagination Tech Ltd | Noise variance estimation and interference detection |
| GB2499270B (en) * | 2012-06-07 | 2014-07-09 | Imagination Tech Ltd | Efficient demapping of constellations |
| GB2497154B (en) * | 2012-08-30 | 2013-10-16 | Imagination Tech Ltd | Tile based interleaving and de-interleaving for digital signal processing |
| GB2505446B (en) * | 2012-08-30 | 2014-08-13 | Imagination Tech Ltd | Memory address generation for digital signal processing |
| GB2513677B (en) * | 2013-10-17 | 2015-09-02 | Imagination Tech Ltd | Channel impulse response |
| GB2531367B (en) * | 2015-01-09 | 2016-12-28 | Imagination Tech Ltd | Impulsive noise rejection |
| TWI569587B (zh) * | 2015-02-06 | 2017-02-01 | 晨星半導體股份有限公司 | 解迴旋交錯器 |
| GB2536655B (en) * | 2015-03-24 | 2017-09-20 | Imagination Tech Ltd | Logging events with timestamps |
| GB2536658B (en) * | 2015-03-24 | 2017-03-22 | Imagination Tech Ltd | Controlling data flow between processors in a processing system |
| GB2536069B (en) * | 2015-03-25 | 2017-08-30 | Imagination Tech Ltd | SIMD processing module |
| US10216412B2 (en) * | 2017-02-14 | 2019-02-26 | Arm Limited | Data processing systems |
| US10387160B2 (en) * | 2017-04-01 | 2019-08-20 | Intel Corporation | Shared local memory tiling mechanism |
| US10896043B2 (en) * | 2018-09-28 | 2021-01-19 | Intel Corporation | Systems for performing instructions for fast element unpacking into 2-dimensional registers |
-
2012
- 2012-08-30 GB GB1215425.8A patent/GB2497154B/en not_active Expired - Fee Related
-
2013
- 2013-03-12 US US13/794,796 patent/US10296456B2/en active Active
- 2013-08-06 TW TW102128080A patent/TWI604726B/zh not_active IP Right Cessation
- 2013-08-16 JP JP2013169110A patent/JP5575310B2/ja not_active Expired - Fee Related
- 2013-08-26 DE DE102013014168.0A patent/DE102013014168B4/de not_active Expired - Fee Related
- 2013-08-29 CN CN201310384449.8A patent/CN103678190B/zh not_active Expired - Fee Related
-
2019
- 2019-04-11 US US16/381,268 patent/US10657050B2/en active Active
-
2020
- 2020-04-10 US US16/845,303 patent/US11210217B2/en active Active
-
2021
- 2021-11-18 US US17/529,954 patent/US11755474B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| GB201215425D0 (en) | 2012-10-17 |
| CN103678190A (zh) | 2014-03-26 |
| GB2497154A (en) | 2013-06-05 |
| TW201419837A (zh) | 2014-05-16 |
| DE102013014168B4 (de) | 2016-07-07 |
| US10296456B2 (en) | 2019-05-21 |
| US20220075723A1 (en) | 2022-03-10 |
| JP2014050103A (ja) | 2014-03-17 |
| US11755474B2 (en) | 2023-09-12 |
| US20140068168A1 (en) | 2014-03-06 |
| GB2497154B (en) | 2013-10-16 |
| JP5575310B2 (ja) | 2014-08-20 |
| US20200242029A1 (en) | 2020-07-30 |
| US10657050B2 (en) | 2020-05-19 |
| US11210217B2 (en) | 2021-12-28 |
| DE102013014168A1 (de) | 2014-03-06 |
| CN103678190B (zh) | 2016-10-26 |
| US20190236006A1 (en) | 2019-08-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI604726B (zh) | 用於數位信號處理之以瓦狀塊為基礎的交插及解交插技術 | |
| US9684592B2 (en) | Memory address generation for digital signal processing | |
| CN107992943B (zh) | 接收输入数据的方法、介质和系统、硬件逻辑及制造方法 | |
| US20190109601A1 (en) | Decoder for low-density parity-check codes | |
| CN101432710A (zh) | 改进的可置换地址的处理器及方法 | |
| US9705505B2 (en) | Reconfigurable semiconductor device | |
| US20150236723A1 (en) | Parallel VLSI architectures for constrained turbo block convolutional decoding | |
| CN111063379A (zh) | 存储器装置以及操作其以用于读取页面媒体流的方法 | |
| JP5359569B2 (ja) | メモリのアクセス方法 | |
| TWI521352B (zh) | 用於數位信號處理之記憶體存取技術 | |
| JP2003108435A (ja) | ユーザによりプログラム可能なアドレス指定モードを有するシステム及びその方法 | |
| EP4116924B1 (en) | Mapping multi-dimensional coordinates to a 1d space | |
| CN101076778A (zh) | 可编程信号处理电路和交织方法 | |
| US20240396705A1 (en) | Fully homomorphic encrypted processing acceleration | |
| JP4936223B2 (ja) | アフィン変換装置および方法 | |
| JP2004312348A (ja) | インターリーブ/デインターリーブ方法及び装置 | |
| EP4325726B1 (en) | Interleave circuit and communication device | |
| US20240396704A1 (en) | Fully homomorphic encrypted processing acceleration | |
| US7733122B2 (en) | Semiconductor device | |
| JP6863661B2 (ja) | レートデマッチング及びデインターリーブ回路 | |
| Niittylahti et al. | On Design of Parallel Memory Access Schemes for Video Coding | |
| CN105404588B (zh) | 处理器和其中生成数据存储操作的一个或多个地址的方法 | |
| CN1495897A (zh) | 集成电路设备及用于该设备的系统 | |
| CN120491885A (zh) | 运算装置及其方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |