JP2014003292A - 集積回路パッケージおよびそれを作る方法 - Google Patents

集積回路パッケージおよびそれを作る方法 Download PDF

Info

Publication number
JP2014003292A
JP2014003292A JP2013122304A JP2013122304A JP2014003292A JP 2014003292 A JP2014003292 A JP 2014003292A JP 2013122304 A JP2013122304 A JP 2013122304A JP 2013122304 A JP2013122304 A JP 2013122304A JP 2014003292 A JP2014003292 A JP 2014003292A
Authority
JP
Japan
Prior art keywords
die
adhesive layer
layer
adhesive
dielectric substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2013122304A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014003292A5 (enExample
Inventor
Paul Alan Mcconnelee
ポール・アラン・マッコネリー
Arun Virupaksha Gowda
アルン・ヴィルパクシャ・ゴウダ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of JP2014003292A publication Critical patent/JP2014003292A/ja
Publication of JP2014003292A5 publication Critical patent/JP2014003292A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H10W90/00
    • H10W42/00
    • H10P72/7402
    • H10W70/05
    • H10W70/09
    • H10W70/095
    • H10W70/60
    • H10W70/611
    • H10W70/635
    • H10W70/65
    • H10W70/685
    • H10W72/30
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305Affixing by adhesive
    • H10P72/7416
    • H10P72/7422
    • H10P72/744
    • H10W70/093
    • H10W72/01304
    • H10W72/01323
    • H10W72/01333
    • H10W72/01336
    • H10W72/01365
    • H10W72/01371
    • H10W72/0198
    • H10W72/073
    • H10W72/07338
    • H10W72/354
    • H10W72/9413
    • H10W90/734
    • H10W99/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
JP2013122304A 2012-06-15 2013-06-11 集積回路パッケージおよびそれを作る方法 Pending JP2014003292A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/524,369 2012-06-15
US13/524,369 US9117813B2 (en) 2012-06-15 2012-06-15 Integrated circuit package and method of making same

Publications (2)

Publication Number Publication Date
JP2014003292A true JP2014003292A (ja) 2014-01-09
JP2014003292A5 JP2014003292A5 (enExample) 2016-07-21

Family

ID=48578955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013122304A Pending JP2014003292A (ja) 2012-06-15 2013-06-11 集積回路パッケージおよびそれを作る方法

Country Status (6)

Country Link
US (2) US9117813B2 (enExample)
EP (1) EP2674970A3 (enExample)
JP (1) JP2014003292A (enExample)
KR (1) KR102027339B1 (enExample)
CA (1) CA2818040C (enExample)
TW (1) TWI578452B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016111350A (ja) * 2014-12-01 2016-06-20 ゼネラル・エレクトリック・カンパニイ 電子パッケージとその作製方法および使用方法
JP2017073472A (ja) * 2015-10-07 2017-04-13 株式会社ディスコ 半導体装置の製造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11128786B2 (en) * 2014-11-21 2021-09-21 Apple Inc. Bending a circuit-bearing die
US20170064821A1 (en) * 2015-08-31 2017-03-02 Kristof Darmawikarta Electronic package and method forming an electrical package
KR102294537B1 (ko) 2016-03-12 2021-08-27 닝보 써니 오포테크 코., 엘티디. 카메라 모듈, 그 감광성 부품 및 그 제조 방법
KR102555721B1 (ko) 2018-08-20 2023-07-17 삼성전자주식회사 플립 칩 본딩 방법
CN120229024B (zh) * 2025-05-29 2025-08-29 浙江鼎晶科技有限公司 一种Micro OLED的喷墨方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08306737A (ja) * 1994-10-11 1996-11-22 Martin Marietta Corp 適応相互接続層を有する回路モジュール及び製造方法
JP2009253283A (ja) * 2008-04-02 2009-10-29 General Electric Co <Ge> 取外し可能な相互接続構造体
JP2011253939A (ja) * 2010-06-02 2011-12-15 Sony Chemical & Information Device Corp ウエハのダイシング方法、接続方法及び接続構造体

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4793883A (en) 1986-07-14 1988-12-27 National Starch And Chemical Corporation Method of bonding a semiconductor chip to a substrate
US5353195A (en) 1993-07-09 1994-10-04 General Electric Company Integral power and ground structure for multi-chip modules
US5776799A (en) * 1996-11-08 1998-07-07 Samsung Electronics Co., Ltd. Lead-on-chip type semiconductor chip package using an adhesive deposited on chip active surfaces at a wafer level and method for manufacturing same
US6306680B1 (en) * 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6242282B1 (en) 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6773962B2 (en) 2001-03-15 2004-08-10 General Electric Company Microelectromechanical system device packaging method
KR100517075B1 (ko) 2003-08-11 2005-09-26 삼성전자주식회사 반도체 소자 제조 방법
US7243421B2 (en) * 2003-10-29 2007-07-17 Conductive Inkjet Technology Limited Electrical connection of components
US7101620B1 (en) * 2004-09-07 2006-09-05 National Semiconductor Corporation Thermal release wafer mount tape with B-stage adhesive
US8049338B2 (en) 2006-04-07 2011-11-01 General Electric Company Power semiconductor module and fabrication method
KR100999919B1 (ko) * 2008-09-08 2010-12-13 삼성전기주식회사 인쇄회로기판 제조 방법
EP2184774A1 (en) 2008-11-05 2010-05-12 General Electric Company Low-temperature recoverable electronic component
US7851266B2 (en) * 2008-11-26 2010-12-14 Micron Technologies, Inc. Microelectronic device wafers including an in-situ molded adhesive, molds for in-situ molding adhesives on microelectronic device wafers, and methods of molding adhesives on microelectronic device wafers
US8008125B2 (en) 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
US20110156261A1 (en) 2009-03-24 2011-06-30 Christopher James Kapusta Integrated circuit package and method of making same
US8623699B2 (en) 2010-07-26 2014-01-07 General Electric Company Method of chip package build-up
US8114712B1 (en) 2010-12-22 2012-02-14 General Electric Company Method for fabricating a semiconductor device package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08306737A (ja) * 1994-10-11 1996-11-22 Martin Marietta Corp 適応相互接続層を有する回路モジュール及び製造方法
JP2009253283A (ja) * 2008-04-02 2009-10-29 General Electric Co <Ge> 取外し可能な相互接続構造体
JP2011253939A (ja) * 2010-06-02 2011-12-15 Sony Chemical & Information Device Corp ウエハのダイシング方法、接続方法及び接続構造体

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016111350A (ja) * 2014-12-01 2016-06-20 ゼネラル・エレクトリック・カンパニイ 電子パッケージとその作製方法および使用方法
US9666516B2 (en) 2014-12-01 2017-05-30 General Electric Company Electronic packages and methods of making and using the same
JP2017073472A (ja) * 2015-10-07 2017-04-13 株式会社ディスコ 半導体装置の製造方法

Also Published As

Publication number Publication date
KR20130141387A (ko) 2013-12-26
TWI578452B (zh) 2017-04-11
CA2818040A1 (en) 2013-12-15
EP2674970A2 (en) 2013-12-18
US20150287699A1 (en) 2015-10-08
US20130334706A1 (en) 2013-12-19
TW201405724A (zh) 2014-02-01
CA2818040C (en) 2020-09-22
US9117813B2 (en) 2015-08-25
KR102027339B1 (ko) 2019-10-01
US9613932B2 (en) 2017-04-04
EP2674970A3 (en) 2014-03-26

Similar Documents

Publication Publication Date Title
US9613932B2 (en) Integrated circuit package and method of making same
EP2672789B1 (en) Ultrathin buried die module and method of manufacturing thereof
CN104465418B (zh) 一种扇出晶圆级封装方法
CN103325703B (zh) 在封装件形成期间探测芯片
US12218098B2 (en) Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate
CN103998552B (zh) 具有单片化的粘合剂层的粘合剂片材的制造方法、使用了粘合剂片材的布线基板的制造方法、半导体装置的制造方法及粘合剂片材的制造装置
CN109494182B (zh) 一种用于半导体集成工艺中超薄半导体晶圆的拿持方法
US10607929B2 (en) Electronics package having a self-aligning interconnect assembly and method of making same
JP5496692B2 (ja) 半導体モジュールの製造方法
US8653670B2 (en) Electrical interconnect for an integrated circuit package and method of making same
JP2004193497A (ja) チップサイズパッケージおよびその製造方法
US20100112786A1 (en) Method of manufacturing semiconductor device
TWI425580B (zh) 製造半導體晶片封裝模組之方法
JP5023664B2 (ja) 半導体装置の製造方法
CN101807532A (zh) 一种超薄芯片的倒装式封装方法以及封装体
JP2007294575A (ja) 半導体装置の製造方法
Sterken et al. High yield embedding of 30μm thin chips in a flexible PCB using a photopatternable polyimide based Ultra-Thin Chip package (UTCP)
JP2024154576A (ja) ダイアタッチフィルム及び半導体装置の製造方法
JP2012074715A (ja) 接着シート

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160601

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160601

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170425

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170509

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170710

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170919

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20171127

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20180130